diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-30 04:09:26 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 08:13:42 -0400 |
| commit | 115103a9fe5c7b03149af7ea13f837c5e71924be (patch) | |
| tree | 8a18576acc975b4af9c5b85e35d4e4dfeec08c13 /arch/blackfin/mach-bf537 | |
| parent | 3dd666067d2b285724c828946e83100ea4c43d4b (diff) | |
Blackfin: bf533/bf537/bf561: convert to BFIN_IRQ helper
This brings the parts in line with newer ones, and makes things easier
to read at a glance.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/irq.h | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h index 09234b75aa77..fe2223b5dd52 100644 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ b/arch/blackfin/mach-bf537/include/mach/irq.h | |||
| @@ -11,39 +11,39 @@ | |||
| 11 | 11 | ||
| 12 | #define NR_PERI_INTS 32 | 12 | #define NR_PERI_INTS 32 |
| 13 | 13 | ||
| 14 | #define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ | 14 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
| 15 | #define IRQ_DMA_ERROR 8 /* DMA Error (general) */ | 15 | #define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ |
| 16 | #define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */ | 16 | #define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */ |
| 17 | #define IRQ_RTC 10 /* RTC Interrupt */ | 17 | #define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */ |
| 18 | #define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */ | 18 | #define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */ |
| 19 | #define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */ | 19 | #define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */ |
| 20 | #define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */ | 20 | #define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */ |
| 21 | #define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */ | 21 | #define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */ |
| 22 | #define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */ | 22 | #define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */ |
| 23 | #define IRQ_TWI 16 /* TWI Interrupt */ | 23 | #define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */ |
| 24 | #define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */ | 24 | #define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */ |
| 25 | #define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */ | 25 | #define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */ |
| 26 | #define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */ | 26 | #define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */ |
| 27 | #define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */ | 27 | #define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */ |
| 28 | #define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */ | 28 | #define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */ |
| 29 | #define IRQ_CAN_RX 22 /* CAN Receive Interrupt */ | 29 | #define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */ |
| 30 | #define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */ | 30 | #define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */ |
| 31 | #define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */ | 31 | #define IRQ_MAC_RX BFIN_IRQ(17) /* DMA1 (Ethernet RX) Interrupt */ |
| 32 | #define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */ | 32 | #define IRQ_MAC_TX BFIN_IRQ(18) /* DMA2 (Ethernet TX) Interrupt */ |
| 33 | #define IRQ_TIMER0 26 /* Timer 0 */ | 33 | #define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */ |
| 34 | #define IRQ_TIMER1 27 /* Timer 1 */ | 34 | #define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */ |
| 35 | #define IRQ_TIMER2 28 /* Timer 2 */ | 35 | #define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */ |
| 36 | #define IRQ_TIMER3 29 /* Timer 3 */ | 36 | #define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */ |
| 37 | #define IRQ_TIMER4 30 /* Timer 4 */ | 37 | #define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */ |
| 38 | #define IRQ_TIMER5 31 /* Timer 5 */ | 38 | #define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */ |
| 39 | #define IRQ_TIMER6 32 /* Timer 6 */ | 39 | #define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */ |
| 40 | #define IRQ_TIMER7 33 /* Timer 7 */ | 40 | #define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */ |
| 41 | #define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ | 41 | #define IRQ_PROG_INTA BFIN_IRQ(27) /* PF Ports F&G (PF15:0) Interrupt A */ |
| 42 | #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ | 42 | #define IRQ_PORTG_INTB BFIN_IRQ(28) /* PF Port G (PF15:0) Interrupt B */ |
| 43 | #define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */ | 43 | #define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */ |
| 44 | #define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */ | 44 | #define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */ |
| 45 | #define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ | 45 | #define IRQ_PROG_INTB BFIN_IRQ(31) /* PF Ports F (PF15:0) Interrupt B */ |
| 46 | #define IRQ_WATCH 38 /* Watch Dog Timer */ | 46 | #define IRQ_WATCH BFIN_IRQ(32) /* Watch Dog Timer */ |
| 47 | 47 | ||
| 48 | #define SYS_IRQS 39 | 48 | #define SYS_IRQS 39 |
| 49 | 49 | ||