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authorYi Li <yi.li@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit6a01f230339321292cf065551f8cf55361052461 (patch)
tree7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf537/include/mach/irq.h
parent5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff)
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach/irq.h')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2e68a8a1e730..b2a71d5d4e5f 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -82,14 +82,14 @@
82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
85#define IRQ_TMR0 26 /*Timer 0 */ 85#define IRQ_TIMER0 26 /*Timer 0 */
86#define IRQ_TMR1 27 /*Timer 1 */ 86#define IRQ_TIMER1 27 /*Timer 1 */
87#define IRQ_TMR2 28 /*Timer 2 */ 87#define IRQ_TIMER2 28 /*Timer 2 */
88#define IRQ_TMR3 29 /*Timer 3 */ 88#define IRQ_TIMER3 29 /*Timer 3 */
89#define IRQ_TMR4 30 /*Timer 4 */ 89#define IRQ_TIMER4 30 /*Timer 4 */
90#define IRQ_TMR5 31 /*Timer 5 */ 90#define IRQ_TIMER5 31 /*Timer 5 */
91#define IRQ_TMR6 32 /*Timer 6 */ 91#define IRQ_TIMER6 32 /*Timer 6 */
92#define IRQ_TMR7 33 /*Timer 7 */ 92#define IRQ_TIMER7 33 /*Timer 7 */
93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
@@ -195,16 +195,16 @@
195#define IRQ_CAN_TX_POS 0 195#define IRQ_CAN_TX_POS 0
196#define IRQ_MAC_RX_POS 4 196#define IRQ_MAC_RX_POS 4
197#define IRQ_MAC_TX_POS 8 197#define IRQ_MAC_TX_POS 8
198#define IRQ_TMR0_POS 12 198#define IRQ_TIMER0_POS 12
199#define IRQ_TMR1_POS 16 199#define IRQ_TIMER1_POS 16
200#define IRQ_TMR2_POS 20 200#define IRQ_TIMER2_POS 20
201#define IRQ_TMR3_POS 24 201#define IRQ_TIMER3_POS 24
202#define IRQ_TMR4_POS 28 202#define IRQ_TIMER4_POS 28
203 203
204/* IAR3 BIT FIELDS*/ 204/* IAR3 BIT FIELDS*/
205#define IRQ_TMR5_POS 0 205#define IRQ_TIMER5_POS 0
206#define IRQ_TMR6_POS 4 206#define IRQ_TIMER6_POS 4
207#define IRQ_TMR7_POS 8 207#define IRQ_TIMER7_POS 8
208#define IRQ_PROG_INTA_POS 12 208#define IRQ_PROG_INTA_POS 12
209#define IRQ_PORTG_INTB_POS 16 209#define IRQ_PORTG_INTB_POS 16
210#define IRQ_MEM_DMA0_POS 20 210#define IRQ_MEM_DMA0_POS 20