diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-20 13:20:21 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:59 -0500 |
| commit | 00d2460454676344a55a03f03fa284ad69325592 (patch) | |
| tree | 7885d8dcdeb1ffc026bc4888e1074ce7b8133c7a /arch/blackfin/mach-bf537/include/mach/defBF534.h | |
| parent | c6feb7682885f732a264ef589ee44edb1a3d45f2 (diff) | |
Blackfin: unify DMA masks
Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach/defBF534.h')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 868e1a139944..066d5c261f47 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -1584,34 +1584,6 @@ | |||
| 1584 | #define BGSTAT 0x0020 /* Bus Grant Status */ | 1584 | #define BGSTAT 0x0020 /* Bus Grant Status */ |
| 1585 | 1585 | ||
| 1586 | /* ************************** DMA CONTROLLER MASKS ********************************/ | 1586 | /* ************************** DMA CONTROLLER MASKS ********************************/ |
| 1587 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | ||
| 1588 | #define DMAEN 0x0001 /* DMA Channel Enable */ | ||
| 1589 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | ||
| 1590 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ | ||
| 1591 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ | ||
| 1592 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ | ||
| 1593 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ | ||
| 1594 | #define RESTART 0x0020 /* DMA Buffer Clear */ | ||
| 1595 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ | ||
| 1596 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | ||
| 1597 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1598 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1599 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1600 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1601 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1602 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1603 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1604 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1605 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1606 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1607 | #define NDSIZE 0x0900 /* Next Descriptor Size */ | ||
| 1608 | |||
| 1609 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
| 1610 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1611 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1612 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1613 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1614 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1615 | 1587 | ||
| 1616 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | 1588 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ |
| 1617 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | 1589 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ |
| @@ -1629,12 +1601,6 @@ | |||
| 1629 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | 1601 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ |
| 1630 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | 1602 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ |
| 1631 | 1603 | ||
| 1632 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | ||
| 1633 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ | ||
| 1634 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ | ||
| 1635 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | ||
| 1636 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | ||
| 1637 | |||
| 1638 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | 1604 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ |
| 1639 | /* PPI_CONTROL Masks */ | 1605 | /* PPI_CONTROL Masks */ |
| 1640 | #define PORT_EN 0x0001 /* PPI Port Enable */ | 1606 | #define PORT_EN 0x0001 /* PPI Port Enable */ |