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authorYi Li <yi.li@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit6a01f230339321292cf065551f8cf55361052461 (patch)
tree7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf537/include/mach/cdefBF534.h
parent5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff)
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach/cdefBF534.h')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index f3416923be69..5f8b5f845be6 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1783,7 +1783,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1783 if (val == bfin_read_PLL_CTL()) 1783 if (val == bfin_read_PLL_CTL())
1784 return; 1784 return;
1785 1785
1786 local_irq_save(flags); 1786 local_irq_save_hw(flags);
1787 /* Enable the PLL Wakeup bit in SIC IWR */ 1787 /* Enable the PLL Wakeup bit in SIC IWR */
1788 iwr = bfin_read32(SIC_IWR); 1788 iwr = bfin_read32(SIC_IWR);
1789 /* Only allow PPL Wakeup) */ 1789 /* Only allow PPL Wakeup) */
@@ -1794,7 +1794,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1794 asm("IDLE;"); 1794 asm("IDLE;");
1795 1795
1796 bfin_write32(SIC_IWR, iwr); 1796 bfin_write32(SIC_IWR, iwr);
1797 local_irq_restore(flags); 1797 local_irq_restore_hw(flags);
1798} 1798}
1799 1799
1800/* Writing to VR_CTL initiates a PLL relock sequence. */ 1800/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1805,7 +1805,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1805 if (val == bfin_read_VR_CTL()) 1805 if (val == bfin_read_VR_CTL())
1806 return; 1806 return;
1807 1807
1808 local_irq_save(flags); 1808 local_irq_save_hw(flags);
1809 /* Enable the PLL Wakeup bit in SIC IWR */ 1809 /* Enable the PLL Wakeup bit in SIC IWR */
1810 iwr = bfin_read32(SIC_IWR); 1810 iwr = bfin_read32(SIC_IWR);
1811 /* Only allow PPL Wakeup) */ 1811 /* Only allow PPL Wakeup) */
@@ -1816,7 +1816,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1816 asm("IDLE;"); 1816 asm("IDLE;");
1817 1817
1818 bfin_write32(SIC_IWR, iwr); 1818 bfin_write32(SIC_IWR, iwr);
1819 local_irq_restore(flags); 1819 local_irq_restore_hw(flags);
1820} 1820}
1821 1821
1822#endif /* _CDEF_BF534_H */ 1822#endif /* _CDEF_BF534_H */