Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index d9b411adf6a7..b1d4b91b7aed 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -100,8 +100,8 @@ ENTRY(__start)
         R0 = R1;
 
         /* Turn off the icache */
-        p0.l = (IMEM_CONTROL & 0xFFFF);
-        p0.h = (IMEM_CONTROL >> 16);
+        p0.l = LO(IMEM_CONTROL);
+        p0.h = HI(IMEM_CONTROL);
         R1 = [p0];
         R0 = ~ENICPLB;
         R0 = R0 & R1;
@@ -118,8 +118,8 @@ ENTRY(__start)
 #endif
 
         /* Turn off the dcache */
-        p0.l = (DMEM_CONTROL & 0xFFFF);
-        p0.h = (DMEM_CONTROL >> 16);
+        p0.l = LO(DMEM_CONTROL);
+        p0.h = HI(DMEM_CONTROL);
         R1 = [p0];
         R0 = ~ENDCPLB;
         R0 = R0 & R1;
@@ -436,8 +436,8 @@ ENTRY(_start_dma_code)
         w[p0] = r0.l;
         ssync;
 
-        p0.l = (EBIU_SDBCTL & 0xFFFF);
-        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        p0.l = LO(EBIU_SDBCTL);
+        p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
         r0 = mem_SDBCTL;
         w[p0] = r0.l;
         ssync;