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authorMike Frysinger <michael.frysinger@analog.com>2007-06-11 03:31:30 -0400
committerBryan Wu <bryan.wu@analog.com>2007-06-11 03:31:30 -0400
commit83a5c3e3218f138b1a99f787c76e380d6a6ecec9 (patch)
treed71fb83fb0406af38d4e3266cb2d54dabb1bb3eb /arch/blackfin/mach-bf537/head.S
parent16983de0cec7b93cc2568f96909d4ea7c118bd8a (diff)
Blackfin arch: unify differences between our diff head.S files -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf537/head.S')
-rw-r--r--arch/blackfin/mach-bf537/head.S22
1 files changed, 12 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 2c2652bee7e5..3f490bfb73fa 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -40,7 +40,7 @@
40.extern ___bss_start 40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 41.extern _bf53x_relocate_l1_mem
42 42
43#define INITIAL_STACK 0xFFB01000 43#define INITIAL_STACK 0xFFB01000
44 44
45.text 45.text
46 46
@@ -48,12 +48,14 @@ ENTRY(__start)
48ENTRY(__stext) 48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */ 49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0; 50 R7 = R0;
51 /* Set the SYSCFG register */ 51 /* Set the SYSCFG register:
52 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
53 */
52 R0 = 0x36; 54 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ 55 SYSCFG = R0;
54 R0 = 0; 56 R0 = 0;
55 57
56 /* Clear Out All the data and pointer Registers*/ 58 /* Clear Out All the data and pointer Registers */
57 R1 = R0; 59 R1 = R0;
58 R2 = R0; 60 R2 = R0;
59 R3 = R0; 61 R3 = R0;
@@ -75,7 +77,7 @@ ENTRY(__stext)
75 L2 = r0; 77 L2 = r0;
76 L3 = r0; 78 L3 = r0;
77 79
78 /* Clear Out All the DAG Registers*/ 80 /* Clear Out All the DAG Registers */
79 B0 = r0; 81 B0 = r0;
80 B1 = r0; 82 B1 = r0;
81 B2 = r0; 83 B2 = r0;
@@ -191,7 +193,7 @@ ENTRY(__stext)
191 193
192 p0.h = hi(UART_DLL); 194 p0.h = hi(UART_DLL);
193 p0.l = lo(UART_DLL); 195 p0.l = lo(UART_DLL);
194 r0 = 0x00(Z); 196 r0 = 0x0(Z);
195 w[p0] = r0.L; 197 w[p0] = r0.L;
196 ssync; 198 ssync;
197 199
@@ -218,6 +220,7 @@ ENTRY(__stext)
218#if CONFIG_BFIN_KERNEL_CLOCK 220#if CONFIG_BFIN_KERNEL_CLOCK
219 call _start_dma_code; 221 call _start_dma_code;
220#endif 222#endif
223
221 /* Code for initializing Async memory banks */ 224 /* Code for initializing Async memory banks */
222 225
223 p2.h = hi(EBIU_AMBCTL1); 226 p2.h = hi(EBIU_AMBCTL1);
@@ -291,7 +294,7 @@ ENTRY(_real_start)
291 p2.h = ___bss_stop; 294 p2.h = ___bss_stop;
292 r0 = 0; 295 r0 = 0;
293 p2 -= p1; 296 p2 -= p1;
294 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2; 297 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
295.L_clear_bss: 298.L_clear_bss:
296 B[p1++] = r0; 299 B[p1++] = r0;
297 300
@@ -306,7 +309,7 @@ ENTRY(_real_start)
306 r0 = r0 >> 1; 309 r0 = r0 >> 1;
307 p2 = r0; 310 p2 = r0;
308 r0 = 0; 311 r0 = 0;
309 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2; 312 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
310.L_clear_zero: 313.L_clear_zero:
311 W[p1++] = r0; 314 W[p1++] = r0;
312 315
@@ -328,9 +331,8 @@ ENTRY(_real_start)
328 r1 = p3; 331 r1 = p3;
329 [p1] = r1; 332 [p1] = r1;
330 333
331
332 /* 334 /*
333 * load the current thread pointer and stack 335 * load the current thread pointer and stack
334 */ 336 */
335 r1.l = _init_thread_union; 337 r1.l = _init_thread_union;
336 r1.h = _init_thread_union; 338 r1.h = _init_thread_union;