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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /arch/blackfin/mach-bf537/boards/pnav10.c
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/boards/pnav10.c')
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diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
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@@ -0,0 +1,523 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h>
39#endif
40#include <asm/irq.h>
41#include <asm/bfin5xx_spi.h>
42#include <linux/usb_sl811.h>
43
44#include <linux/spi/ad7877.h>
45
46/*
47 * Name the Board for the /proc/cpuinfo
48 */
49char *bfin_board_name = "PNAV-1.0";
50
51/*
52 * Driver needs to know address, irq and flag pin.
53 */
54
55#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
56static struct resource bfin_pcmcia_cf_resources[] = {
57 {
58 .start = 0x20310000, /* IO PORT */
59 .end = 0x20312000,
60 .flags = IORESOURCE_MEM,
61 },{
62 .start = 0x20311000, /* Attribute Memeory */
63 .end = 0x20311FFF,
64 .flags = IORESOURCE_MEM,
65 },{
66 .start = IRQ_PF4,
67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{
70 .start = 6, /* Card Detect PF6 */
71 .end = 6,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device bfin_pcmcia_cf_device = {
77 .name = "bfin_cf_pcmcia",
78 .id = -1,
79 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
80 .resource = bfin_pcmcia_cf_resources,
81};
82#endif
83
84#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
85static struct platform_device rtc_device = {
86 .name = "rtc-bfin",
87 .id = -1,
88};
89#endif
90
91#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
92static struct resource smc91x_resources[] = {
93 {
94 .name = "smc91x-regs",
95 .start = 0x20300300,
96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM,
98 },{
99
100 .start = IRQ_PF7,
101 .end = IRQ_PF7,
102 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
103 },
104};
105static struct platform_device smc91x_device = {
106 .name = "smc91x",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(smc91x_resources),
109 .resource = smc91x_resources,
110};
111#endif
112
113#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
114static struct resource sl811_hcd_resources[] = {
115 {
116 .start = 0x20340000,
117 .end = 0x20340000,
118 .flags = IORESOURCE_MEM,
119 },{
120 .start = 0x20340004,
121 .end = 0x20340004,
122 .flags = IORESOURCE_MEM,
123 },{
124 .start = CONFIG_USB_SL811_BFIN_IRQ,
125 .end = CONFIG_USB_SL811_BFIN_IRQ,
126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
127 },
128};
129
130#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
131void sl811_port_power(struct device *dev, int is_on)
132{
133 unsigned short mask = (1 << CONFIG_USB_SL811_BFIN_GPIO_VBUS);
134
135 bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
136 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
137
138 if (is_on)
139 bfin_write_FIO_FLAG_S(mask);
140 else
141 bfin_write_FIO_FLAG_C(mask);
142}
143#endif
144
145static struct sl811_platform_data sl811_priv = {
146 .potpg = 10,
147 .power = 250, /* == 500mA */
148#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
149 .port_power = &sl811_port_power,
150#endif
151};
152
153static struct platform_device sl811_hcd_device = {
154 .name = "sl811-hcd",
155 .id = 0,
156 .dev = {
157 .platform_data = &sl811_priv,
158 },
159 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
160 .resource = sl811_hcd_resources,
161};
162#endif
163
164#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
165static struct resource isp1362_hcd_resources[] = {
166 {
167 .start = 0x20360000,
168 .end = 0x20360000,
169 .flags = IORESOURCE_MEM,
170 },{
171 .start = 0x20360004,
172 .end = 0x20360004,
173 .flags = IORESOURCE_MEM,
174 },{
175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
178 },
179};
180
181static struct isp1362_platform_data isp1362_priv = {
182 .sel15Kres = 1,
183 .clknotstop = 0,
184 .oc_enable = 0,
185 .int_act_high = 0,
186 .int_edge_triggered = 0,
187 .remote_wakeup_connected = 0,
188 .no_power_switching = 1,
189 .power_switching_mode = 0,
190};
191
192static struct platform_device isp1362_hcd_device = {
193 .name = "isp1362-hcd",
194 .id = 0,
195 .dev = {
196 .platform_data = &isp1362_priv,
197 },
198 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
199 .resource = isp1362_hcd_resources,
200};
201#endif
202
203#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
204static struct platform_device bfin_mac_device = {
205 .name = "bfin_mac",
206};
207#endif
208
209#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
210static struct resource net2272_bfin_resources[] = {
211 {
212 .start = 0x20300000,
213 .end = 0x20300000 + 0x100,
214 .flags = IORESOURCE_MEM,
215 },{
216 .start = IRQ_PF7,
217 .end = IRQ_PF7,
218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
219 },
220};
221
222static struct platform_device net2272_bfin_device = {
223 .name = "net2272",
224 .id = -1,
225 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
226 .resource = net2272_bfin_resources,
227};
228#endif
229
230#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
231/* all SPI peripherals info goes here */
232
233#if defined(CONFIG_MTD_M25P80) \
234 || defined(CONFIG_MTD_M25P80_MODULE)
235static struct mtd_partition bfin_spi_flash_partitions[] = {
236 {
237 .name = "bootloader",
238 .size = 0x00020000,
239 .offset = 0,
240 .mask_flags = MTD_CAP_ROM
241 },{
242 .name = "kernel",
243 .size = 0xe0000,
244 .offset = 0x20000
245 },{
246 .name = "file system",
247 .size = 0x700000,
248 .offset = 0x00100000,
249 }
250};
251
252static struct flash_platform_data bfin_spi_flash_data = {
253 .name = "m25p80",
254 .parts = bfin_spi_flash_partitions,
255 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
256 .type = "m25p64",
257};
258
259/* SPI flash chip (m25p64) */
260static struct bfin5xx_spi_chip spi_flash_chip_info = {
261 .enable_dma = 0, /* use dma transfer with this chip*/
262 .bits_per_word = 8,
263};
264#endif
265
266#if defined(CONFIG_SPI_ADC_BF533) \
267 || defined(CONFIG_SPI_ADC_BF533_MODULE)
268/* SPI ADC chip */
269static struct bfin5xx_spi_chip spi_adc_chip_info = {
270 .enable_dma = 1, /* use dma transfer with this chip*/
271 .bits_per_word = 16,
272};
273#endif
274
275#if defined(CONFIG_SND_BLACKFIN_AD1836) \
276 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
277static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
278 .enable_dma = 0,
279 .bits_per_word = 16,
280};
281#endif
282
283#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
284static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
285 .enable_dma = 0,
286 .bits_per_word = 16,
287};
288#endif
289
290#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
291static struct bfin5xx_spi_chip spi_mmc_chip_info = {
292 .enable_dma = 1,
293 .bits_per_word = 8,
294};
295#endif
296
297#if defined(CONFIG_PBX)
298static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
299 .ctl_reg = 0x4, /* send zero */
300 .enable_dma = 0,
301 .bits_per_word = 8,
302 .cs_change_per_word = 1,
303};
304#endif
305
306
307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
308static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
309 .cs_change_per_word = 1,
310 .enable_dma = 0,
311 .bits_per_word = 16,
312};
313
314static const struct ad7877_platform_data bfin_ad7877_ts_info = {
315 .model = 7877,
316 .vref_delay_usecs = 50, /* internal, no capacitor */
317 .x_plate_ohms = 419,
318 .y_plate_ohms = 486,
319 .pressure_max = 1000,
320 .pressure_min = 0,
321 .stopacq_polarity = 1,
322 .first_conversion_delay = 3,
323 .acquisition_time = 1,
324 .averaging = 1,
325 .pen_down_acc_interval = 1,
326};
327#endif
328
329static struct spi_board_info bfin_spi_board_info[] __initdata = {
330#if defined(CONFIG_MTD_M25P80) \
331 || defined(CONFIG_MTD_M25P80_MODULE)
332 {
333 /* the modalias must be the same as spi device driver name */
334 .modalias = "m25p80", /* Name of spi_driver for this device */
335 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
336 .bus_num = 1, /* Framework bus number */
337 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
338 .platform_data = &bfin_spi_flash_data,
339 .controller_data = &spi_flash_chip_info,
340 .mode = SPI_MODE_3,
341 },
342#endif
343
344#if defined(CONFIG_SPI_ADC_BF533) \
345 || defined(CONFIG_SPI_ADC_BF533_MODULE)
346 {
347 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
348 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
349 .bus_num = 1, /* Framework bus number */
350 .chip_select = 1, /* Framework chip select. */
351 .platform_data = NULL, /* No spi_driver specific config */
352 .controller_data = &spi_adc_chip_info,
353 },
354#endif
355
356#if defined(CONFIG_SND_BLACKFIN_AD1836) \
357 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
358 {
359 .modalias = "ad1836-spi",
360 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
361 .bus_num = 1,
362 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
363 .controller_data = &ad1836_spi_chip_info,
364 },
365#endif
366#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
367 {
368 .modalias = "ad9960-spi",
369 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
370 .bus_num = 1,
371 .chip_select = 1,
372 .controller_data = &ad9960_spi_chip_info,
373 },
374#endif
375#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
376 {
377 .modalias = "spi_mmc_dummy",
378 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
379 .bus_num = 1,
380 .chip_select = 7,
381 .platform_data = NULL,
382 .controller_data = &spi_mmc_chip_info,
383 .mode = SPI_MODE_3,
384 },
385 {
386 .modalias = "spi_mmc",
387 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
388 .bus_num = 1,
389 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
390 .platform_data = NULL,
391 .controller_data = &spi_mmc_chip_info,
392 .mode = SPI_MODE_3,
393 },
394#endif
395#if defined(CONFIG_PBX)
396 {
397 .modalias = "fxs-spi",
398 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
399 .bus_num = 1,
400 .chip_select = 3,
401 .controller_data= &spi_si3xxx_chip_info,
402 .mode = SPI_MODE_3,
403 },
404 {
405 .modalias = "fxo-spi",
406 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
407 .bus_num = 1,
408 .chip_select = 2,
409 .controller_data= &spi_si3xxx_chip_info,
410 .mode = SPI_MODE_3,
411 },
412#endif
413#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
414{
415 .modalias = "ad7877",
416 .platform_data = &bfin_ad7877_ts_info,
417 .irq = IRQ_PF2,
418 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
419 .bus_num = 1,
420 .chip_select = 5,
421 .controller_data = &spi_ad7877_chip_info,
422},
423#endif
424
425};
426
427/* SPI controller data */
428static struct bfin5xx_spi_master spi_bfin_master_info = {
429 .num_chipselect = 8,
430 .enable_dma = 1, /* master has the ability to do dma transfer */
431};
432
433static struct platform_device spi_bfin_master_device = {
434 .name = "bfin-spi-master",
435 .id = 1, /* Bus number */
436 .dev = {
437 .platform_data = &spi_bfin_master_info, /* Passed to driver */
438 },
439};
440#endif /* spi master and devices */
441
442#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
443static struct platform_device bfin_fb_device = {
444 .name = "bf537-fb",
445};
446#endif
447
448#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
449static struct resource bfin_uart_resources[] = {
450 {
451 .start = 0xFFC00400,
452 .end = 0xFFC004FF,
453 .flags = IORESOURCE_MEM,
454 },{
455 .start = 0xFFC02000,
456 .end = 0xFFC020FF,
457 .flags = IORESOURCE_MEM,
458 },
459};
460
461static struct platform_device bfin_uart_device = {
462 .name = "bfin-uart",
463 .id = 1,
464 .num_resources = ARRAY_SIZE(bfin_uart_resources),
465 .resource = bfin_uart_resources,
466};
467#endif
468
469
470static struct platform_device *stamp_devices[] __initdata = {
471#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
472 &bfin_pcmcia_cf_device,
473#endif
474
475#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
476 &rtc_device,
477#endif
478
479#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
480 &sl811_hcd_device,
481#endif
482
483#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
484 &isp1362_hcd_device,
485#endif
486
487#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
488 &smc91x_device,
489#endif
490
491#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
492 &bfin_mac_device,
493#endif
494
495#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
496 &net2272_bfin_device,
497#endif
498
499#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
500 &spi_bfin_master_device,
501#endif
502
503#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
504 &bfin_fb_device,
505#endif
506
507#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
508 &bfin_uart_device,
509#endif
510};
511
512static int __init stamp_init(void)
513{
514 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
515 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
516#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
517 spi_register_board_info(bfin_spi_board_info,
518 ARRAY_SIZE(bfin_spi_board_info));
519#endif
520 return 0;
521}
522
523arch_initcall(stamp_init);
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