blackfin architecture

This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix!  Tinyboards.

The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000.  Since then ADI has put this core into its Blackfin
processor family of devices.  The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.

The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf

The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc

This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/

We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel

[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 141 insertions, 0 deletions

diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
new file mode 100644
index 000000000000..cc9ae38a4dda
--- /dev/null
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -0,0 +1,141 @@
+if (BF537 || BF534 || BF536)
+
+menu "BF537 Specific Configuration"
+
+comment "PORT F/G Selection"
+choice
+        prompt "Select BF537/6/4 default GPIO PFx PORTx"
+        help
+          Quick Hack for BF537/6/4 default GPIO PFx PORTF.
+
+config BF537_PORT_F
+        bool "Select BF537/6/4 default GPIO PFx PORTF"
+        depends on (BF537 || BF536 || BF534)
+        help
+          Quick Hack for BF537/6/4 default GPIO PFx PORTF.
+
+config BF537_PORT_G
+        bool "Select BF537/6/4 default GPIO PFx PORTG"
+        depends on (BF537 || BF536 || BF534)
+        help
+          Quick Hack for BF537/6/4 default GPIO PFx PORTG.
+
+config BF537_PORT_H
+        bool "Select BF537/6/4 default GPIO PFx PORTH"
+        depends on (BF537 || BF536 || BF534)
+        help
+          Quick Hack for BF537/6/4 default GPIO PFx PORTH
+          Use only when Blackfin EMAC support is not required.
+
+endchoice
+
+comment "Interrupt Priority Assignment"
+menu "Priority"
+
+config IRQ_PLL_WAKEUP
+        int "IRQ_PLL_WAKEUP"
+        default 7
+config IRQ_DMA_ERROR
+        int "IRQ_DMA_ERROR Generic"
+        default 7
+config IRQ_ERROR
+        int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
+        default 7
+config IRQ_RTC
+        int "IRQ_RTC"
+        default 8
+config IRQ_PPI
+        int "IRQ_PPI"
+        default 8
+config IRQ_SPORT0_RX
+        int "IRQ_SPORT0_RX"
+        default 9
+config IRQ_SPORT0_TX
+        int "IRQ_SPORT0_TX"
+        default 9
+config IRQ_SPORT1_RX
+        int "IRQ_SPORT1_RX"
+        default 9
+config IRQ_SPORT1_TX
+        int "IRQ_SPORT1_TX"
+        default 9
+config IRQ_TWI
+        int "IRQ_TWI"
+        default 10
+config IRQ_SPI
+        int "IRQ_SPI"
+        default 10
+config IRQ_UART0_RX
+        int "IRQ_UART0_RX"
+        default 10
+config IRQ_UART0_TX
+        int "IRQ_UART0_TX"
+        default 10
+config IRQ_UART1_RX
+        int "IRQ_UART1_RX"
+        default 10
+config IRQ_UART1_TX
+        int "IRQ_UART1_TX"
+        default 10
+config IRQ_CAN_RX
+        int "IRQ_CAN_RX"
+        default 11
+config IRQ_CAN_TX
+        int "IRQ_CAN_TX"
+        default 11
+config IRQ_MAC_RX
+        int "IRQ_MAC_RX"
+        default 11
+config IRQ_MAC_TX
+        int "IRQ_MAC_TX"
+        default 11
+config IRQ_TMR0
+        int "IRQ_TMR0"
+        default 12
+config IRQ_TMR1
+        int "IRQ_TMR1"
+        default 12
+config IRQ_TMR2
+        int "IRQ_TMR2"
+        default 12
+config IRQ_TMR3
+        int "IRQ_TMR3"
+        default 12
+config IRQ_TMR4
+        int "IRQ_TMR4"
+        default 12
+config IRQ_TMR5
+        int "IRQ_TMR5"
+        default 12
+config IRQ_TMR6
+        int "IRQ_TMR6"
+        default 12
+config IRQ_TMR7
+        int "IRQ_TMR7"
+        default 12
+config IRQ_PROG_INTA
+        int "IRQ_PROG_INTA"
+        default 12
+config IRQ_PORTG_INTB
+        int "IRQ_PORTG_INTB"
+        default 12
+config IRQ_MEM_DMA0
+        int "IRQ_MEM_DMA0"
+        default 13
+config IRQ_MEM_DMA1
+        int "IRQ_MEM_DMA1"
+        default 13
+config IRQ_WATCH
+        int "IRQ_WATCH"
+        default 13
+
+        help
+          Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
+          This applies to all the above.  It is not recommended to assign the
+          highest priority number 7 to UART or any other device.
+
+endmenu
+
+endmenu
+
+endif