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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:17:10 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:17:10 -0400
commit7e64acabfdb530b1b7d3db2592d75d102827baf3 (patch)
tree9cd5d29f86a700fa474f063462bad928d292b567 /arch/blackfin/mach-bf533
parent1375204611f417541e55ee09e248acdbbb94356d (diff)
Blackfin arch: move async memory programming into common setup_arch() as the banks dont really need to be setup fully as early as head.S
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r--arch/blackfin/mach-bf533/head.S22
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 0ffbe7a205ba..7f0a7a0c6fd6 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -172,28 +172,6 @@ ENTRY(__start)
172 call _start_dma_code; 172 call _start_dma_code;
173#endif 173#endif
174 174
175 /* Code for initializing Async memory banks */
176
177 p2.h = hi(EBIU_AMBCTL1);
178 p2.l = lo(EBIU_AMBCTL1);
179 r0.h = hi(AMBCTL1VAL);
180 r0.l = lo(AMBCTL1VAL);
181 [p2] = r0;
182 ssync;
183
184 p2.h = hi(EBIU_AMBCTL0);
185 p2.l = lo(EBIU_AMBCTL0);
186 r0.h = hi(AMBCTL0VAL);
187 r0.l = lo(AMBCTL0VAL);
188 [p2] = r0;
189 ssync;
190
191 p2.h = hi(EBIU_AMGCTL);
192 p2.l = lo(EBIU_AMGCTL);
193 r0 = AMGCTLVAL;
194 w[p2] = r0;
195 ssync;
196
197 /* This section keeps the processor in supervisor mode 175 /* This section keeps the processor in supervisor mode
198 * during kernel boot. Switches to user mode at end of boot. 176 * during kernel boot. Switches to user mode at end of boot.
199 * See page 3-9 of Hardware Reference manual for documentation. 177 * See page 3-9 of Hardware Reference manual for documentation.