Blackfin: clean up style in irq defines

These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
author: Mike Frysinger <vapier@gentoo.org> 2011-03-30 03:59:00 -0400
committer: Mike Frysinger <vapier@gentoo.org> 2011-05-25 08:13:42 -0400
commit: 3dd666067d2b285724c828946e83100ea4c43d4b (patch)
tree: bb0e0c060013e12a7d6674f8139a5fec59cf6fbc /arch/blackfin/mach-bf533
parent: 6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff)
1 files changed, 55 insertions, 54 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index c4c29fc4ea90..ed19567f96d3 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -9,33 +9,34 @@
 #include <mach-common/irq.h>
-#define SYS_IRQS        31
+#define NR_PERI_INTS            24
-#define NR_PERI_INTS    24
-#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
+#define IRQ_PLL_WAKEUP          7       /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
+#define IRQ_DMA_ERROR           8       /* DMA Error (general) */
-#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
+#define IRQ_PPI_ERROR           9       /* PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
+#define IRQ_SPORT0_ERROR        10      /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
+#define IRQ_SPORT1_ERROR        11      /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
+#define IRQ_SPI_ERROR           12      /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR         13      /*UART Error Interrupt */
+#define IRQ_UART0_ERROR         13      /* UART Error Interrupt */
-#define IRQ_RTC                 14      /*RTC Interrupt */
+#define IRQ_RTC                 14      /* RTC Interrupt */
-#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
+#define IRQ_PPI                 15      /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_RX           16      /* DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT0_TX           17      /* DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_RX           18      /* DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPORT1_TX           19      /* DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define IRQ_SPI                 20      /* DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX            21      /*DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_RX            21      /* DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX            22      /*DMA7 Interrupt (UART TX) */
+#define IRQ_UART0_TX            22      /* DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0              23      /*Timer 0 */
+#define IRQ_TIMER0              23      /* Timer 0 */
-#define IRQ_TIMER1              24      /*Timer 1 */
+#define IRQ_TIMER1              24      /* Timer 1 */
-#define IRQ_TIMER2              25      /*Timer 2 */
+#define IRQ_TIMER2              25      /* Timer 2 */
-#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
+#define IRQ_PROG_INTA           26      /* Programmable Flags A (8) */
-#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
+#define IRQ_PROG_INTB           27      /* Programmable Flags B (8) */
-#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA0            28      /* DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_MEM_DMA1            29      /* DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH               30      /*Watch Dog Timer */
+#define IRQ_WATCH               30      /* Watch Dog Timer */
+#define SYS_IRQS                31
 #define IRQ_PF0                 33
 #define IRQ_PF1                 34
@@ -58,34 +59,34 @@
 #define NR_MACH_IRQS            (IRQ_PF15 + 1)
-/* IAR0 BIT FIELDS*/
+/* IAR0 BIT FIELDS */
-#define RTC_ERROR_POS                   28
+#define RTC_ERROR_POS           28
-#define UART_ERROR_POS                  24
+#define UART_ERROR_POS          24
-#define SPORT1_ERROR_POS                20
+#define SPORT1_ERROR_POS        20
-#define SPI_ERROR_POS                   16
+#define SPI_ERROR_POS           16
-#define SPORT0_ERROR_POS                12
+#define SPORT0_ERROR_POS        12
-#define PPI_ERROR_POS                   8
+#define PPI_ERROR_POS           8
-#define DMA_ERROR_POS                   4
+#define DMA_ERROR_POS           4
-#define PLLWAKE_ERROR_POS               0
+#define PLLWAKE_ERROR_POS       0
-/* IAR1 BIT FIELDS*/
+/* IAR1 BIT FIELDS */
-#define DMA7_UARTTX_POS                 28
+#define DMA7_UARTTX_POS         28
-#define DMA6_UARTRX_POS                 24
+#define DMA6_UARTRX_POS         24
-#define DMA5_SPI_POS                    20
+#define DMA5_SPI_POS            20
-#define DMA4_SPORT1TX_POS               16
+#define DMA4_SPORT1TX_POS       16
-#define DMA3_SPORT1RX_POS               12
+#define DMA3_SPORT1RX_POS       12
-#define DMA2_SPORT0TX_POS               8
+#define DMA2_SPORT0TX_POS       8
-#define DMA1_SPORT0RX_POS               4
+#define DMA1_SPORT0RX_POS       4
-#define DMA0_PPI_POS                    0
+#define DMA0_PPI_POS            0
-/* IAR2 BIT FIELDS*/
+/* IAR2 BIT FIELDS */
-#define WDTIMER_POS                     28
+#define WDTIMER_POS             28
-#define MEMDMA1_POS                     24
+#define MEMDMA1_POS             24
-#define MEMDMA0_POS                     20
+#define MEMDMA0_POS             20
-#define PFB_POS                         16
+#define PFB_POS                 16
-#define PFA_POS                         12
+#define PFA_POS                 12
-#define TIMER2_POS                      8
+#define TIMER2_POS              8
-#define TIMER1_POS                      4
+#define TIMER1_POS              4
-#define TIMER0_POS                      0
+#define TIMER0_POS              0
-#endif                          /* _BF533_IRQ_H_ */
+#endif
author	Mike Frysinger <vapier@gentoo.org>	2011-03-30 03:59:00 -0400
committer	Mike Frysinger <vapier@gentoo.org>	2011-05-25 08:13:42 -0400
commit	3dd666067d2b285724c828946e83100ea4c43d4b (patch)
tree	bb0e0c060013e12a7d6674f8139a5fec59cf6fbc /arch/blackfin/mach-bf533
parent	6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff)

diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h index c4c29fc4ea90..ed19567f96d3 100644 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -9,33 +9,34 @@
9		9
10	#include <mach-common/irq.h>	10	#include <mach-common/irq.h>
11		11
12	#define SYS_IRQS 31	12	#define NR_PERI_INTS 24
13	#define NR_PERI_INTS 24
14		13
15	#define IRQ_PLL_WAKEUP 7 /PLL Wakeup Interrupt /	14	#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
16	#define IRQ_DMA_ERROR 8 /DMA Error (general) /	15	#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
17	#define IRQ_PPI_ERROR 9 /PPI Error Interrupt /	16	#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
18	#define IRQ_SPORT0_ERROR 10 /SPORT0 Error Interrupt /	17	#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
19	#define IRQ_SPORT1_ERROR 11 /SPORT1 Error Interrupt /	18	#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
20	#define IRQ_SPI_ERROR 12 /SPI Error Interrupt /	19	#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
21	#define IRQ_UART0_ERROR 13 /UART Error Interrupt /	20	#define IRQ_UART0_ERROR 13 /* UART Error Interrupt */
22	#define IRQ_RTC 14 /RTC Interrupt /	21	#define IRQ_RTC 14 /* RTC Interrupt */
23	#define IRQ_PPI 15 /DMA0 Interrupt (PPI) /	22	#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
24	#define IRQ_SPORT0_RX 16 /DMA1 Interrupt (SPORT0 RX) /	23	#define IRQ_SPORT0_RX 16 /* DMA1 Interrupt (SPORT0 RX) */
25	#define IRQ_SPORT0_TX 17 /DMA2 Interrupt (SPORT0 TX) /	24	#define IRQ_SPORT0_TX 17 /* DMA2 Interrupt (SPORT0 TX) */
26	#define IRQ_SPORT1_RX 18 /DMA3 Interrupt (SPORT1 RX) /	25	#define IRQ_SPORT1_RX 18 /* DMA3 Interrupt (SPORT1 RX) */
27	#define IRQ_SPORT1_TX 19 /DMA4 Interrupt (SPORT1 TX) /	26	#define IRQ_SPORT1_TX 19 /* DMA4 Interrupt (SPORT1 TX) */
28	#define IRQ_SPI 20 /DMA5 Interrupt (SPI) /	27	#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
29	#define IRQ_UART0_RX 21 /DMA6 Interrupt (UART RX) /	28	#define IRQ_UART0_RX 21 /* DMA6 Interrupt (UART RX) */
30	#define IRQ_UART0_TX 22 /DMA7 Interrupt (UART TX) /	29	#define IRQ_UART0_TX 22 /* DMA7 Interrupt (UART TX) */
31	#define IRQ_TIMER0 23 /Timer 0 /	30	#define IRQ_TIMER0 23 /* Timer 0 */
32	#define IRQ_TIMER1 24 /Timer 1 /	31	#define IRQ_TIMER1 24 /* Timer 1 */
33	#define IRQ_TIMER2 25 /Timer 2 /	32	#define IRQ_TIMER2 25 /* Timer 2 */
34	#define IRQ_PROG_INTA 26 /Programmable Flags A (8) /	33	#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
35	#define IRQ_PROG_INTB 27 /Programmable Flags B (8) /	34	#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
36	#define IRQ_MEM_DMA0 28 /DMA8/9 Interrupt (Memory DMA Stream 0) /	35	#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
37	#define IRQ_MEM_DMA1 29 /DMA10/11 Interrupt (Memory DMA Stream 1) /	36	#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
38	#define IRQ_WATCH 30 /Watch Dog Timer /	37	#define IRQ_WATCH 30 /* Watch Dog Timer */
		38
		39	#define SYS_IRQS 31
39		40
40	#define IRQ_PF0 33	41	#define IRQ_PF0 33
41	#define IRQ_PF1 34	42	#define IRQ_PF1 34
@@ -58,34 +59,34 @@
58		59
59	#define NR_MACH_IRQS (IRQ_PF15 + 1)	60	#define NR_MACH_IRQS (IRQ_PF15 + 1)
60		61
61	/* IAR0 BIT FIELDS*/	62	/* IAR0 BIT FIELDS */
62	#define RTC_ERROR_POS 28	63	#define RTC_ERROR_POS 28
63	#define UART_ERROR_POS 24	64	#define UART_ERROR_POS 24
64	#define SPORT1_ERROR_POS 20	65	#define SPORT1_ERROR_POS 20
65	#define SPI_ERROR_POS 16	66	#define SPI_ERROR_POS 16
66	#define SPORT0_ERROR_POS 12	67	#define SPORT0_ERROR_POS 12
67	#define PPI_ERROR_POS 8	68	#define PPI_ERROR_POS 8
68	#define DMA_ERROR_POS 4	69	#define DMA_ERROR_POS 4
69	#define PLLWAKE_ERROR_POS 0	70	#define PLLWAKE_ERROR_POS 0
70		71
71	/* IAR1 BIT FIELDS*/	72	/* IAR1 BIT FIELDS */
72	#define DMA7_UARTTX_POS 28	73	#define DMA7_UARTTX_POS 28
73	#define DMA6_UARTRX_POS 24	74	#define DMA6_UARTRX_POS 24
74	#define DMA5_SPI_POS 20	75	#define DMA5_SPI_POS 20
75	#define DMA4_SPORT1TX_POS 16	76	#define DMA4_SPORT1TX_POS 16
76	#define DMA3_SPORT1RX_POS 12	77	#define DMA3_SPORT1RX_POS 12
77	#define DMA2_SPORT0TX_POS 8	78	#define DMA2_SPORT0TX_POS 8
78	#define DMA1_SPORT0RX_POS 4	79	#define DMA1_SPORT0RX_POS 4
79	#define DMA0_PPI_POS 0	80	#define DMA0_PPI_POS 0
80		81
81	/* IAR2 BIT FIELDS*/	82	/* IAR2 BIT FIELDS */
82	#define WDTIMER_POS 28	83	#define WDTIMER_POS 28
83	#define MEMDMA1_POS 24	84	#define MEMDMA1_POS 24
84	#define MEMDMA0_POS 20	85	#define MEMDMA0_POS 20
85	#define PFB_POS 16	86	#define PFB_POS 16
86	#define PFA_POS 12	87	#define PFA_POS 12
87	#define TIMER2_POS 8	88	#define TIMER2_POS 8
88	#define TIMER1_POS 4	89	#define TIMER1_POS 4
89	#define TIMER0_POS 0	90	#define TIMER0_POS 0
90		91
91	#endif /* _BF533_IRQ_H_ */	92	#endif