diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-15 00:13:29 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-22 03:48:27 -0400 |
| commit | 3d6437b35d68836b6ec4d45a24dfdafc61a27a84 (patch) | |
| tree | d0c4eb6f11fc9f6c5317c6b3a348711ee2c5ec8f /arch/blackfin/mach-bf533 | |
| parent | d4429f608abde89e8bc1e24b43cd503feb95c496 (diff) | |
Blackfin: punt short SPI MMR bit names
Now that the common header defines everything and the SPI drivers are
using it, we can drop these duplicated global namespace polluters.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 04acf1ed10f9..3adb0b44e597 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h | |||
| @@ -681,76 +681,6 @@ | |||
| 681 | #define PF14_P 14 | 681 | #define PF14_P 14 |
| 682 | #define PF15_P 15 | 682 | #define PF15_P 15 |
| 683 | 683 | ||
| 684 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | ||
| 685 | |||
| 686 | /* SPI_CTL Masks */ | ||
| 687 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | ||
| 688 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
| 689 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
| 690 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
| 691 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
| 692 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ | ||
| 693 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | ||
| 694 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | ||
| 695 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | ||
| 696 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ | ||
| 697 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ | ||
| 698 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | ||
| 699 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | ||
| 700 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | ||
| 701 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | ||
| 702 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | ||
| 703 | |||
| 704 | /* SPI_FLG Masks */ | ||
| 705 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 706 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 707 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 708 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 709 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 710 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 711 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 712 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 713 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 714 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 715 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 716 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 717 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 718 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 719 | |||
| 720 | /* SPI_FLG Bit Positions */ | ||
| 721 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 722 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 723 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 724 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 725 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 726 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 727 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 728 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 729 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 730 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 731 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 732 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 733 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 734 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 735 | |||
| 736 | /* SPI_STAT Masks */ | ||
| 737 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | ||
| 738 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | ||
| 739 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | ||
| 740 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 741 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | ||
| 742 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 743 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | ||
| 744 | |||
| 745 | /* SPIx_FLG Masks */ | ||
| 746 | #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ | ||
| 747 | #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ | ||
| 748 | #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ | ||
| 749 | #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ | ||
| 750 | #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ | ||
| 751 | #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ | ||
| 752 | #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ | ||
| 753 | |||
| 754 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | 684 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
| 755 | 685 | ||
| 756 | /* AMGCTL Masks */ | 686 | /* AMGCTL Masks */ |