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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:23:50 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:23:50 -0400
commit17e89bcfa12f71b840361da07fe6c2f9c48d0605 (patch)
treec5ab94b397bcdfc5ffe0363f24ff83e012e8801a /arch/blackfin/mach-bf533
parent67618fd8748a5d83f6bdcd578c8e748c3f47c4d4 (diff)
Blackfin arch: unify the duplicated portions of __start and split mach-specific pieces into _mach_early_start where they will be easier to trim over time
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r--arch/blackfin/mach-bf533/head.S131
1 files changed, 3 insertions, 128 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7f0a7a0c6fd6..6603967367ec 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -30,74 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
35#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
36#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
37#endif 36#endif
38 37
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
42 39
43#define INITIAL_STACK 0xFFB01000
44
45__INIT 40__INIT
46 41
47ENTRY(__start) 42ENTRY(_mach_early_start)
48 /* R0: argument of command line string, passed from uboot, save it */
49 R7 = R0;
50 /* Enable Cycle Counter and Nesting Of Interrupts */
51#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
52 R0 = SYSCFG_SNEN;
53#else
54 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
55#endif
56 SYSCFG = R0;
57 R0 = 0;
58
59 /* Clear Out All the data and pointer Registers */
60 R1 = R0;
61 R2 = R0;
62 R3 = R0;
63 R4 = R0;
64 R5 = R0;
65 R6 = R0;
66
67 P0 = R0;
68 P1 = R0;
69 P2 = R0;
70 P3 = R0;
71 P4 = R0;
72 P5 = R0;
73
74 LC0 = r0;
75 LC1 = r0;
76 L0 = r0;
77 L1 = r0;
78 L2 = r0;
79 L3 = r0;
80
81 /* Clear Out All the DAG Registers */
82 B0 = r0;
83 B1 = r0;
84 B2 = r0;
85 B3 = r0;
86
87 I0 = r0;
88 I1 = r0;
89 I2 = r0;
90 I3 = r0;
91
92 M0 = r0;
93 M1 = r0;
94 M2 = r0;
95 M3 = r0;
96
97 trace_buffer_init(p0,r0);
98 P0 = R1;
99 R0 = R1;
100
101 p0.h = hi(FIO_MASKA_C); 43 p0.h = hi(FIO_MASKA_C);
102 p0.l = lo(FIO_MASKA_C); 44 p0.l = lo(FIO_MASKA_C);
103 r0 = 0xFFFF(Z); 45 r0 = 0xFFFF(Z);
@@ -110,24 +52,6 @@ ENTRY(__start)
110 w[p0] = r0.L; /* Disable all interrupts */ 52 w[p0] = r0.L; /* Disable all interrupts */
111 ssync; 53 ssync;
112 54
113 /* Turn off the icache */
114 p0.l = LO(IMEM_CONTROL);
115 p0.h = HI(IMEM_CONTROL);
116 R1 = [p0];
117 R0 = ~ENICPLB;
118 R0 = R0 & R1;
119 [p0] = R0;
120 SSYNC;
121
122 /* Turn off the dcache */
123 p0.l = LO(DMEM_CONTROL);
124 p0.h = HI(DMEM_CONTROL);
125 R1 = [p0];
126 R0 = ~ENDCPLB;
127 R0 = R0 & R1;
128 [p0] = R0;
129 SSYNC;
130
131 /* Initialise UART - when booting from u-boot, the UART is not disabled 55 /* Initialise UART - when booting from u-boot, the UART is not disabled
132 * so if we dont initalize here, our serial console gets hosed */ 56 * so if we dont initalize here, our serial console gets hosed */
133 p0.h = hi(BFIN_UART_LCR); 57 p0.h = hi(BFIN_UART_LCR);
@@ -154,57 +78,8 @@ ENTRY(__start)
154 w[p0] = r0.L; /* To enable UART clock */ 78 w[p0] = r0.L; /* To enable UART clock */
155 ssync; 79 ssync;
156 80
157 /* Initialize stack pointer */ 81 rts;
158 sp.l = lo(INITIAL_STACK); 82ENDPROC(_mach_early_start)
159 sp.h = hi(INITIAL_STACK);
160 fp = sp;
161 usp = sp;
162
163#ifdef CONFIG_EARLY_PRINTK
164 SP += -12;
165 call _init_early_exception_vectors;
166 SP += 12;
167#endif
168
169 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
170 call _bf53x_relocate_l1_mem;
171#ifdef CONFIG_BFIN_KERNEL_CLOCK
172 call _start_dma_code;
173#endif
174
175 /* This section keeps the processor in supervisor mode
176 * during kernel boot. Switches to user mode at end of boot.
177 * See page 3-9 of Hardware Reference manual for documentation.
178 */
179
180 /* EVT15 = _real_start */
181
182 p0.l = lo(EVT15);
183 p0.h = hi(EVT15);
184 p1.l = _real_start;
185 p1.h = _real_start;
186 [p0] = p1;
187 csync;
188
189 p0.l = lo(IMASK);
190 p0.h = hi(IMASK);
191 p1.l = IMASK_IVG15;
192 p1.h = 0x0;
193 [p0] = p1;
194 csync;
195
196 raise 15;
197 p0.l = .LWAIT_HERE;
198 p0.h = .LWAIT_HERE;
199 reti = p0;
200#if ANOMALY_05000281
201 nop; nop; nop;
202#endif
203 rti;
204
205.LWAIT_HERE:
206 jump .LWAIT_HERE;
207ENDPROC(__start)
208 83
209__FINIT 84__FINIT
210 85