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authorRobin Getz <robin.getz@analog.com>2007-08-27 05:38:40 -0400
committerBryan Wu <bryan.wu@analog.com>2007-08-27 05:38:40 -0400
commit02f13f9d5c1d3104c5c4e7f4ae30c43d595d1d75 (patch)
tree6ae30584b1158307961224c1755e4e7a34f48a41 /arch/blackfin/mach-bf533
parentd2b11a468a49716debd96532552a72b6078f1cf5 (diff)
Blackfin arch: Remove cruft - CONFIG_DEBUG_SERIAL_EARLY_INIT didn't work that well with DEBUG_KERNEL_START
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r--arch/blackfin/mach-bf533/head.S243
1 files changed, 0 insertions, 243 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 6e1b5f6da5ca..fa6dc0d8593b 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -35,9 +35,6 @@
35#include <asm/mach-common/clocks.h> 35#include <asm/mach-common/clocks.h>
36#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
37#endif 37#endif
38#if CONFIG_DEBUG_KERNEL_START
39#include <asm/mach-common/def_LPBlackfin.h>
40#endif
41 38
42.global __rambase 39.global __rambase
43.global __ramstart 40.global __ramstart
@@ -104,36 +101,6 @@ ENTRY(__start)
104 P0 = R1; 101 P0 = R1;
105 R0 = R1; 102 R0 = R1;
106 103
107#if CONFIG_DEBUG_KERNEL_START
108
109/*
110 * Set up a temporary Event Vector Table, so if something bad happens before
111 * the kernel is fully started, it doesn't vector off into the bootloaders
112 * table
113 */
114 P0.l = lo(EVT2);
115 P0.h = hi(EVT2);
116 P1.l = lo(EVT15);
117 P1.h = hi(EVT15);
118 P2.l = debug_kernel_start_trap;
119 P2.h = debug_kernel_start_trap;
120
121 RTS = P2;
122 RTI = P2;
123 RTX = P2;
124 RTN = P2;
125 RTE = P2;
126
127.Lfill_temp_vector_table:
128 [P0++] = P2; /* Core Event Vector Table */
129 CC = P0 == P1;
130 if !CC JUMP .Lfill_temp_vector_table
131 P0 = r0;
132 P1 = r0;
133 P2 = r0;
134
135#endif
136
137 p0.h = hi(FIO_MASKA_C); 104 p0.h = hi(FIO_MASKA_C);
138 p0.l = lo(FIO_MASKA_C); 105 p0.l = lo(FIO_MASKA_C);
139 r0 = 0xFFFF(Z); 106 r0 = 0xFFFF(Z);
@@ -459,216 +426,6 @@ ENTRY(_start_dma_code)
459ENDPROC(_start_dma_code) 426ENDPROC(_start_dma_code)
460#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 427#endif /* CONFIG_BFIN_KERNEL_CLOCK */
461 428
462#if CONFIG_DEBUG_KERNEL_START
463debug_kernel_start_trap:
464 /* Set up a temp stack in L1 - SDRAM might not be working */
465 P0.L = lo(L1_DATA_A_START + 0x100);
466 P0.H = hi(L1_DATA_A_START + 0x100);
467 SP = P0;
468
469 /* Make sure the Clocks are the way I think they should be */
470 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
471 r0 = r0 << 9; /* Shift it over, */
472 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
473 r0 = r1 | r0;
474 r1 = PLL_BYPASS; /* Bypass the PLL? */
475 r1 = r1 << 8; /* Shift it over */
476 r0 = r1 | r0; /* add them all together */
477
478 p0.h = hi(PLL_CTL);
479 p0.l = lo(PLL_CTL); /* Load the address */
480 cli r2; /* Disable interrupts */
481 ssync;
482 w[p0] = r0.l; /* Set the value */
483 idle; /* Wait for the PLL to stablize */
484 sti r2; /* Enable interrupts */
485
486.Lcheck_again1:
487 p0.h = hi(PLL_STAT);
488 p0.l = lo(PLL_STAT);
489 R0 = W[P0](Z);
490 CC = BITTST(R0,5);
491 if ! CC jump .Lcheck_again1;
492
493 /* Configure SCLK & CCLK Dividers */
494 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
495 p0.h = hi(PLL_DIV);
496 p0.l = lo(PLL_DIV);
497 w[p0] = r0.l;
498 ssync;
499
500 /* Make sure UART is enabled - you can never be sure */
501
502/*
503 * Setup for console. Argument comes from the menuconfig
504 */
505
506#ifdef CONFIG_BAUD_9600
507#define CONSOLE_BAUD_RATE 9600
508#elif CONFIG_BAUD_19200
509#define CONSOLE_BAUD_RATE 19200
510#elif CONFIG_BAUD_38400
511#define CONSOLE_BAUD_RATE 38400
512#elif CONFIG_BAUD_57600
513#define CONSOLE_BAUD_RATE 57600
514#elif CONFIG_BAUD_115200
515#define CONSOLE_BAUD_RATE 115200
516#endif
517
518 p0.h = hi(UART_GCTL);
519 p0.l = lo(UART_GCTL);
520 r0 = 0x00(Z);
521 w[p0] = r0.L; /* To Turn off UART clocks */
522 ssync;
523
524 p0.h = hi(UART_LCR);
525 p0.l = lo(UART_LCR);
526 r0 = 0x83(Z);
527 w[p0] = r0.L; /* To enable DLL writes */
528 ssync;
529
530 R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
531
532 p0.h = hi(UART_DLL);
533 p0.l = lo(UART_DLL);
534 r0 = 0xFF(Z);
535 r0 = R1 & R0;
536 w[p0] = r0.L;
537 ssync;
538
539 p0.h = hi(UART_DLH);
540 p0.l = lo(UART_DLH);
541 r1 >>= 8 ;
542 w[p0] = r1.L;
543 ssync;
544
545 p0.h = hi(UART_GCTL);
546 p0.l = lo(UART_GCTL);
547 r0 = 0x0(Z);
548 w[p0] = r0.L; /* To enable UART clock */
549 ssync;
550
551 p0.h = hi(UART_LCR);
552 p0.l = lo(UART_LCR);
553 r0 = 0x03(Z);
554 w[p0] = r0.L; /* To Turn on UART */
555 ssync;
556
557 p0.h = hi(UART_GCTL);
558 p0.l = lo(UART_GCTL);
559 r0 = 0x01(Z);
560 w[p0] = r0.L; /* To Turn on UART Clocks */
561 ssync;
562
563 P0.h = hi(UART_THR);
564 P0.l = lo(UART_THR);
565 P1.h = hi(UART_LSR);
566 P1.l = lo(UART_LSR);
567
568 R0.L = 'K';
569 call .Lwait_char;
570 R0.L='e';
571 call .Lwait_char;
572 R0.L='r';
573 call .Lwait_char;
574 R0.L='n'
575 call .Lwait_char;
576 R0.L='e'
577 call .Lwait_char;
578 R0.L='l';
579 call .Lwait_char;
580 R0.L=' ';
581 call .Lwait_char;
582 R0.L='c';
583 call .Lwait_char;
584 R0.L='r';
585 call .Lwait_char;
586 R0.L='a';
587 call .Lwait_char;
588 R0.L='s';
589 call .Lwait_char;
590 R0.L='h';
591 call .Lwait_char;
592 R0.L='\r';
593 call .Lwait_char;
594 R0.L='\n';
595 call .Lwait_char;
596
597 R0.L='S';
598 call .Lwait_char;
599 R0.L='E';
600 call .Lwait_char;
601 R0.L='Q'
602 call .Lwait_char;
603 R0.L='S'
604 call .Lwait_char;
605 R0.L='T';
606 call .Lwait_char;
607 R0.L='A';
608 call .Lwait_char;
609 R0.L='T';
610 call .Lwait_char;
611 R0.L='=';
612 call .Lwait_char;
613 R2 = SEQSTAT;
614 call .Ldump_reg;
615
616 R0.L=' ';
617 call .Lwait_char;
618 R0.L='R';
619 call .Lwait_char;
620 R0.L='E'
621 call .Lwait_char;
622 R0.L='T'
623 call .Lwait_char;
624 R0.L='X';
625 call .Lwait_char;
626 R0.L='=';
627 call .Lwait_char;
628 R2 = RETX;
629 call .Ldump_reg;
630
631 R0.L='\r';
632 call .Lwait_char;
633 R0.L='\n';
634 call .Lwait_char;
635
636.Ldebug_kernel_start_trap_done:
637 JUMP .Ldebug_kernel_start_trap_done;
638.Ldump_reg:
639 R3 = 32;
640 R4 = 0x0F;
641 R5 = ':'; /* one past 9 */
642
643.Ldump_reg2:
644 R0 = R2;
645 R3 += -4;
646 R0 >>>= R3;
647 R0 = R0 & R4;
648 R0 += 0x30;
649 CC = R0 <= R5;
650 if CC JUMP .Ldump_reg1;
651 R0 += 7;
652
653.Ldump_reg1:
654 R1.l = W[P1];
655 CC = BITTST(R1, 5);
656 if !CC JUMP .Ldump_reg1;
657 W[P0] = r0;
658
659 CC = R3 == 0;
660 if !CC JUMP .Ldump_reg2
661 RTS;
662
663.Lwait_char:
664 R1.l = W[P1];
665 CC = BITTST(R1, 5);
666 if !CC JUMP .Lwait_char;
667 W[P0] = r0;
668 RTS;
669
670#endif /* CONFIG_DEBUG_KERNEL_START */
671
672.data 429.data
673 430
674/* 431/*