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authorMike Frysinger <vapier@gentoo.org>2011-03-30 02:54:33 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:42 -0400
commit6adc521e7127732512ebd7fcfd3926d7970a82e1 (patch)
tree1de12c99fde995c82a8cd7487f45c6f6ea0b4ef4 /arch/blackfin/mach-bf533
parent6b108049d67090988fbb0b9d9905ffca114b6ff1 (diff)
Blackfin: unify core IRQ definitions
Start a new common IRQ header and move all of the CEC pieces there. This lets the individual part headers worry just about its SIC defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h61
1 files changed, 1 insertions, 60 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 1f7e9765d954..c4c29fc4ea90 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -7,59 +7,11 @@
7#ifndef _BF533_IRQ_H_ 7#ifndef _BF533_IRQ_H_
8#define _BF533_IRQ_H_ 8#define _BF533_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21 PLL Wakeup Interrupt IVG7 7
22 DMA Error (generic) IVG7 8
23 PPI Error Interrupt IVG7 9
24 SPORT0 Error Interrupt IVG7 10
25 SPORT1 Error Interrupt IVG7 11
26 SPI Error Interrupt IVG7 12
27 UART Error Interrupt IVG7 13
28 RTC Interrupt IVG8 14
29 DMA0 Interrupt (PPI) IVG8 15
30 DMA1 (SPORT0 RX) IVG9 16
31 DMA2 (SPORT0 TX) IVG9 17
32 DMA3 (SPORT1 RX) IVG9 18
33 DMA4 (SPORT1 TX) IVG9 19
34 DMA5 (PPI) IVG10 20
35 DMA6 (UART RX) IVG10 21
36 DMA7 (UART TX) IVG10 22
37 Timer0 IVG11 23
38 Timer1 IVG11 24
39 Timer2 IVG11 25
40 PF Interrupt A IVG12 26
41 PF Interrupt B IVG12 27
42 DMA8/9 Interrupt IVG13 28
43 DMA10/11 Interrupt IVG13 29
44 Watchdog Timer IVG13 30
45 11
46 Softirq IVG14 31
47 System Call --
48 (lowest priority) IVG15 32 *
49 */
50#define SYS_IRQS 31 12#define SYS_IRQS 31
51#define NR_PERI_INTS 24 13#define NR_PERI_INTS 24
52 14
53/* The ABSTRACT IRQ definitions */
54/** the first seven of the following are fixed, the rest you change if you need to **/
55#define IRQ_EMU 0 /*Emulation */
56#define IRQ_RST 1 /*reset */
57#define IRQ_NMI 2 /*Non Maskable */
58#define IRQ_EVX 3 /*Exception */
59#define IRQ_UNUSED 4 /*- unused interrupt*/
60#define IRQ_HWERR 5 /*Hardware Error */
61#define IRQ_CORETMR 6 /*Core timer */
62
63#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
64#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
65#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */ 17#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
@@ -105,17 +57,6 @@ Core Emulation **
105#define GPIO_IRQ_BASE IRQ_PF0 57#define GPIO_IRQ_BASE IRQ_PF0
106 58
107#define NR_MACH_IRQS (IRQ_PF15 + 1) 59#define NR_MACH_IRQS (IRQ_PF15 + 1)
108#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
109
110#define IVG7 7
111#define IVG8 8
112#define IVG9 9
113#define IVG10 10
114#define IVG11 11
115#define IVG12 12
116#define IVG13 13
117#define IVG14 14
118#define IVG15 15
119 60
120/* IAR0 BIT FIELDS*/ 61/* IAR0 BIT FIELDS*/
121#define RTC_ERROR_POS 28 62#define RTC_ERROR_POS 28