diff options
author | Yi Li <yi.li@analog.com> | 2009-01-07 10:14:39 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 10:14:39 -0500 |
commit | 6a01f230339321292cf065551f8cf55361052461 (patch) | |
tree | 7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf533 | |
parent | 5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff) |
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf533')
-rw-r--r-- | arch/blackfin/mach-bf533/Kconfig | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 16 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/irq.h | 6 |
3 files changed, 12 insertions, 12 deletions
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig index 76beb75f12da..14427de7d77f 100644 --- a/arch/blackfin/mach-bf533/Kconfig +++ b/arch/blackfin/mach-bf533/Kconfig | |||
@@ -59,7 +59,7 @@ config DMA7_UARTTX | |||
59 | default 10 | 59 | default 10 |
60 | config TIMER0 | 60 | config TIMER0 |
61 | int "TIMER0" | 61 | int "TIMER0" |
62 | default 11 | 62 | default 8 |
63 | config TIMER1 | 63 | config TIMER1 |
64 | int "TIMER1" | 64 | int "TIMER1" |
65 | default 11 | 65 | default 11 |
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index d7b08f638ea4..bbc3c8386d48 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h | |||
@@ -684,10 +684,10 @@ | |||
684 | static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ | 684 | static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ |
685 | { \ | 685 | { \ |
686 | unsigned long flags; \ | 686 | unsigned long flags; \ |
687 | local_irq_save(flags); \ | 687 | local_irq_save_hw(flags); \ |
688 | bfin_write16(FIO_FLAG_##name, val); \ | 688 | bfin_write16(FIO_FLAG_##name, val); \ |
689 | bfin_read_CHIPID(); \ | 689 | bfin_read_CHIPID(); \ |
690 | local_irq_restore(flags); \ | 690 | local_irq_restore_hw(flags); \ |
691 | } | 691 | } |
692 | BFIN_WRITE_FIO_FLAG(D) | 692 | BFIN_WRITE_FIO_FLAG(D) |
693 | BFIN_WRITE_FIO_FLAG(C) | 693 | BFIN_WRITE_FIO_FLAG(C) |
@@ -699,10 +699,10 @@ static inline u16 bfin_read_FIO_FLAG_##name(void) \ | |||
699 | { \ | 699 | { \ |
700 | unsigned long flags; \ | 700 | unsigned long flags; \ |
701 | u16 ret; \ | 701 | u16 ret; \ |
702 | local_irq_save(flags); \ | 702 | local_irq_save_hw(flags); \ |
703 | ret = bfin_read16(FIO_FLAG_##name); \ | 703 | ret = bfin_read16(FIO_FLAG_##name); \ |
704 | bfin_read_CHIPID(); \ | 704 | bfin_read_CHIPID(); \ |
705 | local_irq_restore(flags); \ | 705 | local_irq_restore_hw(flags); \ |
706 | return ret; \ | 706 | return ret; \ |
707 | } | 707 | } |
708 | BFIN_READ_FIO_FLAG(D) | 708 | BFIN_READ_FIO_FLAG(D) |
@@ -729,7 +729,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) | |||
729 | if (val == bfin_read_PLL_CTL()) | 729 | if (val == bfin_read_PLL_CTL()) |
730 | return; | 730 | return; |
731 | 731 | ||
732 | local_irq_save(flags); | 732 | local_irq_save_hw(flags); |
733 | /* Enable the PLL Wakeup bit in SIC IWR */ | 733 | /* Enable the PLL Wakeup bit in SIC IWR */ |
734 | iwr = bfin_read32(SIC_IWR); | 734 | iwr = bfin_read32(SIC_IWR); |
735 | /* Only allow PPL Wakeup) */ | 735 | /* Only allow PPL Wakeup) */ |
@@ -740,7 +740,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) | |||
740 | asm("IDLE;"); | 740 | asm("IDLE;"); |
741 | 741 | ||
742 | bfin_write32(SIC_IWR, iwr); | 742 | bfin_write32(SIC_IWR, iwr); |
743 | local_irq_restore(flags); | 743 | local_irq_restore_hw(flags); |
744 | } | 744 | } |
745 | 745 | ||
746 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | 746 | /* Writing to VR_CTL initiates a PLL relock sequence. */ |
@@ -751,7 +751,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
751 | if (val == bfin_read_VR_CTL()) | 751 | if (val == bfin_read_VR_CTL()) |
752 | return; | 752 | return; |
753 | 753 | ||
754 | local_irq_save(flags); | 754 | local_irq_save_hw(flags); |
755 | /* Enable the PLL Wakeup bit in SIC IWR */ | 755 | /* Enable the PLL Wakeup bit in SIC IWR */ |
756 | iwr = bfin_read32(SIC_IWR); | 756 | iwr = bfin_read32(SIC_IWR); |
757 | /* Only allow PPL Wakeup) */ | 757 | /* Only allow PPL Wakeup) */ |
@@ -762,7 +762,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
762 | asm("IDLE;"); | 762 | asm("IDLE;"); |
763 | 763 | ||
764 | bfin_write32(SIC_IWR, iwr); | 764 | bfin_write32(SIC_IWR, iwr); |
765 | local_irq_restore(flags); | 765 | local_irq_restore_hw(flags); |
766 | } | 766 | } |
767 | 767 | ||
768 | #endif /* _CDEF_BF532_H */ | 768 | #endif /* _CDEF_BF532_H */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h index e7dd315159df..db1e346cd1aa 100644 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ b/arch/blackfin/mach-bf533/include/mach/irq.h | |||
@@ -100,9 +100,9 @@ Core Emulation ** | |||
100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ | 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ |
101 | #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ | 101 | #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ |
102 | #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ | 102 | #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ |
103 | #define IRQ_TMR0 23 /*Timer 0 */ | 103 | #define IRQ_TIMER0 23 /*Timer 0 */ |
104 | #define IRQ_TMR1 24 /*Timer 1 */ | 104 | #define IRQ_TIMER1 24 /*Timer 1 */ |
105 | #define IRQ_TMR2 25 /*Timer 2 */ | 105 | #define IRQ_TIMER2 25 /*Timer 2 */ |
106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ | 106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ |
107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ | 107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ |
108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ | 108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ |