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authorMike Frysinger <vapier.adi@gmail.com>2008-10-10 09:07:55 -0400
committerBryan Wu <cooloney@kernel.org>2008-10-10 09:07:55 -0400
commit4e8086d65bd0a606434a4b16611653387f8c9698 (patch)
treef22974c7c32e5c314e71831b53bbf6f2ce6b4e0a /arch/blackfin/mach-bf533/include
parent9a6f5ae1f1f3c37aad938a1c82db248a3f95a629 (diff)
Blackfin arch: update anomaly headers to match the latest sheet
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf533/include')
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h49
1 files changed, 27 insertions, 22 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 8f7ea112fd3a..f544fc56959a 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 10 * - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -97,11 +97,11 @@
97/* UART STB Bit Incorrectly Affects Receiver Setting */ 97/* UART STB Bit Incorrectly Affects Receiver Setting */
98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
100#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) 100#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
101/* Incorrect Revision Number in DSPID Register */ 101/* Incorrect Revision Number in DSPID Register */
102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) 102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
104#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) 104#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -131,7 +131,7 @@
131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
134#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) 134#define ANOMALY_05000265 (1)
135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) 136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
@@ -141,56 +141,59 @@
141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
142#define ANOMALY_05000272 (1) 142#define ANOMALY_05000272 (1)
143/* Writes to Synchronous SDRAM Memory May Be Lost */ 143/* Writes to Synchronous SDRAM Memory May Be Lost */
144#define ANOMALY_05000273 (1) 144#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
146#define ANOMALY_05000276 (1) 146#define ANOMALY_05000276 (1)
147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
148#define ANOMALY_05000277 (1) 148#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
150#define ANOMALY_05000278 (1) 150#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
151/* False Hardware Error Exception When ISR Context Is Not Restored */ 151/* False Hardware Error Exception When ISR Context Is Not Restored */
152#define ANOMALY_05000281 (1) 152#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
154#define ANOMALY_05000282 (1) 154#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
156#define ANOMALY_05000283 (1) 156#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
157/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 157/* SPORTs May Receive Bad Data If FIFOs Fill Up */
158#define ANOMALY_05000288 (1) 158#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
160#define ANOMALY_05000301 (1) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
167/* SCKELOW Bit Does Not Maintain State Through Hibernate */
168#define ANOMALY_05000307 (1)
167/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 169/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
168#define ANOMALY_05000310 (1) 170#define ANOMALY_05000310 (1)
169/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ 171/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
170#define ANOMALY_05000311 (1) 172#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
171/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 173/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
172#define ANOMALY_05000312 (1) 174#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
173/* PPI Is Level-Sensitive on First Transfer */ 175/* PPI Is Level-Sensitive on First Transfer */
174#define ANOMALY_05000313 (1) 176#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
175/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 177/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
176#define ANOMALY_05000315 (1) 178#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 179/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) 180#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
179/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 181/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
180#define ANOMALY_05000357 (1) 182#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
181/* UART Break Signal Issues */ 183/* UART Break Signal Issues */
182#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) 184#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
183/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 185/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
184#define ANOMALY_05000366 (1) 186#define ANOMALY_05000366 (1)
185/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 187/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
186#define ANOMALY_05000371 (1) 188#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
187/* PPI Does Not Start Properly In Specific Mode */ 189/* PPI Does Not Start Properly In Specific Mode */
188#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) 190#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
189/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 191/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
190#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) 192#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
191/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 193/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
192#define ANOMALY_05000403 (1) 194#define ANOMALY_05000403 (1)
193 195/* Speculative Fetches Can Cause Undesired External FIFO Operations */
196#define ANOMALY_05000416 (1)
194 197
195/* These anomalies have been "phased" out of analog.com anomaly sheets and are 198/* These anomalies have been "phased" out of analog.com anomaly sheets and are
196 * here to show running on older silicon just isn't feasible. 199 * here to show running on older silicon just isn't feasible.
@@ -268,5 +271,7 @@
268/* Anomalies that don't exist on this proc */ 271/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000266 (0) 272#define ANOMALY_05000266 (0)
270#define ANOMALY_05000323 (0) 273#define ANOMALY_05000323 (0)
274#define ANOMALY_05000353 (1)
275#define ANOMALY_05000386 (1)
271 276
272#endif 277#endif