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authorMike Frysinger <vapier.adi@gmail.com>2008-08-14 03:15:43 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-14 03:15:43 -0400
commit7e1e7aed0ca082b4e76567ee7ea13993b476e66a (patch)
tree8d294d0b5f838e52f708b6bba622acdf2231c755 /arch/blackfin/mach-bf527
parent95a86b5e51139a199d081b6b108e761966d914ef (diff)
Blackfin arch: do not muck with the UART during boot -- let the serial driver worry about it
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/head.S36
1 files changed, 0 insertions, 36 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index fa4b18eddf63..c3334cc5bcb7 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -35,42 +35,6 @@
35#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
36#endif 36#endif
37 37
38.extern _bf53x_relocate_l1_mem
39
40__INIT
41
42ENTRY(_mach_early_start)
43 /* Initialise UART - when booting from u-boot, the UART is not disabled
44 * so if we dont initalize here, our serial console gets hosed */
45 p0.h = hi(UART1_LCR);
46 p0.l = lo(UART1_LCR);
47 r0 = 0x0(Z);
48 w[p0] = r0.L; /* To enable DLL writes */
49 ssync;
50
51 p0.h = hi(UART1_DLL);
52 p0.l = lo(UART1_DLL);
53 r0 = 0x0(Z);
54 w[p0] = r0.L;
55 ssync;
56
57 p0.h = hi(UART1_DLH);
58 p0.l = lo(UART1_DLH);
59 r0 = 0x00(Z);
60 w[p0] = r0.L;
61 ssync;
62
63 p0.h = hi(UART1_GCTL);
64 p0.l = lo(UART1_GCTL);
65 r0 = 0x0(Z);
66 w[p0] = r0.L; /* To enable UART clock */
67 ssync;
68
69 rts;
70ENDPROC(_mach_early_start)
71
72__FINIT
73
74.section .l1.text 38.section .l1.text
75#ifdef CONFIG_BFIN_KERNEL_CLOCK 39#ifdef CONFIG_BFIN_KERNEL_CLOCK
76ENTRY(_start_dma_code) 40ENTRY(_start_dma_code)