diff options
author | Bryan Wu <cooloney@kernel.org> | 2008-08-26 22:51:02 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-08-26 22:51:02 -0400 |
commit | 639f6571458948b5112be2cf00c0c2c04db2897d (patch) | |
tree | a4dd7af33d0e92c935ba1e904f6fb7e923ac825e /arch/blackfin/mach-bf527 | |
parent | 3d9b7a5ce534f3963afcf8f4777267e5899fe007 (diff) |
Blackfin arch: move include/asm-blackfin header files to arch/blackfin
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
19 files changed, 7799 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index c3334cc5bcb7..28c486191209 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S | |||
@@ -31,8 +31,8 @@ | |||
31 | #include <linux/init.h> | 31 | #include <linux/init.h> |
32 | #include <asm/blackfin.h> | 32 | #include <asm/blackfin.h> |
33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
34 | #include <asm/mach-common/clocks.h> | 34 | #include <asm/clocks.h> |
35 | #include <asm/mach/mem_init.h> | 35 | #include <mach/mem_init.h> |
36 | #endif | 36 | #endif |
37 | 37 | ||
38 | .section .l1.text | 38 | .section .l1.text |
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h new file mode 100644 index 000000000000..b7b166f4f064 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/anomaly.h | ||
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
4 | * | ||
5 | * Copyright (C) 2004-2008 Analog Devices Inc. | ||
6 | * Licensed under the GPL-2 or later. | ||
7 | */ | ||
8 | |||
9 | /* This file shoule be up to date with: | ||
10 | * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List | ||
11 | */ | ||
12 | |||
13 | #ifndef _MACH_ANOMALY_H_ | ||
14 | #define _MACH_ANOMALY_H_ | ||
15 | |||
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | ||
17 | #define ANOMALY_05000074 (1) | ||
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | ||
19 | #define ANOMALY_05000119 (1) | ||
20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | ||
21 | #define ANOMALY_05000122 (1) | ||
22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | ||
23 | #define ANOMALY_05000245 (1) | ||
24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | ||
25 | #define ANOMALY_05000265 (1) | ||
26 | /* New Feature: EMAC TX DMA Word Alignment */ | ||
27 | #define ANOMALY_05000285 (1) | ||
28 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
29 | #define ANOMALY_05000312 (1) | ||
30 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | ||
31 | #define ANOMALY_05000328 (1) | ||
32 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | ||
33 | #define ANOMALY_05000337 (1) | ||
34 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | ||
35 | #define ANOMALY_05000341 (1) | ||
36 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ | ||
37 | #define ANOMALY_05000342 (1) | ||
38 | /* USB Calibration Value Is Not Initialized */ | ||
39 | #define ANOMALY_05000346 (1) | ||
40 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ | ||
41 | #define ANOMALY_05000347 (1) | ||
42 | /* Security Features Are Not Functional */ | ||
43 | #define ANOMALY_05000348 (__SILICON_REVISION__ < 1) | ||
44 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | ||
45 | #define ANOMALY_05000355 (1) | ||
46 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | ||
47 | #define ANOMALY_05000357 (1) | ||
48 | /* Incorrect Revision Number in DSPID Register */ | ||
49 | #define ANOMALY_05000364 (__SILICON_REVISION__ > 0) | ||
50 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
51 | #define ANOMALY_05000366 (1) | ||
52 | /* New Feature: Higher Default CCLK Rate */ | ||
53 | #define ANOMALY_05000368 (1) | ||
54 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | ||
55 | #define ANOMALY_05000371 (1) | ||
56 | /* Authentication Fails To Initiate */ | ||
57 | #define ANOMALY_05000376 (__SILICON_REVISION__ > 0) | ||
58 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ | ||
59 | #define ANOMALY_05000380 (1) | ||
60 | /* USB Full-speed Mode not Fully Tested */ | ||
61 | #define ANOMALY_05000381 (1) | ||
62 | /* New Feature: Boot from OTP Memory */ | ||
63 | #define ANOMALY_05000385 (1) | ||
64 | /* New Feature: bfrom_SysControl() Routine */ | ||
65 | #define ANOMALY_05000386 (1) | ||
66 | /* New Feature: Programmable Preboot Settings */ | ||
67 | #define ANOMALY_05000387 (1) | ||
68 | /* Reset Vector Must Not Be in SDRAM Memory Space */ | ||
69 | #define ANOMALY_05000389 (1) | ||
70 | /* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ | ||
71 | #define ANOMALY_05000392 (1) | ||
72 | /* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ | ||
73 | #define ANOMALY_05000393 (1) | ||
74 | /* New Feature: Log Buffer Functionality */ | ||
75 | #define ANOMALY_05000394 (1) | ||
76 | /* New Feature: Hook Routine Functionality */ | ||
77 | #define ANOMALY_05000395 (1) | ||
78 | /* New Feature: Header Indirect Bit */ | ||
79 | #define ANOMALY_05000396 (1) | ||
80 | /* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ | ||
81 | #define ANOMALY_05000397 (1) | ||
82 | /* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ | ||
83 | #define ANOMALY_05000398 (1) | ||
84 | /* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ | ||
85 | #define ANOMALY_05000399 (1) | ||
86 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ | ||
87 | #define ANOMALY_05000401 (1) | ||
88 | |||
89 | /* Anomalies that don't exist on this proc */ | ||
90 | #define ANOMALY_05000125 (0) | ||
91 | #define ANOMALY_05000158 (0) | ||
92 | #define ANOMALY_05000183 (0) | ||
93 | #define ANOMALY_05000198 (0) | ||
94 | #define ANOMALY_05000230 (0) | ||
95 | #define ANOMALY_05000244 (0) | ||
96 | #define ANOMALY_05000261 (0) | ||
97 | #define ANOMALY_05000263 (0) | ||
98 | #define ANOMALY_05000266 (0) | ||
99 | #define ANOMALY_05000273 (0) | ||
100 | #define ANOMALY_05000311 (0) | ||
101 | #define ANOMALY_05000323 (0) | ||
102 | #define ANOMALY_05000363 (0) | ||
103 | |||
104 | #endif | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h new file mode 100644 index 000000000000..056eb4b9cd25 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/bf527.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/bf527.h | ||
3 | * Based on: include/asm-blackfin/mach-bf537/bf537.h | ||
4 | * Author: Michael Hennerich (michael.hennerich@analog.com) | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527 | ||
8 | * | ||
9 | * Modified: | ||
10 | * Copyright 2004-2007 Analog Devices Inc. | ||
11 | * | ||
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, see the file COPYING, or write | ||
26 | * to the Free Software Foundation, Inc., | ||
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
28 | */ | ||
29 | |||
30 | #ifndef __MACH_BF527_H__ | ||
31 | #define __MACH_BF527_H__ | ||
32 | |||
33 | #define SUPPORTED_REVID 2 | ||
34 | |||
35 | #define OFFSET_(x) ((x) & 0x0000FFFF) | ||
36 | |||
37 | /*some misc defines*/ | ||
38 | #define IMASK_IVG15 0x8000 | ||
39 | #define IMASK_IVG14 0x4000 | ||
40 | #define IMASK_IVG13 0x2000 | ||
41 | #define IMASK_IVG12 0x1000 | ||
42 | |||
43 | #define IMASK_IVG11 0x0800 | ||
44 | #define IMASK_IVG10 0x0400 | ||
45 | #define IMASK_IVG9 0x0200 | ||
46 | #define IMASK_IVG8 0x0100 | ||
47 | |||
48 | #define IMASK_IVG7 0x0080 | ||
49 | #define IMASK_IVGTMR 0x0040 | ||
50 | #define IMASK_IVGHW 0x0020 | ||
51 | |||
52 | /***************************/ | ||
53 | |||
54 | #define BFIN_DSUBBANKS 4 | ||
55 | #define BFIN_DWAYS 2 | ||
56 | #define BFIN_DLINES 64 | ||
57 | #define BFIN_ISUBBANKS 4 | ||
58 | #define BFIN_IWAYS 4 | ||
59 | #define BFIN_ILINES 32 | ||
60 | |||
61 | #define WAY0_L 0x1 | ||
62 | #define WAY1_L 0x2 | ||
63 | #define WAY01_L 0x3 | ||
64 | #define WAY2_L 0x4 | ||
65 | #define WAY02_L 0x5 | ||
66 | #define WAY12_L 0x6 | ||
67 | #define WAY012_L 0x7 | ||
68 | |||
69 | #define WAY3_L 0x8 | ||
70 | #define WAY03_L 0x9 | ||
71 | #define WAY13_L 0xA | ||
72 | #define WAY013_L 0xB | ||
73 | |||
74 | #define WAY32_L 0xC | ||
75 | #define WAY320_L 0xD | ||
76 | #define WAY321_L 0xE | ||
77 | #define WAYALL_L 0xF | ||
78 | |||
79 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ | ||
80 | |||
81 | /********************************* EBIU Settings ************************************/ | ||
82 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) | ||
83 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) | ||
84 | |||
85 | #ifdef CONFIG_C_AMBEN_ALL | ||
86 | #define V_AMBEN AMBEN_ALL | ||
87 | #endif | ||
88 | #ifdef CONFIG_C_AMBEN | ||
89 | #define V_AMBEN 0x0 | ||
90 | #endif | ||
91 | #ifdef CONFIG_C_AMBEN_B0 | ||
92 | #define V_AMBEN AMBEN_B0 | ||
93 | #endif | ||
94 | #ifdef CONFIG_C_AMBEN_B0_B1 | ||
95 | #define V_AMBEN AMBEN_B0_B1 | ||
96 | #endif | ||
97 | #ifdef CONFIG_C_AMBEN_B0_B1_B2 | ||
98 | #define V_AMBEN AMBEN_B0_B1_B2 | ||
99 | #endif | ||
100 | #ifdef CONFIG_C_AMCKEN | ||
101 | #define V_AMCKEN AMCKEN | ||
102 | #else | ||
103 | #define V_AMCKEN 0x0 | ||
104 | #endif | ||
105 | #ifdef CONFIG_C_CDPRIO | ||
106 | #define V_CDPRIO 0x100 | ||
107 | #else | ||
108 | #define V_CDPRIO 0x0 | ||
109 | #endif | ||
110 | |||
111 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) | ||
112 | |||
113 | #ifdef CONFIG_BF527 | ||
114 | #define CPU "BF527" | ||
115 | #endif | ||
116 | #ifdef CONFIG_BF525 | ||
117 | #define CPU "BF525" | ||
118 | #endif | ||
119 | #ifdef CONFIG_BF522 | ||
120 | #define CPU "BF522" | ||
121 | #endif | ||
122 | #ifndef CPU | ||
123 | #define CPU "UNKNOWN" | ||
124 | #define CPUID 0x0 | ||
125 | #endif | ||
126 | |||
127 | #endif /* __MACH_BF527_H__ */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h new file mode 100644 index 000000000000..2526b6ed6faa --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h | |||
@@ -0,0 +1,195 @@ | |||
1 | /* | ||
2 | * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h | ||
3 | * based on: | ||
4 | * author: | ||
5 | * | ||
6 | * created: | ||
7 | * description: | ||
8 | * blackfin serial driver head file | ||
9 | * rev: | ||
10 | * | ||
11 | * modified: | ||
12 | * | ||
13 | * | ||
14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * this program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the gnu general public license as published by | ||
18 | * the free software foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * this program is distributed in the hope that it will be useful, | ||
22 | * but without any warranty; without even the implied warranty of | ||
23 | * merchantability or fitness for a particular purpose. see the | ||
24 | * gnu general public license for more details. | ||
25 | * | ||
26 | * you should have received a copy of the gnu general public license | ||
27 | * along with this program; see the file copying. | ||
28 | * if not, write to the free software foundation, | ||
29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
30 | */ | ||
31 | |||
32 | #include <linux/serial.h> | ||
33 | #include <asm/dma.h> | ||
34 | #include <asm/portmux.h> | ||
35 | |||
36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) | ||
37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) | ||
38 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) | ||
39 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | ||
40 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | ||
41 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | ||
42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | ||
43 | |||
44 | #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) | ||
45 | #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) | ||
46 | #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) | ||
47 | #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) | ||
48 | #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) | ||
49 | #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) | ||
50 | #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) | ||
51 | #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) | ||
52 | |||
53 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) | ||
54 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) | ||
55 | |||
56 | #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) | ||
57 | #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) | ||
58 | #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) | ||
59 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | ||
60 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | ||
61 | |||
62 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | ||
63 | # define CONFIG_SERIAL_BFIN_CTSRTS | ||
64 | |||
65 | # ifndef CONFIG_UART0_CTS_PIN | ||
66 | # define CONFIG_UART0_CTS_PIN -1 | ||
67 | # endif | ||
68 | |||
69 | # ifndef CONFIG_UART0_RTS_PIN | ||
70 | # define CONFIG_UART0_RTS_PIN -1 | ||
71 | # endif | ||
72 | |||
73 | # ifndef CONFIG_UART1_CTS_PIN | ||
74 | # define CONFIG_UART1_CTS_PIN -1 | ||
75 | # endif | ||
76 | |||
77 | # ifndef CONFIG_UART1_RTS_PIN | ||
78 | # define CONFIG_UART1_RTS_PIN -1 | ||
79 | # endif | ||
80 | #endif | ||
81 | /* | ||
82 | * The pin configuration is different from schematic | ||
83 | */ | ||
84 | struct bfin_serial_port { | ||
85 | struct uart_port port; | ||
86 | unsigned int old_status; | ||
87 | unsigned int lsr; | ||
88 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
89 | int tx_done; | ||
90 | int tx_count; | ||
91 | struct circ_buf rx_dma_buf; | ||
92 | struct timer_list rx_dma_timer; | ||
93 | int rx_dma_nrows; | ||
94 | unsigned int tx_dma_channel; | ||
95 | unsigned int rx_dma_channel; | ||
96 | struct work_struct tx_dma_workqueue; | ||
97 | #endif | ||
98 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
99 | struct timer_list cts_timer; | ||
100 | int cts_pin; | ||
101 | int rts_pin; | ||
102 | #endif | ||
103 | }; | ||
104 | |||
105 | /* The hardware clears the LSR bits upon read, so we need to cache | ||
106 | * some of the more fun bits in software so they don't get lost | ||
107 | * when checking the LSR in other code paths (TX). | ||
108 | */ | ||
109 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) | ||
110 | { | ||
111 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); | ||
112 | uart->lsr |= (lsr & (BI|FE|PE|OE)); | ||
113 | return lsr | uart->lsr; | ||
114 | } | ||
115 | |||
116 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) | ||
117 | { | ||
118 | uart->lsr = 0; | ||
119 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); | ||
120 | } | ||
121 | |||
122 | struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; | ||
123 | struct bfin_serial_res { | ||
124 | unsigned long uart_base_addr; | ||
125 | int uart_irq; | ||
126 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
127 | unsigned int uart_tx_dma_channel; | ||
128 | unsigned int uart_rx_dma_channel; | ||
129 | #endif | ||
130 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
131 | int uart_cts_pin; | ||
132 | int uart_rts_pin; | ||
133 | #endif | ||
134 | }; | ||
135 | |||
136 | struct bfin_serial_res bfin_serial_resource[] = { | ||
137 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
138 | { | ||
139 | 0xFFC00400, | ||
140 | IRQ_UART0_RX, | ||
141 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
142 | CH_UART0_TX, | ||
143 | CH_UART0_RX, | ||
144 | #endif | ||
145 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
146 | CONFIG_UART0_CTS_PIN, | ||
147 | CONFIG_UART0_RTS_PIN, | ||
148 | #endif | ||
149 | }, | ||
150 | #endif | ||
151 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
152 | { | ||
153 | 0xFFC02000, | ||
154 | IRQ_UART1_RX, | ||
155 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
156 | CH_UART1_TX, | ||
157 | CH_UART1_RX, | ||
158 | #endif | ||
159 | #ifdef CONFIG_BFIN_UART1_CTSRTS | ||
160 | CONFIG_UART1_CTS_PIN, | ||
161 | CONFIG_UART1_RTS_PIN, | ||
162 | #endif | ||
163 | }, | ||
164 | #endif | ||
165 | }; | ||
166 | |||
167 | int nr_ports = ARRAY_SIZE(bfin_serial_resource); | ||
168 | |||
169 | #define DRIVER_NAME "bfin-uart" | ||
170 | |||
171 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) | ||
172 | { | ||
173 | |||
174 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
175 | peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
176 | peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
177 | #endif | ||
178 | |||
179 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
180 | peripheral_request(P_UART1_TX, DRIVER_NAME); | ||
181 | peripheral_request(P_UART1_RX, DRIVER_NAME); | ||
182 | #endif | ||
183 | |||
184 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
185 | if (uart->cts_pin >= 0) { | ||
186 | gpio_request(uart->cts_pin, DRIVER_NAME); | ||
187 | gpio_direction_input(uart->cts_pin); | ||
188 | } | ||
189 | |||
190 | if (uart->rts_pin >= 0) { | ||
191 | gpio_request(uart->rts_pin, DRIVER_NAME); | ||
192 | gpio_direction_output(uart->rts_pin, 0); | ||
193 | } | ||
194 | #endif | ||
195 | } | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h new file mode 100644 index 000000000000..cfd8ad4f1f2c --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h | |||
@@ -0,0 +1,142 @@ | |||
1 | /* | ||
2 | * Blackfin Infra-red Driver | ||
3 | * | ||
4 | * Copyright 2006-2008 Analog Devices Inc. | ||
5 | * | ||
6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
7 | * | ||
8 | * Licensed under the GPL-2 or later. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <linux/serial.h> | ||
13 | #include <asm/dma.h> | ||
14 | #include <asm/portmux.h> | ||
15 | |||
16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) | ||
19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
20 | #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) | ||
21 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
23 | |||
24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
26 | #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) | ||
27 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
28 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
29 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
30 | |||
31 | #ifdef CONFIG_SIR_BFIN_DMA | ||
32 | struct dma_rx_buf { | ||
33 | char *buf; | ||
34 | int head; | ||
35 | int tail; | ||
36 | }; | ||
37 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
38 | |||
39 | struct bfin_sir_port { | ||
40 | unsigned char __iomem *membase; | ||
41 | unsigned int irq; | ||
42 | unsigned int lsr; | ||
43 | unsigned long clk; | ||
44 | struct net_device *dev; | ||
45 | #ifdef CONFIG_SIR_BFIN_DMA | ||
46 | int tx_done; | ||
47 | struct dma_rx_buf rx_dma_buf; | ||
48 | struct timer_list rx_dma_timer; | ||
49 | int rx_dma_nrows; | ||
50 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
51 | unsigned int tx_dma_channel; | ||
52 | unsigned int rx_dma_channel; | ||
53 | }; | ||
54 | |||
55 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
56 | |||
57 | struct bfin_sir_port_res { | ||
58 | unsigned long base_addr; | ||
59 | int irq; | ||
60 | unsigned int rx_dma_channel; | ||
61 | unsigned int tx_dma_channel; | ||
62 | }; | ||
63 | |||
64 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
65 | #ifdef CONFIG_BFIN_SIR0 | ||
66 | { | ||
67 | 0xFFC00400, | ||
68 | IRQ_UART0_RX, | ||
69 | CH_UART0_RX, | ||
70 | CH_UART0_TX, | ||
71 | }, | ||
72 | #endif | ||
73 | #ifdef CONFIG_BFIN_SIR1 | ||
74 | { | ||
75 | 0xFFC02000, | ||
76 | IRQ_UART1_RX, | ||
77 | CH_UART1_RX, | ||
78 | CH_UART1_TX, | ||
79 | }, | ||
80 | #endif | ||
81 | }; | ||
82 | |||
83 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
84 | |||
85 | struct bfin_sir_self { | ||
86 | struct bfin_sir_port *sir_port; | ||
87 | spinlock_t lock; | ||
88 | unsigned int open; | ||
89 | int speed; | ||
90 | int newspeed; | ||
91 | |||
92 | struct sk_buff *txskb; | ||
93 | struct sk_buff *rxskb; | ||
94 | struct net_device_stats stats; | ||
95 | struct device *dev; | ||
96 | struct irlap_cb *irlap; | ||
97 | struct qos_info qos; | ||
98 | |||
99 | iobuff_t tx_buff; | ||
100 | iobuff_t rx_buff; | ||
101 | |||
102 | struct work_struct work; | ||
103 | int mtt; | ||
104 | }; | ||
105 | |||
106 | static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) | ||
107 | { | ||
108 | unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); | ||
109 | port->lsr |= (lsr & (BI|FE|PE|OE)); | ||
110 | return lsr | port->lsr; | ||
111 | } | ||
112 | |||
113 | static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) | ||
114 | { | ||
115 | port->lsr = 0; | ||
116 | bfin_read16(port->membase + OFFSET_LSR); | ||
117 | } | ||
118 | |||
119 | #define DRIVER_NAME "bfin_sir" | ||
120 | |||
121 | static int bfin_sir_hw_init(void) | ||
122 | { | ||
123 | int ret = -ENODEV; | ||
124 | #ifdef CONFIG_BFIN_SIR0 | ||
125 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
126 | if (ret) | ||
127 | return ret; | ||
128 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
129 | if (ret) | ||
130 | return ret; | ||
131 | #endif | ||
132 | |||
133 | #ifdef CONFIG_BFIN_SIR1 | ||
134 | ret = peripheral_request(P_UART1_TX, DRIVER_NAME); | ||
135 | if (ret) | ||
136 | return ret; | ||
137 | ret = peripheral_request(P_UART1_RX, DRIVER_NAME); | ||
138 | if (ret) | ||
139 | return ret; | ||
140 | #endif | ||
141 | return ret; | ||
142 | } | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h new file mode 100644 index 000000000000..297821e2d79a --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/blackfin.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * | ||
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License as published by | ||
18 | * the Free Software Foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * This program is distributed in the hope that it will be useful, | ||
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
24 | * GNU General Public License for more details. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License | ||
27 | * along with this program; see the file COPYING. | ||
28 | * If not, write to the Free Software Foundation, | ||
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
30 | */ | ||
31 | |||
32 | #ifndef _MACH_BLACKFIN_H_ | ||
33 | #define _MACH_BLACKFIN_H_ | ||
34 | |||
35 | #define BF527_FAMILY | ||
36 | |||
37 | #include "bf527.h" | ||
38 | #include "mem_map.h" | ||
39 | #include "defBF522.h" | ||
40 | #include "anomaly.h" | ||
41 | |||
42 | #if defined(CONFIG_BF527) || defined(CONFIG_BF526) | ||
43 | #include "defBF527.h" | ||
44 | #endif | ||
45 | |||
46 | #if defined(CONFIG_BF525) || defined(CONFIG_BF524) | ||
47 | #include "defBF525.h" | ||
48 | #endif | ||
49 | |||
50 | #if !defined(__ASSEMBLY__) | ||
51 | #include "cdefBF522.h" | ||
52 | |||
53 | #if defined(CONFIG_BF527) || defined(CONFIG_BF526) | ||
54 | #include "cdefBF527.h" | ||
55 | #endif | ||
56 | |||
57 | #if defined(CONFIG_BF525) || defined(CONFIG_BF524) | ||
58 | #include "cdefBF525.h" | ||
59 | #endif | ||
60 | #endif | ||
61 | |||
62 | /* UART_IIR Register */ | ||
63 | #define STATUS(x) ((x << 1) & 0x06) | ||
64 | #define STATUS_P1 0x02 | ||
65 | #define STATUS_P0 0x01 | ||
66 | |||
67 | #define BFIN_UART_NR_PORTS 2 | ||
68 | |||
69 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | ||
70 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | ||
71 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | ||
72 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | ||
73 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
74 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
75 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
76 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
77 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
78 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
79 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
80 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
81 | |||
82 | /* DPMC*/ | ||
83 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
84 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
85 | #define STOPCK_OFF STOPCK | ||
86 | |||
87 | /* PLL_DIV Masks */ | ||
88 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | ||
89 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | ||
90 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | ||
91 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | ||
92 | |||
93 | #endif | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h new file mode 100644 index 000000000000..663c2bbdfd91 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/cdefbf522.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: system mmr register map | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * | ||
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License as published by | ||
18 | * the Free Software Foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * This program is distributed in the hope that it will be useful, | ||
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
24 | * GNU General Public License for more details. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License | ||
27 | * along with this program; see the file COPYING. | ||
28 | * If not, write to the Free Software Foundation, | ||
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
30 | */ | ||
31 | |||
32 | #ifndef _CDEF_BF522_H | ||
33 | #define _CDEF_BF522_H | ||
34 | |||
35 | /* include all Core registers and bit definitions */ | ||
36 | #include "defBF522.h" | ||
37 | |||
38 | /* include core specific register pointer definitions */ | ||
39 | #include <asm/cdef_LPBlackfin.h> | ||
40 | |||
41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ | ||
42 | |||
43 | /* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
44 | #include "cdefBF52x_base.h" | ||
45 | |||
46 | #endif /* _CDEF_BF522_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h new file mode 100644 index 000000000000..00377eb59b75 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h | |||
@@ -0,0 +1,461 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/cdefbf525.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: system mmr register map | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * | ||
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License as published by | ||
18 | * the Free Software Foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * This program is distributed in the hope that it will be useful, | ||
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
24 | * GNU General Public License for more details. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License | ||
27 | * along with this program; see the file COPYING. | ||
28 | * If not, write to the Free Software Foundation, | ||
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
30 | */ | ||
31 | |||
32 | #ifndef _CDEF_BF525_H | ||
33 | #define _CDEF_BF525_H | ||
34 | |||
35 | /* include all Core registers and bit definitions */ | ||
36 | #include "defBF525.h" | ||
37 | |||
38 | /* include core specific register pointer definitions */ | ||
39 | #include <asm/cdef_LPBlackfin.h> | ||
40 | |||
41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ | ||
42 | |||
43 | /* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
44 | #include "cdefBF52x_base.h" | ||
45 | |||
46 | /* The following are the #defines needed by ADSP-BF525 that are not in the common header */ | ||
47 | |||
48 | /* USB Control Registers */ | ||
49 | |||
50 | #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) | ||
51 | #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) | ||
52 | #define bfin_read_USB_POWER() bfin_read16(USB_POWER) | ||
53 | #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) | ||
54 | #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) | ||
55 | #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) | ||
56 | #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) | ||
57 | #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) | ||
58 | #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) | ||
59 | #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) | ||
60 | #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) | ||
61 | #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) | ||
62 | #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) | ||
63 | #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) | ||
64 | #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) | ||
65 | #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) | ||
66 | #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) | ||
67 | #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) | ||
68 | #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) | ||
69 | #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) | ||
70 | #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) | ||
71 | #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) | ||
72 | #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) | ||
73 | #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) | ||
74 | #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) | ||
75 | #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) | ||
76 | |||
77 | /* USB Packet Control Registers */ | ||
78 | |||
79 | #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) | ||
80 | #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) | ||
81 | #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) | ||
82 | #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) | ||
83 | #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) | ||
84 | #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) | ||
85 | #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) | ||
86 | #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) | ||
87 | #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) | ||
88 | #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) | ||
89 | #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) | ||
90 | #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) | ||
91 | #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) | ||
92 | #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) | ||
93 | #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) | ||
94 | #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) | ||
95 | #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) | ||
96 | #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) | ||
97 | #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) | ||
98 | #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) | ||
99 | #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) | ||
100 | #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) | ||
101 | #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) | ||
102 | #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) | ||
103 | #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) | ||
104 | #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) | ||
105 | |||
106 | /* USB Endpoint FIFO Registers */ | ||
107 | |||
108 | #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) | ||
109 | #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) | ||
110 | #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) | ||
111 | #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) | ||
112 | #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) | ||
113 | #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) | ||
114 | #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) | ||
115 | #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) | ||
116 | #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) | ||
117 | #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) | ||
118 | #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) | ||
119 | #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) | ||
120 | #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) | ||
121 | #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) | ||
122 | #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) | ||
123 | #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) | ||
124 | |||
125 | /* USB OTG Control Registers */ | ||
126 | |||
127 | #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) | ||
128 | #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) | ||
129 | #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) | ||
130 | #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) | ||
131 | #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) | ||
132 | #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) | ||
133 | |||
134 | /* USB Phy Control Registers */ | ||
135 | |||
136 | #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) | ||
137 | #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) | ||
138 | #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) | ||
139 | #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) | ||
140 | #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) | ||
141 | #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) | ||
142 | #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) | ||
143 | #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) | ||
144 | #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) | ||
145 | #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) | ||
146 | |||
147 | /* (APHY_CNTRL is for ADI usage only) */ | ||
148 | |||
149 | #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) | ||
150 | #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) | ||
151 | |||
152 | /* (APHY_CALIB is for ADI usage only) */ | ||
153 | |||
154 | #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) | ||
155 | #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) | ||
156 | |||
157 | #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) | ||
158 | #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) | ||
159 | |||
160 | /* (PHY_TEST is for ADI usage only) */ | ||
161 | |||
162 | #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) | ||
163 | #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) | ||
164 | |||
165 | #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) | ||
166 | #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) | ||
167 | #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) | ||
168 | #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) | ||
169 | |||
170 | /* USB Endpoint 0 Control Registers */ | ||
171 | |||
172 | #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) | ||
173 | #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) | ||
174 | #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) | ||
175 | #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) | ||
176 | #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) | ||
177 | #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) | ||
178 | #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) | ||
179 | #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) | ||
180 | #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) | ||
181 | #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) | ||
182 | #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) | ||
183 | #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) | ||
184 | #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) | ||
185 | #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) | ||
186 | #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) | ||
187 | #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) | ||
188 | #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) | ||
189 | #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) | ||
190 | #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) | ||
191 | #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) | ||
192 | |||
193 | /* USB Endpoint 1 Control Registers */ | ||
194 | |||
195 | #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) | ||
196 | #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) | ||
197 | #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) | ||
198 | #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) | ||
199 | #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) | ||
200 | #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) | ||
201 | #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) | ||
202 | #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) | ||
203 | #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) | ||
204 | #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) | ||
205 | #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) | ||
206 | #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) | ||
207 | #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) | ||
208 | #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) | ||
209 | #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) | ||
210 | #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) | ||
211 | #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) | ||
212 | #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) | ||
213 | #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) | ||
214 | #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) | ||
215 | |||
216 | /* USB Endpoint 2 Control Registers */ | ||
217 | |||
218 | #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) | ||
219 | #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) | ||
220 | #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) | ||
221 | #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) | ||
222 | #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) | ||
223 | #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) | ||
224 | #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) | ||
225 | #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) | ||
226 | #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) | ||
227 | #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) | ||
228 | #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) | ||
229 | #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) | ||
230 | #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) | ||
231 | #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) | ||
232 | #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) | ||
233 | #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) | ||
234 | #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) | ||
235 | #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) | ||
236 | #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) | ||
237 | #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) | ||
238 | |||
239 | /* USB Endpoint 3 Control Registers */ | ||
240 | |||
241 | #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) | ||
242 | #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) | ||
243 | #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) | ||
244 | #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) | ||
245 | #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) | ||
246 | #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) | ||
247 | #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) | ||
248 | #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) | ||
249 | #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) | ||
250 | #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) | ||
251 | #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) | ||
252 | #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) | ||
253 | #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) | ||
254 | #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) | ||
255 | #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) | ||
256 | #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) | ||
257 | #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) | ||
258 | #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) | ||
259 | #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) | ||
260 | #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) | ||
261 | |||
262 | /* USB Endpoint 4 Control Registers */ | ||
263 | |||
264 | #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) | ||
265 | #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) | ||
266 | #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) | ||
267 | #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) | ||
268 | #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) | ||
269 | #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) | ||
270 | #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) | ||
271 | #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) | ||
272 | #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) | ||
273 | #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) | ||
274 | #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) | ||
275 | #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) | ||
276 | #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) | ||
277 | #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) | ||
278 | #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) | ||
279 | #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) | ||
280 | #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) | ||
281 | #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) | ||
282 | #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) | ||
283 | #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) | ||
284 | |||
285 | /* USB Endpoint 5 Control Registers */ | ||
286 | |||
287 | #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) | ||
288 | #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) | ||
289 | #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) | ||
290 | #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) | ||
291 | #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) | ||
292 | #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) | ||
293 | #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) | ||
294 | #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) | ||
295 | #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) | ||
296 | #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) | ||
297 | #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) | ||
298 | #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) | ||
299 | #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) | ||
300 | #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) | ||
301 | #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) | ||
302 | #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) | ||
303 | #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) | ||
304 | #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) | ||
305 | #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) | ||
306 | #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) | ||
307 | |||
308 | /* USB Endpoint 6 Control Registers */ | ||
309 | |||
310 | #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) | ||
311 | #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) | ||
312 | #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) | ||
313 | #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) | ||
314 | #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) | ||
315 | #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) | ||
316 | #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) | ||
317 | #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) | ||
318 | #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) | ||
319 | #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) | ||
320 | #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) | ||
321 | #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) | ||
322 | #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) | ||
323 | #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) | ||
324 | #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) | ||
325 | #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) | ||
326 | #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) | ||
327 | #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) | ||
328 | #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) | ||
329 | #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) | ||
330 | |||
331 | /* USB Endpoint 7 Control Registers */ | ||
332 | |||
333 | #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) | ||
334 | #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) | ||
335 | #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) | ||
336 | #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) | ||
337 | #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) | ||
338 | #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) | ||
339 | #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) | ||
340 | #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) | ||
341 | #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) | ||
342 | #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) | ||
343 | #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) | ||
344 | #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) | ||
345 | #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) | ||
346 | #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) | ||
347 | #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) | ||
348 | #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) | ||
349 | #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) | ||
350 | #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) | ||
351 | #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) | ||
352 | #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) | ||
353 | |||
354 | #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) | ||
355 | #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) | ||
356 | |||
357 | /* USB Channel 0 Config Registers */ | ||
358 | |||
359 | #define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) | ||
360 | #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) | ||
361 | #define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) | ||
362 | #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) | ||
363 | #define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) | ||
364 | #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) | ||
365 | #define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) | ||
366 | #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) | ||
367 | #define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) | ||
368 | #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) | ||
369 | |||
370 | /* USB Channel 1 Config Registers */ | ||
371 | |||
372 | #define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) | ||
373 | #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) | ||
374 | #define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) | ||
375 | #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) | ||
376 | #define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) | ||
377 | #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) | ||
378 | #define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) | ||
379 | #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) | ||
380 | #define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) | ||
381 | #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) | ||
382 | |||
383 | /* USB Channel 2 Config Registers */ | ||
384 | |||
385 | #define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) | ||
386 | #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) | ||
387 | #define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) | ||
388 | #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) | ||
389 | #define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) | ||
390 | #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) | ||
391 | #define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) | ||
392 | #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) | ||
393 | #define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) | ||
394 | #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) | ||
395 | |||
396 | /* USB Channel 3 Config Registers */ | ||
397 | |||
398 | #define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) | ||
399 | #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) | ||
400 | #define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) | ||
401 | #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) | ||
402 | #define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) | ||
403 | #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) | ||
404 | #define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) | ||
405 | #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) | ||
406 | #define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) | ||
407 | #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) | ||
408 | |||
409 | /* USB Channel 4 Config Registers */ | ||
410 | |||
411 | #define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) | ||
412 | #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) | ||
413 | #define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) | ||
414 | #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) | ||
415 | #define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) | ||
416 | #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) | ||
417 | #define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) | ||
418 | #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) | ||
419 | #define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) | ||
420 | #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) | ||
421 | |||
422 | /* USB Channel 5 Config Registers */ | ||
423 | |||
424 | #define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) | ||
425 | #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) | ||
426 | #define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) | ||
427 | #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) | ||
428 | #define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) | ||
429 | #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) | ||
430 | #define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) | ||
431 | #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) | ||
432 | #define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) | ||
433 | #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) | ||
434 | |||
435 | /* USB Channel 6 Config Registers */ | ||
436 | |||
437 | #define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) | ||
438 | #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) | ||
439 | #define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) | ||
440 | #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) | ||
441 | #define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) | ||
442 | #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) | ||
443 | #define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) | ||
444 | #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) | ||
445 | #define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) | ||
446 | #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) | ||
447 | |||
448 | /* USB Channel 7 Config Registers */ | ||
449 | |||
450 | #define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) | ||
451 | #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) | ||
452 | #define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) | ||
453 | #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) | ||
454 | #define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) | ||
455 | #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) | ||
456 | #define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) | ||
457 | #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) | ||
458 | #define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) | ||
459 | #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) | ||
460 | |||
461 | #endif /* _CDEF_BF525_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h new file mode 100644 index 000000000000..fca8db708119 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h | |||
@@ -0,0 +1,626 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/cdefbf527.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: system mmr register map | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * | ||
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License as published by | ||
18 | * the Free Software Foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * This program is distributed in the hope that it will be useful, | ||
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
24 | * GNU General Public License for more details. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License | ||
27 | * along with this program; see the file COPYING. | ||
28 | * If not, write to the Free Software Foundation, | ||
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
30 | */ | ||
31 | |||
32 | #ifndef _CDEF_BF527_H | ||
33 | #define _CDEF_BF527_H | ||
34 | |||
35 | /* include all Core registers and bit definitions */ | ||
36 | #include "defBF527.h" | ||
37 | |||
38 | /* include core specific register pointer definitions */ | ||
39 | #include <asm/cdef_LPBlackfin.h> | ||
40 | |||
41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ | ||
42 | |||
43 | /* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
44 | #include "cdefBF52x_base.h" | ||
45 | |||
46 | /* The following are the #defines needed by ADSP-BF527 that are not in the common header */ | ||
47 | |||
48 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
49 | |||
50 | #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) | ||
51 | #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) | ||
52 | #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) | ||
53 | #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) | ||
54 | #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) | ||
55 | #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) | ||
56 | #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) | ||
57 | #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) | ||
58 | #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) | ||
59 | #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) | ||
60 | #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) | ||
61 | #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) | ||
62 | #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) | ||
63 | #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) | ||
64 | #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) | ||
65 | #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) | ||
66 | #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) | ||
67 | #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) | ||
68 | #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) | ||
69 | #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) | ||
70 | #define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) | ||
71 | #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) | ||
72 | #define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) | ||
73 | #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) | ||
74 | #define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) | ||
75 | #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) | ||
76 | #define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) | ||
77 | #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) | ||
78 | #define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) | ||
79 | #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) | ||
80 | #define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) | ||
81 | #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) | ||
82 | #define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) | ||
83 | #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) | ||
84 | #define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) | ||
85 | #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) | ||
86 | #define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) | ||
87 | #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) | ||
88 | |||
89 | #define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) | ||
90 | #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) | ||
91 | #define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) | ||
92 | #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) | ||
93 | #define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) | ||
94 | #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) | ||
95 | #define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) | ||
96 | #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) | ||
97 | #define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) | ||
98 | #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) | ||
99 | #define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) | ||
100 | #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) | ||
101 | #define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) | ||
102 | #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) | ||
103 | #define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) | ||
104 | #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) | ||
105 | |||
106 | #define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) | ||
107 | #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) | ||
108 | #define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) | ||
109 | #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) | ||
110 | #define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) | ||
111 | #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) | ||
112 | #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) | ||
113 | #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) | ||
114 | #define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) | ||
115 | #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) | ||
116 | |||
117 | #define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) | ||
118 | #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) | ||
119 | #define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) | ||
120 | #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) | ||
121 | #define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) | ||
122 | #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) | ||
123 | #define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) | ||
124 | #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) | ||
125 | #define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) | ||
126 | #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) | ||
127 | #define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) | ||
128 | #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) | ||
129 | #define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) | ||
130 | #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) | ||
131 | #define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) | ||
132 | #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) | ||
133 | #define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) | ||
134 | #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) | ||
135 | #define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) | ||
136 | #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) | ||
137 | #define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) | ||
138 | #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) | ||
139 | #define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) | ||
140 | #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) | ||
141 | #define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) | ||
142 | #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) | ||
143 | #define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) | ||
144 | #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) | ||
145 | #define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) | ||
146 | #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) | ||
147 | #define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) | ||
148 | #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) | ||
149 | #define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) | ||
150 | #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) | ||
151 | #define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) | ||
152 | #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) | ||
153 | #define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) | ||
154 | #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) | ||
155 | #define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) | ||
156 | #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) | ||
157 | #define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) | ||
158 | #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) | ||
159 | #define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) | ||
160 | #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) | ||
161 | #define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) | ||
162 | #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) | ||
163 | #define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) | ||
164 | #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) | ||
165 | |||
166 | #define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) | ||
167 | #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) | ||
168 | #define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) | ||
169 | #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) | ||
170 | #define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) | ||
171 | #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) | ||
172 | #define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) | ||
173 | #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) | ||
174 | #define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) | ||
175 | #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) | ||
176 | #define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) | ||
177 | #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) | ||
178 | #define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) | ||
179 | #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) | ||
180 | #define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) | ||
181 | #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) | ||
182 | #define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) | ||
183 | #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) | ||
184 | #define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) | ||
185 | #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) | ||
186 | #define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) | ||
187 | #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) | ||
188 | #define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) | ||
189 | #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) | ||
190 | #define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) | ||
191 | #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) | ||
192 | #define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) | ||
193 | #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) | ||
194 | #define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) | ||
195 | #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) | ||
196 | #define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) | ||
197 | #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) | ||
198 | #define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) | ||
199 | #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) | ||
200 | #define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) | ||
201 | #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) | ||
202 | #define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) | ||
203 | #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) | ||
204 | #define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) | ||
205 | #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) | ||
206 | #define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) | ||
207 | #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) | ||
208 | #define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) | ||
209 | #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) | ||
210 | #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) | ||
211 | #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) | ||
212 | |||
213 | /* USB Control Registers */ | ||
214 | |||
215 | #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) | ||
216 | #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) | ||
217 | #define bfin_read_USB_POWER() bfin_read16(USB_POWER) | ||
218 | #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) | ||
219 | #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) | ||
220 | #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) | ||
221 | #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) | ||
222 | #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) | ||
223 | #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) | ||
224 | #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) | ||
225 | #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) | ||
226 | #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) | ||
227 | #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) | ||
228 | #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) | ||
229 | #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) | ||
230 | #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) | ||
231 | #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) | ||
232 | #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) | ||
233 | #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) | ||
234 | #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) | ||
235 | #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) | ||
236 | #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) | ||
237 | #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) | ||
238 | #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) | ||
239 | #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) | ||
240 | #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) | ||
241 | |||
242 | /* USB Packet Control Registers */ | ||
243 | |||
244 | #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) | ||
245 | #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) | ||
246 | #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) | ||
247 | #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) | ||
248 | #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) | ||
249 | #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) | ||
250 | #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) | ||
251 | #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) | ||
252 | #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) | ||
253 | #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) | ||
254 | #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) | ||
255 | #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) | ||
256 | #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) | ||
257 | #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) | ||
258 | #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) | ||
259 | #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) | ||
260 | #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) | ||
261 | #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) | ||
262 | #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) | ||
263 | #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) | ||
264 | #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) | ||
265 | #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) | ||
266 | #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) | ||
267 | #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) | ||
268 | #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) | ||
269 | #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) | ||
270 | |||
271 | /* USB Endpoint FIFO Registers */ | ||
272 | |||
273 | #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) | ||
274 | #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) | ||
275 | #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) | ||
276 | #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) | ||
277 | #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) | ||
278 | #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) | ||
279 | #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) | ||
280 | #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) | ||
281 | #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) | ||
282 | #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) | ||
283 | #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) | ||
284 | #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) | ||
285 | #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) | ||
286 | #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) | ||
287 | #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) | ||
288 | #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) | ||
289 | |||
290 | /* USB OTG Control Registers */ | ||
291 | |||
292 | #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) | ||
293 | #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) | ||
294 | #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) | ||
295 | #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) | ||
296 | #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) | ||
297 | #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) | ||
298 | |||
299 | /* USB Phy Control Registers */ | ||
300 | |||
301 | #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) | ||
302 | #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) | ||
303 | #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) | ||
304 | #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) | ||
305 | #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) | ||
306 | #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) | ||
307 | #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) | ||
308 | #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) | ||
309 | #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) | ||
310 | #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) | ||
311 | |||
312 | /* (APHY_CNTRL is for ADI usage only) */ | ||
313 | |||
314 | #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) | ||
315 | #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) | ||
316 | |||
317 | /* (APHY_CALIB is for ADI usage only) */ | ||
318 | |||
319 | #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) | ||
320 | #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) | ||
321 | |||
322 | #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) | ||
323 | #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) | ||
324 | |||
325 | /* (PHY_TEST is for ADI usage only) */ | ||
326 | |||
327 | #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) | ||
328 | #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) | ||
329 | |||
330 | #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) | ||
331 | #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) | ||
332 | #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) | ||
333 | #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) | ||
334 | |||
335 | /* USB Endpoint 0 Control Registers */ | ||
336 | |||
337 | #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) | ||
338 | #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) | ||
339 | #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) | ||
340 | #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) | ||
341 | #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) | ||
342 | #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) | ||
343 | #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) | ||
344 | #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) | ||
345 | #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) | ||
346 | #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) | ||
347 | #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) | ||
348 | #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) | ||
349 | #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) | ||
350 | #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) | ||
351 | #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) | ||
352 | #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) | ||
353 | #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) | ||
354 | #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) | ||
355 | #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) | ||
356 | #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) | ||
357 | |||
358 | /* USB Endpoint 1 Control Registers */ | ||
359 | |||
360 | #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) | ||
361 | #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) | ||
362 | #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) | ||
363 | #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) | ||
364 | #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) | ||
365 | #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) | ||
366 | #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) | ||
367 | #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) | ||
368 | #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) | ||
369 | #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) | ||
370 | #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) | ||
371 | #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) | ||
372 | #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) | ||
373 | #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) | ||
374 | #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) | ||
375 | #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) | ||
376 | #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) | ||
377 | #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) | ||
378 | #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) | ||
379 | #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) | ||
380 | |||
381 | /* USB Endpoint 2 Control Registers */ | ||
382 | |||
383 | #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) | ||
384 | #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) | ||
385 | #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) | ||
386 | #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) | ||
387 | #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) | ||
388 | #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) | ||
389 | #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) | ||
390 | #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) | ||
391 | #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) | ||
392 | #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) | ||
393 | #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) | ||
394 | #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) | ||
395 | #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) | ||
396 | #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) | ||
397 | #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) | ||
398 | #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) | ||
399 | #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) | ||
400 | #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) | ||
401 | #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) | ||
402 | #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) | ||
403 | |||
404 | /* USB Endpoint 3 Control Registers */ | ||
405 | |||
406 | #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) | ||
407 | #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) | ||
408 | #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) | ||
409 | #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) | ||
410 | #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) | ||
411 | #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) | ||
412 | #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) | ||
413 | #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) | ||
414 | #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) | ||
415 | #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) | ||
416 | #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) | ||
417 | #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) | ||
418 | #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) | ||
419 | #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) | ||
420 | #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) | ||
421 | #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) | ||
422 | #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) | ||
423 | #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) | ||
424 | #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) | ||
425 | #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) | ||
426 | |||
427 | /* USB Endpoint 4 Control Registers */ | ||
428 | |||
429 | #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) | ||
430 | #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) | ||
431 | #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) | ||
432 | #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) | ||
433 | #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) | ||
434 | #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) | ||
435 | #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) | ||
436 | #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) | ||
437 | #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) | ||
438 | #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) | ||
439 | #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) | ||
440 | #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) | ||
441 | #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) | ||
442 | #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) | ||
443 | #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) | ||
444 | #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) | ||
445 | #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) | ||
446 | #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) | ||
447 | #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) | ||
448 | #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) | ||
449 | |||
450 | /* USB Endpoint 5 Control Registers */ | ||
451 | |||
452 | #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) | ||
453 | #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) | ||
454 | #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) | ||
455 | #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) | ||
456 | #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) | ||
457 | #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) | ||
458 | #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) | ||
459 | #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) | ||
460 | #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) | ||
461 | #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) | ||
462 | #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) | ||
463 | #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) | ||
464 | #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) | ||
465 | #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) | ||
466 | #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) | ||
467 | #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) | ||
468 | #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) | ||
469 | #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) | ||
470 | #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) | ||
471 | #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) | ||
472 | |||
473 | /* USB Endpoint 6 Control Registers */ | ||
474 | |||
475 | #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) | ||
476 | #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) | ||
477 | #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) | ||
478 | #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) | ||
479 | #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) | ||
480 | #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) | ||
481 | #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) | ||
482 | #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) | ||
483 | #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) | ||
484 | #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) | ||
485 | #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) | ||
486 | #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) | ||
487 | #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) | ||
488 | #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) | ||
489 | #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) | ||
490 | #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) | ||
491 | #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) | ||
492 | #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) | ||
493 | #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) | ||
494 | #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) | ||
495 | |||
496 | /* USB Endpoint 7 Control Registers */ | ||
497 | |||
498 | #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) | ||
499 | #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) | ||
500 | #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) | ||
501 | #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) | ||
502 | #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) | ||
503 | #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) | ||
504 | #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) | ||
505 | #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) | ||
506 | #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) | ||
507 | #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) | ||
508 | #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) | ||
509 | #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) | ||
510 | #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) | ||
511 | #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) | ||
512 | #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) | ||
513 | #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) | ||
514 | #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) | ||
515 | #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) | ||
516 | #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) | ||
517 | #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) | ||
518 | |||
519 | #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) | ||
520 | #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) | ||
521 | |||
522 | /* USB Channel 0 Config Registers */ | ||
523 | |||
524 | #define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) | ||
525 | #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) | ||
526 | #define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) | ||
527 | #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) | ||
528 | #define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) | ||
529 | #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) | ||
530 | #define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) | ||
531 | #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) | ||
532 | #define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) | ||
533 | #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) | ||
534 | |||
535 | /* USB Channel 1 Config Registers */ | ||
536 | |||
537 | #define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) | ||
538 | #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) | ||
539 | #define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) | ||
540 | #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) | ||
541 | #define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) | ||
542 | #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) | ||
543 | #define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) | ||
544 | #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) | ||
545 | #define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) | ||
546 | #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) | ||
547 | |||
548 | /* USB Channel 2 Config Registers */ | ||
549 | |||
550 | #define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) | ||
551 | #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) | ||
552 | #define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) | ||
553 | #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) | ||
554 | #define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) | ||
555 | #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) | ||
556 | #define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) | ||
557 | #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) | ||
558 | #define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) | ||
559 | #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) | ||
560 | |||
561 | /* USB Channel 3 Config Registers */ | ||
562 | |||
563 | #define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) | ||
564 | #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) | ||
565 | #define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) | ||
566 | #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) | ||
567 | #define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) | ||
568 | #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) | ||
569 | #define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) | ||
570 | #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) | ||
571 | #define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) | ||
572 | #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) | ||
573 | |||
574 | /* USB Channel 4 Config Registers */ | ||
575 | |||
576 | #define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) | ||
577 | #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) | ||
578 | #define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) | ||
579 | #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) | ||
580 | #define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) | ||
581 | #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) | ||
582 | #define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) | ||
583 | #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) | ||
584 | #define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) | ||
585 | #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) | ||
586 | |||
587 | /* USB Channel 5 Config Registers */ | ||
588 | |||
589 | #define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) | ||
590 | #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) | ||
591 | #define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) | ||
592 | #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) | ||
593 | #define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) | ||
594 | #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) | ||
595 | #define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) | ||
596 | #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) | ||
597 | #define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) | ||
598 | #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) | ||
599 | |||
600 | /* USB Channel 6 Config Registers */ | ||
601 | |||
602 | #define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) | ||
603 | #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) | ||
604 | #define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) | ||
605 | #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) | ||
606 | #define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) | ||
607 | #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) | ||
608 | #define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) | ||
609 | #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) | ||
610 | #define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) | ||
611 | #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) | ||
612 | |||
613 | /* USB Channel 7 Config Registers */ | ||
614 | |||
615 | #define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) | ||
616 | #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) | ||
617 | #define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) | ||
618 | #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) | ||
619 | #define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) | ||
620 | #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) | ||
621 | #define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) | ||
622 | #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) | ||
623 | #define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) | ||
624 | #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) | ||
625 | |||
626 | #endif /* _CDEF_BF527_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h new file mode 100644 index 000000000000..9a814b9a12b9 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h | |||
@@ -0,0 +1,1204 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _CDEF_BF52X_H | ||
32 | #define _CDEF_BF52X_H | ||
33 | |||
34 | #include <asm/system.h> | ||
35 | #include <asm/blackfin.h> | ||
36 | |||
37 | #include "defBF52x_base.h" | ||
38 | |||
39 | /* Include core specific register pointer definitions */ | ||
40 | #include <asm/cdef_LPBlackfin.h> | ||
41 | |||
42 | /* ==== begin from cdefBF534.h ==== */ | ||
43 | |||
44 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
45 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | ||
46 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
47 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
48 | { | ||
49 | unsigned long flags, iwr0, iwr1; | ||
50 | |||
51 | if (val == bfin_read_PLL_CTL()) | ||
52 | return; | ||
53 | |||
54 | local_irq_save(flags); | ||
55 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
56 | iwr0 = bfin_read32(SIC_IWR0); | ||
57 | iwr1 = bfin_read32(SIC_IWR1); | ||
58 | /* Only allow PPL Wakeup) */ | ||
59 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
60 | bfin_write32(SIC_IWR1, 0); | ||
61 | |||
62 | bfin_write16(PLL_CTL, val); | ||
63 | SSYNC(); | ||
64 | asm("IDLE;"); | ||
65 | |||
66 | bfin_write32(SIC_IWR0, iwr0); | ||
67 | bfin_write32(SIC_IWR1, iwr1); | ||
68 | local_irq_restore(flags); | ||
69 | } | ||
70 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
71 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | ||
72 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
73 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
74 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
75 | { | ||
76 | unsigned long flags, iwr0, iwr1; | ||
77 | |||
78 | if (val == bfin_read_VR_CTL()) | ||
79 | return; | ||
80 | |||
81 | local_irq_save(flags); | ||
82 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
83 | iwr0 = bfin_read32(SIC_IWR0); | ||
84 | iwr1 = bfin_read32(SIC_IWR1); | ||
85 | /* Only allow PPL Wakeup) */ | ||
86 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
87 | bfin_write32(SIC_IWR1, 0); | ||
88 | |||
89 | bfin_write16(VR_CTL, val); | ||
90 | SSYNC(); | ||
91 | asm("IDLE;"); | ||
92 | |||
93 | bfin_write32(SIC_IWR0, iwr0); | ||
94 | bfin_write32(SIC_IWR1, iwr1); | ||
95 | local_irq_restore(flags); | ||
96 | } | ||
97 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
98 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | ||
99 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
100 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | ||
101 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
102 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | ||
103 | |||
104 | |||
105 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
106 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
107 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | ||
108 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
109 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | ||
110 | |||
111 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) | ||
112 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) | ||
113 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | ||
114 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | ||
115 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) | ||
116 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) | ||
117 | |||
118 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | ||
119 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | ||
120 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | ||
121 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | ||
122 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | ||
123 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | ||
124 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | ||
125 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | ||
126 | |||
127 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | ||
128 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | ||
129 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) | ||
130 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) | ||
131 | |||
132 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | ||
133 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | ||
134 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) | ||
135 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) | ||
136 | |||
137 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ | ||
138 | |||
139 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | ||
140 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | ||
141 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | ||
142 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | ||
143 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | ||
144 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | ||
145 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | ||
146 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | ||
147 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) | ||
148 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) | ||
149 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | ||
150 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | ||
151 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | ||
152 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | ||
153 | |||
154 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
155 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | ||
156 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | ||
157 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | ||
158 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | ||
159 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | ||
160 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | ||
161 | |||
162 | |||
163 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
164 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | ||
165 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | ||
166 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | ||
167 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | ||
168 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | ||
169 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | ||
170 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | ||
171 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | ||
172 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | ||
173 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | ||
174 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | ||
175 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) | ||
176 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | ||
177 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | ||
178 | |||
179 | |||
180 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
181 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | ||
182 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | ||
183 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | ||
184 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | ||
185 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | ||
186 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | ||
187 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) | ||
188 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) | ||
189 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | ||
190 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | ||
191 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) | ||
192 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) | ||
193 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | ||
194 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | ||
195 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | ||
196 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | ||
197 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | ||
198 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | ||
199 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) | ||
200 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) | ||
201 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | ||
202 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | ||
203 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | ||
204 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | ||
205 | |||
206 | |||
207 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | ||
208 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) | ||
209 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) | ||
210 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) | ||
211 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) | ||
212 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) | ||
213 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) | ||
214 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) | ||
215 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) | ||
216 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) | ||
217 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) | ||
218 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) | ||
219 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) | ||
220 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) | ||
221 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) | ||
222 | |||
223 | |||
224 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
225 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
226 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | ||
227 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
228 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | ||
229 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
230 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | ||
231 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
232 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | ||
233 | |||
234 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
235 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | ||
236 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
237 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | ||
238 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
239 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | ||
240 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
241 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | ||
242 | |||
243 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
244 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | ||
245 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
246 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | ||
247 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
248 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | ||
249 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
250 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | ||
251 | |||
252 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | ||
253 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) | ||
254 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | ||
255 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) | ||
256 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | ||
257 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) | ||
258 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | ||
259 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) | ||
260 | |||
261 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | ||
262 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) | ||
263 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | ||
264 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) | ||
265 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | ||
266 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) | ||
267 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | ||
268 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) | ||
269 | |||
270 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | ||
271 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) | ||
272 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | ||
273 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) | ||
274 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | ||
275 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) | ||
276 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | ||
277 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) | ||
278 | |||
279 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | ||
280 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) | ||
281 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | ||
282 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) | ||
283 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | ||
284 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) | ||
285 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | ||
286 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) | ||
287 | |||
288 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | ||
289 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) | ||
290 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | ||
291 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) | ||
292 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | ||
293 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) | ||
294 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | ||
295 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) | ||
296 | |||
297 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | ||
298 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) | ||
299 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | ||
300 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) | ||
301 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) | ||
302 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) | ||
303 | |||
304 | |||
305 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
306 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) | ||
307 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) | ||
308 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) | ||
309 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) | ||
310 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) | ||
311 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) | ||
312 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) | ||
313 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) | ||
314 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) | ||
315 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) | ||
316 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) | ||
317 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) | ||
318 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) | ||
319 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) | ||
320 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) | ||
321 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) | ||
322 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) | ||
323 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) | ||
324 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) | ||
325 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) | ||
326 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) | ||
327 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) | ||
328 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) | ||
329 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) | ||
330 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) | ||
331 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) | ||
332 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) | ||
333 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) | ||
334 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) | ||
335 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) | ||
336 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) | ||
337 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) | ||
338 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) | ||
339 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) | ||
340 | |||
341 | |||
342 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
343 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
344 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
345 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
346 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
347 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
348 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
349 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
350 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
351 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
352 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
353 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
354 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
355 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) | ||
356 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) | ||
357 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) | ||
358 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) | ||
359 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) | ||
360 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) | ||
361 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) | ||
362 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) | ||
363 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
364 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
365 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
366 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
367 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
368 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
369 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
370 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
371 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
372 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
373 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
374 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
375 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
376 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
377 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
378 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
379 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
380 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
381 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
382 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
383 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
384 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
385 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
386 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
387 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
388 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
389 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
390 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
391 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
392 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
393 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
394 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
395 | |||
396 | |||
397 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
398 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
399 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | ||
400 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
401 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | ||
402 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
403 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | ||
404 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
405 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | ||
406 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
407 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | ||
408 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
409 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | ||
410 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) | ||
411 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) | ||
412 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) | ||
413 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) | ||
414 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) | ||
415 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) | ||
416 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) | ||
417 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) | ||
418 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
419 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | ||
420 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
421 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | ||
422 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
423 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | ||
424 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
425 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | ||
426 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
427 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | ||
428 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
429 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | ||
430 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
431 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | ||
432 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
433 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | ||
434 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
435 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | ||
436 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
437 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | ||
438 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
439 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | ||
440 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
441 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | ||
442 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
443 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | ||
444 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
445 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | ||
446 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
447 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | ||
448 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
449 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | ||
450 | |||
451 | |||
452 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
453 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
454 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | ||
455 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
456 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | ||
457 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
458 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | ||
459 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
460 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) | ||
461 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | ||
462 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) | ||
463 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
464 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) | ||
465 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
466 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) | ||
467 | |||
468 | |||
469 | /* DMA Traffic Control Registers */ | ||
470 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | ||
471 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) | ||
472 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
473 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) | ||
474 | |||
475 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
476 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
477 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) | ||
478 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
479 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) | ||
480 | |||
481 | /* DMA Controller */ | ||
482 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | ||
483 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | ||
484 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | ||
485 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) | ||
486 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | ||
487 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) | ||
488 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | ||
489 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | ||
490 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | ||
491 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | ||
492 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | ||
493 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) | ||
494 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | ||
495 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) | ||
496 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | ||
497 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) | ||
498 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | ||
499 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) | ||
500 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | ||
501 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | ||
502 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | ||
503 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | ||
504 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | ||
505 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | ||
506 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | ||
507 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | ||
508 | |||
509 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | ||
510 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | ||
511 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | ||
512 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) | ||
513 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | ||
514 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) | ||
515 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | ||
516 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | ||
517 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | ||
518 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | ||
519 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | ||
520 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) | ||
521 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | ||
522 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) | ||
523 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | ||
524 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) | ||
525 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | ||
526 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) | ||
527 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | ||
528 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | ||
529 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | ||
530 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | ||
531 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | ||
532 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | ||
533 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | ||
534 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | ||
535 | |||
536 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | ||
537 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | ||
538 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | ||
539 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) | ||
540 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | ||
541 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) | ||
542 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | ||
543 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | ||
544 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | ||
545 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | ||
546 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | ||
547 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) | ||
548 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | ||
549 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) | ||
550 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | ||
551 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) | ||
552 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | ||
553 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) | ||
554 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | ||
555 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | ||
556 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | ||
557 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | ||
558 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | ||
559 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | ||
560 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | ||
561 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | ||
562 | |||
563 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | ||
564 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | ||
565 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | ||
566 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) | ||
567 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | ||
568 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) | ||
569 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | ||
570 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | ||
571 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | ||
572 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | ||
573 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | ||
574 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) | ||
575 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | ||
576 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) | ||
577 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | ||
578 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) | ||
579 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | ||
580 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) | ||
581 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | ||
582 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | ||
583 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | ||
584 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | ||
585 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | ||
586 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | ||
587 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | ||
588 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | ||
589 | |||
590 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | ||
591 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | ||
592 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | ||
593 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) | ||
594 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | ||
595 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) | ||
596 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | ||
597 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | ||
598 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | ||
599 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | ||
600 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | ||
601 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) | ||
602 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | ||
603 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) | ||
604 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | ||
605 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) | ||
606 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | ||
607 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) | ||
608 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | ||
609 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | ||
610 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | ||
611 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | ||
612 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | ||
613 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | ||
614 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | ||
615 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | ||
616 | |||
617 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | ||
618 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | ||
619 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | ||
620 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) | ||
621 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | ||
622 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) | ||
623 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | ||
624 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | ||
625 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | ||
626 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | ||
627 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | ||
628 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) | ||
629 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | ||
630 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) | ||
631 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | ||
632 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) | ||
633 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | ||
634 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) | ||
635 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | ||
636 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | ||
637 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | ||
638 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | ||
639 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | ||
640 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | ||
641 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | ||
642 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | ||
643 | |||
644 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | ||
645 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | ||
646 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | ||
647 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) | ||
648 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | ||
649 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) | ||
650 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | ||
651 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | ||
652 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | ||
653 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | ||
654 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | ||
655 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) | ||
656 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | ||
657 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) | ||
658 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | ||
659 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) | ||
660 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | ||
661 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) | ||
662 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | ||
663 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | ||
664 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | ||
665 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | ||
666 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | ||
667 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | ||
668 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | ||
669 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | ||
670 | |||
671 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | ||
672 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | ||
673 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | ||
674 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) | ||
675 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | ||
676 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) | ||
677 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | ||
678 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | ||
679 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | ||
680 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | ||
681 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | ||
682 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) | ||
683 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | ||
684 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) | ||
685 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | ||
686 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) | ||
687 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | ||
688 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) | ||
689 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | ||
690 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | ||
691 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | ||
692 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | ||
693 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | ||
694 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | ||
695 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | ||
696 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | ||
697 | |||
698 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | ||
699 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | ||
700 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | ||
701 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) | ||
702 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) | ||
703 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) | ||
704 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | ||
705 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | ||
706 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | ||
707 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | ||
708 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | ||
709 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) | ||
710 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | ||
711 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) | ||
712 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) | ||
713 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) | ||
714 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) | ||
715 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) | ||
716 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | ||
717 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | ||
718 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | ||
719 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | ||
720 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | ||
721 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | ||
722 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | ||
723 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | ||
724 | |||
725 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | ||
726 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | ||
727 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | ||
728 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) | ||
729 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) | ||
730 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) | ||
731 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | ||
732 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | ||
733 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | ||
734 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | ||
735 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | ||
736 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) | ||
737 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | ||
738 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) | ||
739 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) | ||
740 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) | ||
741 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) | ||
742 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) | ||
743 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | ||
744 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | ||
745 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | ||
746 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | ||
747 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | ||
748 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | ||
749 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | ||
750 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | ||
751 | |||
752 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | ||
753 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | ||
754 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | ||
755 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) | ||
756 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) | ||
757 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) | ||
758 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | ||
759 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | ||
760 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | ||
761 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | ||
762 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | ||
763 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) | ||
764 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | ||
765 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) | ||
766 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) | ||
767 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) | ||
768 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) | ||
769 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) | ||
770 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | ||
771 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | ||
772 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | ||
773 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | ||
774 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | ||
775 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | ||
776 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | ||
777 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | ||
778 | |||
779 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | ||
780 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | ||
781 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | ||
782 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) | ||
783 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) | ||
784 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) | ||
785 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | ||
786 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | ||
787 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | ||
788 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | ||
789 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | ||
790 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) | ||
791 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | ||
792 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) | ||
793 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) | ||
794 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) | ||
795 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) | ||
796 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) | ||
797 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | ||
798 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | ||
799 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | ||
800 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | ||
801 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | ||
802 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | ||
803 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | ||
804 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | ||
805 | |||
806 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | ||
807 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) | ||
808 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | ||
809 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) | ||
810 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | ||
811 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) | ||
812 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | ||
813 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) | ||
814 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | ||
815 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) | ||
816 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | ||
817 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) | ||
818 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | ||
819 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) | ||
820 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | ||
821 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) | ||
822 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | ||
823 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) | ||
824 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | ||
825 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) | ||
826 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | ||
827 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) | ||
828 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | ||
829 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) | ||
830 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | ||
831 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) | ||
832 | |||
833 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | ||
834 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) | ||
835 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | ||
836 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) | ||
837 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | ||
838 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) | ||
839 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | ||
840 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) | ||
841 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | ||
842 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) | ||
843 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | ||
844 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) | ||
845 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | ||
846 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) | ||
847 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | ||
848 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) | ||
849 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | ||
850 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) | ||
851 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | ||
852 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) | ||
853 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | ||
854 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) | ||
855 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | ||
856 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) | ||
857 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | ||
858 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) | ||
859 | |||
860 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | ||
861 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) | ||
862 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | ||
863 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) | ||
864 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | ||
865 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) | ||
866 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | ||
867 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | ||
868 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | ||
869 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | ||
870 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | ||
871 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) | ||
872 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | ||
873 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) | ||
874 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | ||
875 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) | ||
876 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | ||
877 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) | ||
878 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | ||
879 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) | ||
880 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | ||
881 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) | ||
882 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | ||
883 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) | ||
884 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | ||
885 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) | ||
886 | |||
887 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | ||
888 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) | ||
889 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | ||
890 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) | ||
891 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | ||
892 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) | ||
893 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | ||
894 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | ||
895 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | ||
896 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | ||
897 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | ||
898 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) | ||
899 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | ||
900 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) | ||
901 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | ||
902 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) | ||
903 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | ||
904 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) | ||
905 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | ||
906 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) | ||
907 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | ||
908 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) | ||
909 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | ||
910 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) | ||
911 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | ||
912 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) | ||
913 | |||
914 | |||
915 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
916 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | ||
917 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | ||
918 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | ||
919 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | ||
920 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | ||
921 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | ||
922 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | ||
923 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | ||
924 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | ||
925 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | ||
926 | |||
927 | |||
928 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
929 | |||
930 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
931 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) | ||
932 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) | ||
933 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) | ||
934 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) | ||
935 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) | ||
936 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) | ||
937 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) | ||
938 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) | ||
939 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) | ||
940 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) | ||
941 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) | ||
942 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) | ||
943 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) | ||
944 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) | ||
945 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) | ||
946 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) | ||
947 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) | ||
948 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) | ||
949 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) | ||
950 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) | ||
951 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) | ||
952 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) | ||
953 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) | ||
954 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) | ||
955 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) | ||
956 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) | ||
957 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) | ||
958 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) | ||
959 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) | ||
960 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) | ||
961 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) | ||
962 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) | ||
963 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) | ||
964 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) | ||
965 | |||
966 | |||
967 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
968 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) | ||
969 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) | ||
970 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) | ||
971 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) | ||
972 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) | ||
973 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) | ||
974 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) | ||
975 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) | ||
976 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) | ||
977 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) | ||
978 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) | ||
979 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) | ||
980 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) | ||
981 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) | ||
982 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) | ||
983 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) | ||
984 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) | ||
985 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) | ||
986 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) | ||
987 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) | ||
988 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) | ||
989 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) | ||
990 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) | ||
991 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) | ||
992 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) | ||
993 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) | ||
994 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) | ||
995 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) | ||
996 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) | ||
997 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) | ||
998 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) | ||
999 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) | ||
1000 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) | ||
1001 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) | ||
1002 | |||
1003 | |||
1004 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
1005 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | ||
1006 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | ||
1007 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | ||
1008 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | ||
1009 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | ||
1010 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | ||
1011 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) | ||
1012 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) | ||
1013 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | ||
1014 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | ||
1015 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) | ||
1016 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) | ||
1017 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | ||
1018 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | ||
1019 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | ||
1020 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | ||
1021 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | ||
1022 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | ||
1023 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) | ||
1024 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) | ||
1025 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | ||
1026 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | ||
1027 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | ||
1028 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | ||
1029 | |||
1030 | /* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ | ||
1031 | |||
1032 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
1033 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) | ||
1034 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) | ||
1035 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) | ||
1036 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) | ||
1037 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) | ||
1038 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) | ||
1039 | #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) | ||
1040 | #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) | ||
1041 | |||
1042 | |||
1043 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
1044 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) | ||
1045 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) | ||
1046 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) | ||
1047 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) | ||
1048 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) | ||
1049 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) | ||
1050 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) | ||
1051 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) | ||
1052 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) | ||
1053 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) | ||
1054 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) | ||
1055 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) | ||
1056 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) | ||
1057 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) | ||
1058 | |||
1059 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) | ||
1060 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) | ||
1061 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) | ||
1062 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) | ||
1063 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) | ||
1064 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) | ||
1065 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) | ||
1066 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) | ||
1067 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) | ||
1068 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) | ||
1069 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) | ||
1070 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) | ||
1071 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | ||
1072 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) | ||
1073 | |||
1074 | /* ==== end from cdefBF534.h ==== */ | ||
1075 | |||
1076 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
1077 | |||
1078 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) | ||
1079 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) | ||
1080 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) | ||
1081 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) | ||
1082 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) | ||
1083 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) | ||
1084 | |||
1085 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) | ||
1086 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) | ||
1087 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) | ||
1088 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) | ||
1089 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) | ||
1090 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) | ||
1091 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) | ||
1092 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) | ||
1093 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) | ||
1094 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) | ||
1095 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) | ||
1096 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) | ||
1097 | #define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) | ||
1098 | #define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) | ||
1099 | #define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) | ||
1100 | #define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) | ||
1101 | #define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) | ||
1102 | #define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) | ||
1103 | #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) | ||
1104 | #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) | ||
1105 | #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) | ||
1106 | #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) | ||
1107 | #define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) | ||
1108 | #define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) | ||
1109 | |||
1110 | /* HOST Port Registers */ | ||
1111 | |||
1112 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) | ||
1113 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) | ||
1114 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) | ||
1115 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) | ||
1116 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) | ||
1117 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) | ||
1118 | |||
1119 | /* Counter Registers */ | ||
1120 | |||
1121 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) | ||
1122 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) | ||
1123 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) | ||
1124 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) | ||
1125 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) | ||
1126 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) | ||
1127 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) | ||
1128 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) | ||
1129 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) | ||
1130 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) | ||
1131 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) | ||
1132 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) | ||
1133 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) | ||
1134 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) | ||
1135 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) | ||
1136 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) | ||
1137 | |||
1138 | /* OTP/FUSE Registers */ | ||
1139 | |||
1140 | #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) | ||
1141 | #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) | ||
1142 | #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) | ||
1143 | #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) | ||
1144 | #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) | ||
1145 | #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) | ||
1146 | #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) | ||
1147 | #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) | ||
1148 | |||
1149 | /* Security Registers */ | ||
1150 | |||
1151 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) | ||
1152 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) | ||
1153 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) | ||
1154 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) | ||
1155 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) | ||
1156 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) | ||
1157 | |||
1158 | /* OTP Read/Write Data Buffer Registers */ | ||
1159 | |||
1160 | #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) | ||
1161 | #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) | ||
1162 | #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) | ||
1163 | #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) | ||
1164 | #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) | ||
1165 | #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) | ||
1166 | #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) | ||
1167 | #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) | ||
1168 | |||
1169 | /* NFC Registers */ | ||
1170 | |||
1171 | #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) | ||
1172 | #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) | ||
1173 | #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) | ||
1174 | #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) | ||
1175 | #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) | ||
1176 | #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) | ||
1177 | #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) | ||
1178 | #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) | ||
1179 | #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) | ||
1180 | #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) | ||
1181 | #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) | ||
1182 | #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) | ||
1183 | #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) | ||
1184 | #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) | ||
1185 | #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) | ||
1186 | #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) | ||
1187 | #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) | ||
1188 | #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) | ||
1189 | #define bfin_read_NFC_RST() bfin_read16(NFC_RST) | ||
1190 | #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) | ||
1191 | #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) | ||
1192 | #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) | ||
1193 | #define bfin_read_NFC_READ() bfin_read16(NFC_READ) | ||
1194 | #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) | ||
1195 | #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) | ||
1196 | #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) | ||
1197 | #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) | ||
1198 | #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) | ||
1199 | #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) | ||
1200 | #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) | ||
1201 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) | ||
1202 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) | ||
1203 | |||
1204 | #endif /* _CDEF_BF52X_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h new file mode 100644 index 000000000000..0a8cdcdf0b49 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/defBF522.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF522_H | ||
32 | #define _DEF_BF522_H | ||
33 | |||
34 | /* Include all Core registers and bit definitions */ | ||
35 | #include <asm/def_LPBlackfin.h> | ||
36 | |||
37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ | ||
38 | |||
39 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
40 | #include "defBF52x_base.h" | ||
41 | |||
42 | #endif /* _DEF_BF522_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h new file mode 100644 index 000000000000..5cd7576fef76 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h | |||
@@ -0,0 +1,713 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/defBF525.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF525_H | ||
32 | #define _DEF_BF525_H | ||
33 | |||
34 | /* Include all Core registers and bit definitions */ | ||
35 | #include <asm/def_LPBlackfin.h> | ||
36 | |||
37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ | ||
38 | |||
39 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
40 | #include "defBF52x_base.h" | ||
41 | |||
42 | /* The following are the #defines needed by ADSP-BF525 that are not in the common header */ | ||
43 | |||
44 | /* USB Control Registers */ | ||
45 | |||
46 | #define USB_FADDR 0xffc03800 /* Function address register */ | ||
47 | #define USB_POWER 0xffc03804 /* Power management register */ | ||
48 | #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | ||
49 | #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ | ||
50 | #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ | ||
51 | #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ | ||
52 | #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ | ||
53 | #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ | ||
54 | #define USB_FRAME 0xffc03820 /* USB frame number */ | ||
55 | #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ | ||
56 | #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ | ||
57 | #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | ||
58 | #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ | ||
59 | |||
60 | /* USB Packet Control Registers */ | ||
61 | |||
62 | #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ | ||
63 | #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
64 | #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
65 | #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ | ||
66 | #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ | ||
67 | #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
68 | #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
69 | #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | ||
70 | #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
71 | #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
72 | #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | ||
73 | #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | ||
74 | #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
75 | |||
76 | /* USB Endpoint FIFO Registers */ | ||
77 | |||
78 | #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ | ||
79 | #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ | ||
80 | #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ | ||
81 | #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ | ||
82 | #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ | ||
83 | #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ | ||
84 | #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ | ||
85 | #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ | ||
86 | |||
87 | /* USB OTG Control Registers */ | ||
88 | |||
89 | #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ | ||
90 | #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ | ||
91 | #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ | ||
92 | |||
93 | /* USB Phy Control Registers */ | ||
94 | |||
95 | #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ | ||
96 | #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ | ||
97 | #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ | ||
98 | #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ | ||
99 | #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ | ||
100 | |||
101 | /* (APHY_CNTRL is for ADI usage only) */ | ||
102 | |||
103 | #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ | ||
104 | |||
105 | /* (APHY_CALIB is for ADI usage only) */ | ||
106 | |||
107 | #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ | ||
108 | |||
109 | #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | ||
110 | |||
111 | /* (PHY_TEST is for ADI usage only) */ | ||
112 | |||
113 | #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ | ||
114 | |||
115 | #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ | ||
116 | #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | ||
117 | |||
118 | /* USB Endpoint 0 Control Registers */ | ||
119 | |||
120 | #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ | ||
121 | #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ | ||
122 | #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ | ||
123 | #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ | ||
124 | #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ | ||
125 | #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | ||
126 | #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ | ||
127 | #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | ||
128 | #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | ||
129 | #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | ||
130 | |||
131 | /* USB Endpoint 1 Control Registers */ | ||
132 | |||
133 | #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ | ||
134 | #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ | ||
135 | #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ | ||
136 | #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ | ||
137 | #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ | ||
138 | #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | ||
139 | #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ | ||
140 | #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | ||
141 | #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | ||
142 | #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | ||
143 | |||
144 | /* USB Endpoint 2 Control Registers */ | ||
145 | |||
146 | #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ | ||
147 | #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ | ||
148 | #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ | ||
149 | #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ | ||
150 | #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ | ||
151 | #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | ||
152 | #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ | ||
153 | #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | ||
154 | #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | ||
155 | #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | ||
156 | |||
157 | /* USB Endpoint 3 Control Registers */ | ||
158 | |||
159 | #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ | ||
160 | #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ | ||
161 | #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ | ||
162 | #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ | ||
163 | #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ | ||
164 | #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | ||
165 | #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ | ||
166 | #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | ||
167 | #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | ||
168 | #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | ||
169 | |||
170 | /* USB Endpoint 4 Control Registers */ | ||
171 | |||
172 | #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ | ||
173 | #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ | ||
174 | #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ | ||
175 | #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ | ||
176 | #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ | ||
177 | #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | ||
178 | #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ | ||
179 | #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | ||
180 | #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | ||
181 | #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | ||
182 | |||
183 | /* USB Endpoint 5 Control Registers */ | ||
184 | |||
185 | #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ | ||
186 | #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ | ||
187 | #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ | ||
188 | #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ | ||
189 | #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ | ||
190 | #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | ||
191 | #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ | ||
192 | #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | ||
193 | #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | ||
194 | #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ | ||
195 | |||
196 | /* USB Endpoint 6 Control Registers */ | ||
197 | |||
198 | #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ | ||
199 | #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ | ||
200 | #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ | ||
201 | #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ | ||
202 | #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ | ||
203 | #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | ||
204 | #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ | ||
205 | #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | ||
206 | #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | ||
207 | #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | ||
208 | |||
209 | /* USB Endpoint 7 Control Registers */ | ||
210 | |||
211 | #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ | ||
212 | #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ | ||
213 | #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ | ||
214 | #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ | ||
215 | #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ | ||
216 | #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | ||
217 | #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ | ||
218 | #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | ||
219 | #define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | ||
220 | #define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | ||
221 | |||
222 | #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ | ||
223 | |||
224 | /* USB Channel 0 Config Registers */ | ||
225 | |||
226 | #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ | ||
227 | #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | ||
228 | #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | ||
229 | #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
230 | #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
231 | |||
232 | /* USB Channel 1 Config Registers */ | ||
233 | |||
234 | #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ | ||
235 | #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | ||
236 | #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | ||
237 | #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
238 | #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
239 | |||
240 | /* USB Channel 2 Config Registers */ | ||
241 | |||
242 | #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ | ||
243 | #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | ||
244 | #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | ||
245 | #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
246 | #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
247 | |||
248 | /* USB Channel 3 Config Registers */ | ||
249 | |||
250 | #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ | ||
251 | #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | ||
252 | #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | ||
253 | #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
254 | #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
255 | |||
256 | /* USB Channel 4 Config Registers */ | ||
257 | |||
258 | #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ | ||
259 | #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | ||
260 | #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | ||
261 | #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
262 | #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
263 | |||
264 | /* USB Channel 5 Config Registers */ | ||
265 | |||
266 | #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ | ||
267 | #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | ||
268 | #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | ||
269 | #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
270 | #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
271 | |||
272 | /* USB Channel 6 Config Registers */ | ||
273 | |||
274 | #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ | ||
275 | #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | ||
276 | #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | ||
277 | #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
278 | #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
279 | |||
280 | /* USB Channel 7 Config Registers */ | ||
281 | |||
282 | #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ | ||
283 | #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | ||
284 | #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | ||
285 | #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
286 | #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
287 | |||
288 | /* Bit masks for USB_FADDR */ | ||
289 | |||
290 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | ||
291 | |||
292 | /* Bit masks for USB_POWER */ | ||
293 | |||
294 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | ||
295 | #define nENABLE_SUSPENDM 0x0 | ||
296 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | ||
297 | #define nSUSPEND_MODE 0x0 | ||
298 | #define RESUME_MODE 0x4 /* DMA Mode */ | ||
299 | #define nRESUME_MODE 0x0 | ||
300 | #define RESET 0x8 /* Reset indicator */ | ||
301 | #define nRESET 0x0 | ||
302 | #define HS_MODE 0x10 /* High Speed mode indicator */ | ||
303 | #define nHS_MODE 0x0 | ||
304 | #define HS_ENABLE 0x20 /* high Speed Enable */ | ||
305 | #define nHS_ENABLE 0x0 | ||
306 | #define SOFT_CONN 0x40 /* Soft connect */ | ||
307 | #define nSOFT_CONN 0x0 | ||
308 | #define ISO_UPDATE 0x80 /* Isochronous update */ | ||
309 | #define nISO_UPDATE 0x0 | ||
310 | |||
311 | /* Bit masks for USB_INTRTX */ | ||
312 | |||
313 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | ||
314 | #define nEP0_TX 0x0 | ||
315 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | ||
316 | #define nEP1_TX 0x0 | ||
317 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | ||
318 | #define nEP2_TX 0x0 | ||
319 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | ||
320 | #define nEP3_TX 0x0 | ||
321 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | ||
322 | #define nEP4_TX 0x0 | ||
323 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | ||
324 | #define nEP5_TX 0x0 | ||
325 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | ||
326 | #define nEP6_TX 0x0 | ||
327 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | ||
328 | #define nEP7_TX 0x0 | ||
329 | |||
330 | /* Bit masks for USB_INTRRX */ | ||
331 | |||
332 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | ||
333 | #define nEP1_RX 0x0 | ||
334 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | ||
335 | #define nEP2_RX 0x0 | ||
336 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | ||
337 | #define nEP3_RX 0x0 | ||
338 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | ||
339 | #define nEP4_RX 0x0 | ||
340 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | ||
341 | #define nEP5_RX 0x0 | ||
342 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | ||
343 | #define nEP6_RX 0x0 | ||
344 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | ||
345 | #define nEP7_RX 0x0 | ||
346 | |||
347 | /* Bit masks for USB_INTRTXE */ | ||
348 | |||
349 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | ||
350 | #define nEP0_TX_E 0x0 | ||
351 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | ||
352 | #define nEP1_TX_E 0x0 | ||
353 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | ||
354 | #define nEP2_TX_E 0x0 | ||
355 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | ||
356 | #define nEP3_TX_E 0x0 | ||
357 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | ||
358 | #define nEP4_TX_E 0x0 | ||
359 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | ||
360 | #define nEP5_TX_E 0x0 | ||
361 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | ||
362 | #define nEP6_TX_E 0x0 | ||
363 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | ||
364 | #define nEP7_TX_E 0x0 | ||
365 | |||
366 | /* Bit masks for USB_INTRRXE */ | ||
367 | |||
368 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | ||
369 | #define nEP1_RX_E 0x0 | ||
370 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | ||
371 | #define nEP2_RX_E 0x0 | ||
372 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | ||
373 | #define nEP3_RX_E 0x0 | ||
374 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | ||
375 | #define nEP4_RX_E 0x0 | ||
376 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | ||
377 | #define nEP5_RX_E 0x0 | ||
378 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | ||
379 | #define nEP6_RX_E 0x0 | ||
380 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | ||
381 | #define nEP7_RX_E 0x0 | ||
382 | |||
383 | /* Bit masks for USB_INTRUSB */ | ||
384 | |||
385 | #define SUSPEND_B 0x1 /* Suspend indicator */ | ||
386 | #define nSUSPEND_B 0x0 | ||
387 | #define RESUME_B 0x2 /* Resume indicator */ | ||
388 | #define nRESUME_B 0x0 | ||
389 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | ||
390 | #define nRESET_OR_BABLE_B 0x0 | ||
391 | #define SOF_B 0x8 /* Start of frame */ | ||
392 | #define nSOF_B 0x0 | ||
393 | #define CONN_B 0x10 /* Connection indicator */ | ||
394 | #define nCONN_B 0x0 | ||
395 | #define DISCON_B 0x20 /* Disconnect indicator */ | ||
396 | #define nDISCON_B 0x0 | ||
397 | #define SESSION_REQ_B 0x40 /* Session Request */ | ||
398 | #define nSESSION_REQ_B 0x0 | ||
399 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | ||
400 | #define nVBUS_ERROR_B 0x0 | ||
401 | |||
402 | /* Bit masks for USB_INTRUSBE */ | ||
403 | |||
404 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | ||
405 | #define nSUSPEND_BE 0x0 | ||
406 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | ||
407 | #define nRESUME_BE 0x0 | ||
408 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | ||
409 | #define nRESET_OR_BABLE_BE 0x0 | ||
410 | #define SOF_BE 0x8 /* Start of frame int enable */ | ||
411 | #define nSOF_BE 0x0 | ||
412 | #define CONN_BE 0x10 /* Connection indicator int enable */ | ||
413 | #define nCONN_BE 0x0 | ||
414 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | ||
415 | #define nDISCON_BE 0x0 | ||
416 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | ||
417 | #define nSESSION_REQ_BE 0x0 | ||
418 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | ||
419 | #define nVBUS_ERROR_BE 0x0 | ||
420 | |||
421 | /* Bit masks for USB_FRAME */ | ||
422 | |||
423 | #define FRAME_NUMBER 0x7ff /* Frame number */ | ||
424 | |||
425 | /* Bit masks for USB_INDEX */ | ||
426 | |||
427 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | ||
428 | |||
429 | /* Bit masks for USB_GLOBAL_CTL */ | ||
430 | |||
431 | #define GLOBAL_ENA 0x1 /* enables USB module */ | ||
432 | #define nGLOBAL_ENA 0x0 | ||
433 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | ||
434 | #define nEP1_TX_ENA 0x0 | ||
435 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | ||
436 | #define nEP2_TX_ENA 0x0 | ||
437 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | ||
438 | #define nEP3_TX_ENA 0x0 | ||
439 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | ||
440 | #define nEP4_TX_ENA 0x0 | ||
441 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | ||
442 | #define nEP5_TX_ENA 0x0 | ||
443 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | ||
444 | #define nEP6_TX_ENA 0x0 | ||
445 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | ||
446 | #define nEP7_TX_ENA 0x0 | ||
447 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | ||
448 | #define nEP1_RX_ENA 0x0 | ||
449 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | ||
450 | #define nEP2_RX_ENA 0x0 | ||
451 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | ||
452 | #define nEP3_RX_ENA 0x0 | ||
453 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | ||
454 | #define nEP4_RX_ENA 0x0 | ||
455 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | ||
456 | #define nEP5_RX_ENA 0x0 | ||
457 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | ||
458 | #define nEP6_RX_ENA 0x0 | ||
459 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | ||
460 | #define nEP7_RX_ENA 0x0 | ||
461 | |||
462 | /* Bit masks for USB_OTG_DEV_CTL */ | ||
463 | |||
464 | #define SESSION 0x1 /* session indicator */ | ||
465 | #define nSESSION 0x0 | ||
466 | #define HOST_REQ 0x2 /* Host negotiation request */ | ||
467 | #define nHOST_REQ 0x0 | ||
468 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | ||
469 | #define nHOST_MODE 0x0 | ||
470 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | ||
471 | #define nVBUS0 0x0 | ||
472 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | ||
473 | #define nVBUS1 0x0 | ||
474 | #define LSDEV 0x20 /* Low-speed indicator */ | ||
475 | #define nLSDEV 0x0 | ||
476 | #define FSDEV 0x40 /* Full or High-speed indicator */ | ||
477 | #define nFSDEV 0x0 | ||
478 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | ||
479 | #define nB_DEVICE 0x0 | ||
480 | |||
481 | /* Bit masks for USB_OTG_VBUS_IRQ */ | ||
482 | |||
483 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | ||
484 | #define nDRIVE_VBUS_ON 0x0 | ||
485 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | ||
486 | #define nDRIVE_VBUS_OFF 0x0 | ||
487 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | ||
488 | #define nCHRG_VBUS_START 0x0 | ||
489 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | ||
490 | #define nCHRG_VBUS_END 0x0 | ||
491 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | ||
492 | #define nDISCHRG_VBUS_START 0x0 | ||
493 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | ||
494 | #define nDISCHRG_VBUS_END 0x0 | ||
495 | |||
496 | /* Bit masks for USB_OTG_VBUS_MASK */ | ||
497 | |||
498 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | ||
499 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
500 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | ||
501 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
502 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | ||
503 | #define nCHRG_VBUS_START_ENA 0x0 | ||
504 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | ||
505 | #define nCHRG_VBUS_END_ENA 0x0 | ||
506 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | ||
507 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
508 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | ||
509 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
510 | |||
511 | /* Bit masks for USB_CSR0 */ | ||
512 | |||
513 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | ||
514 | #define nRXPKTRDY 0x0 | ||
515 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | ||
516 | #define nTXPKTRDY 0x0 | ||
517 | #define STALL_SENT 0x4 /* STALL handshake sent */ | ||
518 | #define nSTALL_SENT 0x0 | ||
519 | #define DATAEND 0x8 /* Data end indicator */ | ||
520 | #define nDATAEND 0x0 | ||
521 | #define SETUPEND 0x10 /* Setup end */ | ||
522 | #define nSETUPEND 0x0 | ||
523 | #define SENDSTALL 0x20 /* Send STALL handshake */ | ||
524 | #define nSENDSTALL 0x0 | ||
525 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | ||
526 | #define nSERVICED_RXPKTRDY 0x0 | ||
527 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | ||
528 | #define nSERVICED_SETUPEND 0x0 | ||
529 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | ||
530 | #define nFLUSHFIFO 0x0 | ||
531 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | ||
532 | #define nSTALL_RECEIVED_H 0x0 | ||
533 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | ||
534 | #define nSETUPPKT_H 0x0 | ||
535 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | ||
536 | #define nERROR_H 0x0 | ||
537 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | ||
538 | #define nREQPKT_H 0x0 | ||
539 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | ||
540 | #define nSTATUSPKT_H 0x0 | ||
541 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | ||
542 | #define nNAK_TIMEOUT_H 0x0 | ||
543 | |||
544 | /* Bit masks for USB_COUNT0 */ | ||
545 | |||
546 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | ||
547 | |||
548 | /* Bit masks for USB_NAKLIMIT0 */ | ||
549 | |||
550 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | ||
551 | |||
552 | /* Bit masks for USB_TX_MAX_PACKET */ | ||
553 | |||
554 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | ||
555 | |||
556 | /* Bit masks for USB_RX_MAX_PACKET */ | ||
557 | |||
558 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | ||
559 | |||
560 | /* Bit masks for USB_TXCSR */ | ||
561 | |||
562 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | ||
563 | #define nTXPKTRDY_T 0x0 | ||
564 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | ||
565 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
566 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | ||
567 | #define nUNDERRUN_T 0x0 | ||
568 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | ||
569 | #define nFLUSHFIFO_T 0x0 | ||
570 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | ||
571 | #define nSTALL_SEND_T 0x0 | ||
572 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | ||
573 | #define nSTALL_SENT_T 0x0 | ||
574 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | ||
575 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
576 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | ||
577 | #define nINCOMPTX_T 0x0 | ||
578 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | ||
579 | #define nDMAREQMODE_T 0x0 | ||
580 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | ||
581 | #define nFORCE_DATATOGGLE_T 0x0 | ||
582 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | ||
583 | #define nDMAREQ_ENA_T 0x0 | ||
584 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | ||
585 | #define nISO_T 0x0 | ||
586 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | ||
587 | #define nAUTOSET_T 0x0 | ||
588 | #define ERROR_TH 0x4 /* error condition host mode */ | ||
589 | #define nERROR_TH 0x0 | ||
590 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | ||
591 | #define nSTALL_RECEIVED_TH 0x0 | ||
592 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | ||
593 | #define nNAK_TIMEOUT_TH 0x0 | ||
594 | |||
595 | /* Bit masks for USB_TXCOUNT */ | ||
596 | |||
597 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
598 | |||
599 | /* Bit masks for USB_RXCSR */ | ||
600 | |||
601 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | ||
602 | #define nRXPKTRDY_R 0x0 | ||
603 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | ||
604 | #define nFIFO_FULL_R 0x0 | ||
605 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | ||
606 | #define nOVERRUN_R 0x0 | ||
607 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | ||
608 | #define nDATAERROR_R 0x0 | ||
609 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | ||
610 | #define nFLUSHFIFO_R 0x0 | ||
611 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | ||
612 | #define nSTALL_SEND_R 0x0 | ||
613 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | ||
614 | #define nSTALL_SENT_R 0x0 | ||
615 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | ||
616 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
617 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | ||
618 | #define nINCOMPRX_R 0x0 | ||
619 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | ||
620 | #define nDMAREQMODE_R 0x0 | ||
621 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | ||
622 | #define nDISNYET_R 0x0 | ||
623 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | ||
624 | #define nDMAREQ_ENA_R 0x0 | ||
625 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | ||
626 | #define nISO_R 0x0 | ||
627 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | ||
628 | #define nAUTOCLEAR_R 0x0 | ||
629 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | ||
630 | #define nERROR_RH 0x0 | ||
631 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | ||
632 | #define nREQPKT_RH 0x0 | ||
633 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | ||
634 | #define nSTALL_RECEIVED_RH 0x0 | ||
635 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | ||
636 | #define nINCOMPRX_RH 0x0 | ||
637 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | ||
638 | #define nDMAREQMODE_RH 0x0 | ||
639 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | ||
640 | #define nAUTOREQ_RH 0x0 | ||
641 | |||
642 | /* Bit masks for USB_RXCOUNT */ | ||
643 | |||
644 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | ||
645 | |||
646 | /* Bit masks for USB_TXTYPE */ | ||
647 | |||
648 | #define TARGET_EP_NO_T 0xf /* EP number */ | ||
649 | #define PROTOCOL_T 0xc /* transfer type */ | ||
650 | |||
651 | /* Bit masks for USB_TXINTERVAL */ | ||
652 | |||
653 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | ||
654 | |||
655 | /* Bit masks for USB_RXTYPE */ | ||
656 | |||
657 | #define TARGET_EP_NO_R 0xf /* EP number */ | ||
658 | #define PROTOCOL_R 0xc /* transfer type */ | ||
659 | |||
660 | /* Bit masks for USB_RXINTERVAL */ | ||
661 | |||
662 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | ||
663 | |||
664 | /* Bit masks for USB_DMA_INTERRUPT */ | ||
665 | |||
666 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | ||
667 | #define nDMA0_INT 0x0 | ||
668 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | ||
669 | #define nDMA1_INT 0x0 | ||
670 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | ||
671 | #define nDMA2_INT 0x0 | ||
672 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | ||
673 | #define nDMA3_INT 0x0 | ||
674 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | ||
675 | #define nDMA4_INT 0x0 | ||
676 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | ||
677 | #define nDMA5_INT 0x0 | ||
678 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | ||
679 | #define nDMA6_INT 0x0 | ||
680 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | ||
681 | #define nDMA7_INT 0x0 | ||
682 | |||
683 | /* Bit masks for USB_DMAxCONTROL */ | ||
684 | |||
685 | #define DMA_ENA 0x1 /* DMA enable */ | ||
686 | #define nDMA_ENA 0x0 | ||
687 | #define DIRECTION 0x2 /* direction of DMA transfer */ | ||
688 | #define nDIRECTION 0x0 | ||
689 | #define MODE 0x4 /* DMA Bus error */ | ||
690 | #define nMODE 0x0 | ||
691 | #define INT_ENA 0x8 /* Interrupt enable */ | ||
692 | #define nINT_ENA 0x0 | ||
693 | #define EPNUM 0xf0 /* EP number */ | ||
694 | #define BUSERROR 0x100 /* DMA Bus error */ | ||
695 | #define nBUSERROR 0x0 | ||
696 | |||
697 | /* Bit masks for USB_DMAxADDRHIGH */ | ||
698 | |||
699 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | ||
700 | |||
701 | /* Bit masks for USB_DMAxADDRLOW */ | ||
702 | |||
703 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | ||
704 | |||
705 | /* Bit masks for USB_DMAxCOUNTHIGH */ | ||
706 | |||
707 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | ||
708 | |||
709 | /* Bit masks for USB_DMAxCOUNTLOW */ | ||
710 | |||
711 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | ||
712 | |||
713 | #endif /* _DEF_BF525_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h new file mode 100644 index 000000000000..f040f364afa3 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h | |||
@@ -0,0 +1,1090 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/defBF527.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF527_H | ||
32 | #define _DEF_BF527_H | ||
33 | |||
34 | /* Include all Core registers and bit definitions */ | ||
35 | #include <asm/def_LPBlackfin.h> | ||
36 | |||
37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ | ||
38 | |||
39 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
40 | #include "defBF52x_base.h" | ||
41 | |||
42 | /* The following are the #defines needed by ADSP-BF527 that are not in the common header */ | ||
43 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
44 | |||
45 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | ||
46 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | ||
47 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | ||
48 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | ||
49 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | ||
50 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | ||
51 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | ||
52 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | ||
53 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | ||
54 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | ||
55 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | ||
56 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | ||
57 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | ||
58 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | ||
59 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | ||
60 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | ||
61 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | ||
62 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | ||
63 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | ||
64 | |||
65 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | ||
66 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | ||
67 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | ||
68 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | ||
69 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | ||
70 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | ||
71 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | ||
72 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | ||
73 | |||
74 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | ||
75 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | ||
76 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | ||
77 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | ||
78 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | ||
79 | |||
80 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | ||
81 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | ||
82 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | ||
83 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | ||
84 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | ||
85 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | ||
86 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | ||
87 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | ||
88 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | ||
89 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | ||
90 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | ||
91 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | ||
92 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | ||
93 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | ||
94 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | ||
95 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | ||
96 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | ||
97 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
98 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | ||
99 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
100 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
101 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
102 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
103 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
104 | |||
105 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | ||
106 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | ||
107 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | ||
108 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | ||
109 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | ||
110 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | ||
111 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | ||
112 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | ||
113 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | ||
114 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | ||
115 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | ||
116 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | ||
117 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | ||
118 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | ||
119 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | ||
120 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | ||
121 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | ||
122 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
123 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
124 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
125 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
126 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
127 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | ||
128 | |||
129 | /* Listing for IEEE-Supported Count Registers */ | ||
130 | |||
131 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | ||
132 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | ||
133 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | ||
134 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | ||
135 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | ||
136 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | ||
137 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | ||
138 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | ||
139 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | ||
140 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | ||
141 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | ||
142 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | ||
143 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | ||
144 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | ||
145 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | ||
146 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | ||
147 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | ||
148 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
149 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | ||
150 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
151 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
152 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
153 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
154 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
155 | |||
156 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | ||
157 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | ||
158 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | ||
159 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | ||
160 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | ||
161 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | ||
162 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | ||
163 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | ||
164 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | ||
165 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | ||
166 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | ||
167 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | ||
168 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | ||
169 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | ||
170 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | ||
171 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | ||
172 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | ||
173 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
174 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
175 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
176 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
177 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
178 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | ||
179 | |||
180 | /*********************************************************************************** | ||
181 | ** System MMR Register Bits And Macros | ||
182 | ** | ||
183 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
184 | ** Use these macros carefully, as any that do left shifts for field | ||
185 | ** depositing will result in the lower order bits being destroyed. Any | ||
186 | ** macro that shifts left to properly position the bit-field should be | ||
187 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
188 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
189 | ** the macro is used. | ||
190 | *************************************************************************************/ | ||
191 | |||
192 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | ||
193 | |||
194 | /* EMAC_OPMODE Masks */ | ||
195 | |||
196 | #define RE 0x00000001 /* Receiver Enable */ | ||
197 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | ||
198 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | ||
199 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | ||
200 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | ||
201 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | ||
202 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | ||
203 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | ||
204 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | ||
205 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | ||
206 | #define RAF 0x00001000 /* Receive-All Mode */ | ||
207 | #define TE 0x00010000 /* Transmitter Enable */ | ||
208 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | ||
209 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | ||
210 | #define DC 0x00080000 /* Deferral Check */ | ||
211 | #define BOLMT 0x00300000 /* Back-Off Limit */ | ||
212 | #define BOLMT_10 0x00000000 /* 10-bit range */ | ||
213 | #define BOLMT_8 0x00100000 /* 8-bit range */ | ||
214 | #define BOLMT_4 0x00200000 /* 4-bit range */ | ||
215 | #define BOLMT_1 0x00300000 /* 1-bit range */ | ||
216 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | ||
217 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | ||
218 | #define RMII 0x01000000 /* RMII/MII* Mode */ | ||
219 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | ||
220 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | ||
221 | #define LB 0x08000000 /* Internal Loopback Enable */ | ||
222 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | ||
223 | |||
224 | /* EMAC_STAADD Masks */ | ||
225 | |||
226 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | ||
227 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | ||
228 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | ||
229 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | ||
230 | #define REGAD 0x000007C0 /* STA Register Address */ | ||
231 | #define PHYAD 0x0000F800 /* PHY Device Address */ | ||
232 | |||
233 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | ||
234 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | ||
235 | |||
236 | /* EMAC_STADAT Mask */ | ||
237 | |||
238 | #define STADATA 0x0000FFFF /* Station Management Data */ | ||
239 | |||
240 | /* EMAC_FLC Masks */ | ||
241 | |||
242 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | ||
243 | #define FLCE 0x00000002 /* Flow Control Enable */ | ||
244 | #define PCF 0x00000004 /* Pass Control Frames */ | ||
245 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | ||
246 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | ||
247 | |||
248 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | ||
249 | |||
250 | /* EMAC_WKUP_CTL Masks */ | ||
251 | |||
252 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | ||
253 | #define MPKE 0x00000002 /* Magic Packet Enable */ | ||
254 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | ||
255 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | ||
256 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | ||
257 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | ||
258 | |||
259 | /* EMAC_WKUP_FFCMD Masks */ | ||
260 | |||
261 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | ||
262 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | ||
263 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | ||
264 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | ||
265 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | ||
266 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | ||
267 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | ||
268 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | ||
269 | |||
270 | /* EMAC_WKUP_FFOFF Masks */ | ||
271 | |||
272 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | ||
273 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | ||
274 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | ||
275 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | ||
276 | |||
277 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | ||
278 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | ||
279 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | ||
280 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | ||
281 | /* Set ALL Offsets */ | ||
282 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | ||
283 | |||
284 | /* EMAC_WKUP_FFCRC0 Masks */ | ||
285 | |||
286 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | ||
287 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | ||
288 | |||
289 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | ||
290 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | ||
291 | |||
292 | /* EMAC_WKUP_FFCRC1 Masks */ | ||
293 | |||
294 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | ||
295 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | ||
296 | |||
297 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | ||
298 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | ||
299 | |||
300 | /* EMAC_SYSCTL Masks */ | ||
301 | |||
302 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | ||
303 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | ||
304 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | ||
305 | #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ | ||
306 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | ||
307 | |||
308 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | ||
309 | |||
310 | /* EMAC_SYSTAT Masks */ | ||
311 | |||
312 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | ||
313 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | ||
314 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | ||
315 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | ||
316 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | ||
317 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | ||
318 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | ||
319 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | ||
320 | |||
321 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | ||
322 | |||
323 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | ||
324 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | ||
325 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | ||
326 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | ||
327 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | ||
328 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | ||
329 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | ||
330 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | ||
331 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | ||
332 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | ||
333 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | ||
334 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | ||
335 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | ||
336 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | ||
337 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | ||
338 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | ||
339 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | ||
340 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | ||
341 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | ||
342 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | ||
343 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | ||
344 | |||
345 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | ||
346 | |||
347 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | ||
348 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | ||
349 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | ||
350 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | ||
351 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | ||
352 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | ||
353 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | ||
354 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | ||
355 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | ||
356 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | ||
357 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | ||
358 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | ||
359 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | ||
360 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | ||
361 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | ||
362 | |||
363 | /* EMAC_MMC_CTL Masks */ | ||
364 | #define RSTC 0x00000001 /* Reset All Counters */ | ||
365 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | ||
366 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | ||
367 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | ||
368 | |||
369 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | ||
370 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | ||
371 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | ||
372 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | ||
373 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | ||
374 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | ||
375 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | ||
376 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | ||
377 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | ||
378 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | ||
379 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | ||
380 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | ||
381 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | ||
382 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | ||
383 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | ||
384 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | ||
385 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | ||
386 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | ||
387 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | ||
388 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | ||
389 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | ||
390 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | ||
391 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | ||
392 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | ||
393 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | ||
394 | |||
395 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | ||
396 | |||
397 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | ||
398 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | ||
399 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | ||
400 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | ||
401 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | ||
402 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | ||
403 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | ||
404 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | ||
405 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | ||
406 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | ||
407 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | ||
408 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | ||
409 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | ||
410 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | ||
411 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | ||
412 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | ||
413 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | ||
414 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | ||
415 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | ||
416 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | ||
417 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | ||
418 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | ||
419 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | ||
420 | |||
421 | /* USB Control Registers */ | ||
422 | |||
423 | #define USB_FADDR 0xffc03800 /* Function address register */ | ||
424 | #define USB_POWER 0xffc03804 /* Power management register */ | ||
425 | #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | ||
426 | #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ | ||
427 | #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ | ||
428 | #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ | ||
429 | #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ | ||
430 | #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ | ||
431 | #define USB_FRAME 0xffc03820 /* USB frame number */ | ||
432 | #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ | ||
433 | #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ | ||
434 | #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | ||
435 | #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ | ||
436 | |||
437 | /* USB Packet Control Registers */ | ||
438 | |||
439 | #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ | ||
440 | #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
441 | #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
442 | #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ | ||
443 | #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ | ||
444 | #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
445 | #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
446 | #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | ||
447 | #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
448 | #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
449 | #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | ||
450 | #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | ||
451 | #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
452 | |||
453 | /* USB Endpoint FIFO Registers */ | ||
454 | |||
455 | #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ | ||
456 | #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ | ||
457 | #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ | ||
458 | #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ | ||
459 | #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ | ||
460 | #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ | ||
461 | #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ | ||
462 | #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ | ||
463 | |||
464 | /* USB OTG Control Registers */ | ||
465 | |||
466 | #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ | ||
467 | #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ | ||
468 | #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ | ||
469 | |||
470 | /* USB Phy Control Registers */ | ||
471 | |||
472 | #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ | ||
473 | #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ | ||
474 | #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ | ||
475 | #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ | ||
476 | #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ | ||
477 | |||
478 | /* (APHY_CNTRL is for ADI usage only) */ | ||
479 | |||
480 | #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ | ||
481 | |||
482 | /* (APHY_CALIB is for ADI usage only) */ | ||
483 | |||
484 | #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ | ||
485 | |||
486 | #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | ||
487 | |||
488 | /* (PHY_TEST is for ADI usage only) */ | ||
489 | |||
490 | #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ | ||
491 | |||
492 | #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ | ||
493 | #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | ||
494 | |||
495 | /* USB Endpoint 0 Control Registers */ | ||
496 | |||
497 | #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ | ||
498 | #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ | ||
499 | #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ | ||
500 | #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ | ||
501 | #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ | ||
502 | #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | ||
503 | #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ | ||
504 | #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | ||
505 | #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | ||
506 | #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | ||
507 | |||
508 | /* USB Endpoint 1 Control Registers */ | ||
509 | |||
510 | #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ | ||
511 | #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ | ||
512 | #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ | ||
513 | #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ | ||
514 | #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ | ||
515 | #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | ||
516 | #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ | ||
517 | #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | ||
518 | #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | ||
519 | #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | ||
520 | |||
521 | /* USB Endpoint 2 Control Registers */ | ||
522 | |||
523 | #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ | ||
524 | #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ | ||
525 | #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ | ||
526 | #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ | ||
527 | #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ | ||
528 | #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | ||
529 | #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ | ||
530 | #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | ||
531 | #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | ||
532 | #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | ||
533 | |||
534 | /* USB Endpoint 3 Control Registers */ | ||
535 | |||
536 | #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ | ||
537 | #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ | ||
538 | #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ | ||
539 | #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ | ||
540 | #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ | ||
541 | #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | ||
542 | #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ | ||
543 | #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | ||
544 | #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | ||
545 | #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | ||
546 | |||
547 | /* USB Endpoint 4 Control Registers */ | ||
548 | |||
549 | #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ | ||
550 | #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ | ||
551 | #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ | ||
552 | #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ | ||
553 | #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ | ||
554 | #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | ||
555 | #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ | ||
556 | #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | ||
557 | #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | ||
558 | #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | ||
559 | |||
560 | /* USB Endpoint 5 Control Registers */ | ||
561 | |||
562 | #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ | ||
563 | #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ | ||
564 | #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ | ||
565 | #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ | ||
566 | #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ | ||
567 | #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | ||
568 | #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ | ||
569 | #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | ||
570 | #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | ||
571 | #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ | ||
572 | |||
573 | /* USB Endpoint 6 Control Registers */ | ||
574 | |||
575 | #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ | ||
576 | #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ | ||
577 | #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ | ||
578 | #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ | ||
579 | #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ | ||
580 | #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | ||
581 | #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ | ||
582 | #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | ||
583 | #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | ||
584 | #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | ||
585 | |||
586 | /* USB Endpoint 7 Control Registers */ | ||
587 | |||
588 | #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ | ||
589 | #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ | ||
590 | #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ | ||
591 | #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ | ||
592 | #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ | ||
593 | #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | ||
594 | #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ | ||
595 | #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | ||
596 | #define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | ||
597 | #define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | ||
598 | |||
599 | #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ | ||
600 | |||
601 | /* USB Channel 0 Config Registers */ | ||
602 | |||
603 | #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ | ||
604 | #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | ||
605 | #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | ||
606 | #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
607 | #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
608 | |||
609 | /* USB Channel 1 Config Registers */ | ||
610 | |||
611 | #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ | ||
612 | #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | ||
613 | #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | ||
614 | #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
615 | #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
616 | |||
617 | /* USB Channel 2 Config Registers */ | ||
618 | |||
619 | #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ | ||
620 | #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | ||
621 | #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | ||
622 | #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
623 | #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
624 | |||
625 | /* USB Channel 3 Config Registers */ | ||
626 | |||
627 | #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ | ||
628 | #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | ||
629 | #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | ||
630 | #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
631 | #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
632 | |||
633 | /* USB Channel 4 Config Registers */ | ||
634 | |||
635 | #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ | ||
636 | #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | ||
637 | #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | ||
638 | #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
639 | #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
640 | |||
641 | /* USB Channel 5 Config Registers */ | ||
642 | |||
643 | #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ | ||
644 | #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | ||
645 | #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | ||
646 | #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
647 | #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
648 | |||
649 | /* USB Channel 6 Config Registers */ | ||
650 | |||
651 | #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ | ||
652 | #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | ||
653 | #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | ||
654 | #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
655 | #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
656 | |||
657 | /* USB Channel 7 Config Registers */ | ||
658 | |||
659 | #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ | ||
660 | #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | ||
661 | #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | ||
662 | #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
663 | #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
664 | |||
665 | /* Bit masks for USB_FADDR */ | ||
666 | |||
667 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | ||
668 | |||
669 | /* Bit masks for USB_POWER */ | ||
670 | |||
671 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | ||
672 | #define nENABLE_SUSPENDM 0x0 | ||
673 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | ||
674 | #define nSUSPEND_MODE 0x0 | ||
675 | #define RESUME_MODE 0x4 /* DMA Mode */ | ||
676 | #define nRESUME_MODE 0x0 | ||
677 | #define RESET 0x8 /* Reset indicator */ | ||
678 | #define nRESET 0x0 | ||
679 | #define HS_MODE 0x10 /* High Speed mode indicator */ | ||
680 | #define nHS_MODE 0x0 | ||
681 | #define HS_ENABLE 0x20 /* high Speed Enable */ | ||
682 | #define nHS_ENABLE 0x0 | ||
683 | #define SOFT_CONN 0x40 /* Soft connect */ | ||
684 | #define nSOFT_CONN 0x0 | ||
685 | #define ISO_UPDATE 0x80 /* Isochronous update */ | ||
686 | #define nISO_UPDATE 0x0 | ||
687 | |||
688 | /* Bit masks for USB_INTRTX */ | ||
689 | |||
690 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | ||
691 | #define nEP0_TX 0x0 | ||
692 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | ||
693 | #define nEP1_TX 0x0 | ||
694 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | ||
695 | #define nEP2_TX 0x0 | ||
696 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | ||
697 | #define nEP3_TX 0x0 | ||
698 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | ||
699 | #define nEP4_TX 0x0 | ||
700 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | ||
701 | #define nEP5_TX 0x0 | ||
702 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | ||
703 | #define nEP6_TX 0x0 | ||
704 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | ||
705 | #define nEP7_TX 0x0 | ||
706 | |||
707 | /* Bit masks for USB_INTRRX */ | ||
708 | |||
709 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | ||
710 | #define nEP1_RX 0x0 | ||
711 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | ||
712 | #define nEP2_RX 0x0 | ||
713 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | ||
714 | #define nEP3_RX 0x0 | ||
715 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | ||
716 | #define nEP4_RX 0x0 | ||
717 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | ||
718 | #define nEP5_RX 0x0 | ||
719 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | ||
720 | #define nEP6_RX 0x0 | ||
721 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | ||
722 | #define nEP7_RX 0x0 | ||
723 | |||
724 | /* Bit masks for USB_INTRTXE */ | ||
725 | |||
726 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | ||
727 | #define nEP0_TX_E 0x0 | ||
728 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | ||
729 | #define nEP1_TX_E 0x0 | ||
730 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | ||
731 | #define nEP2_TX_E 0x0 | ||
732 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | ||
733 | #define nEP3_TX_E 0x0 | ||
734 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | ||
735 | #define nEP4_TX_E 0x0 | ||
736 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | ||
737 | #define nEP5_TX_E 0x0 | ||
738 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | ||
739 | #define nEP6_TX_E 0x0 | ||
740 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | ||
741 | #define nEP7_TX_E 0x0 | ||
742 | |||
743 | /* Bit masks for USB_INTRRXE */ | ||
744 | |||
745 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | ||
746 | #define nEP1_RX_E 0x0 | ||
747 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | ||
748 | #define nEP2_RX_E 0x0 | ||
749 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | ||
750 | #define nEP3_RX_E 0x0 | ||
751 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | ||
752 | #define nEP4_RX_E 0x0 | ||
753 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | ||
754 | #define nEP5_RX_E 0x0 | ||
755 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | ||
756 | #define nEP6_RX_E 0x0 | ||
757 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | ||
758 | #define nEP7_RX_E 0x0 | ||
759 | |||
760 | /* Bit masks for USB_INTRUSB */ | ||
761 | |||
762 | #define SUSPEND_B 0x1 /* Suspend indicator */ | ||
763 | #define nSUSPEND_B 0x0 | ||
764 | #define RESUME_B 0x2 /* Resume indicator */ | ||
765 | #define nRESUME_B 0x0 | ||
766 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | ||
767 | #define nRESET_OR_BABLE_B 0x0 | ||
768 | #define SOF_B 0x8 /* Start of frame */ | ||
769 | #define nSOF_B 0x0 | ||
770 | #define CONN_B 0x10 /* Connection indicator */ | ||
771 | #define nCONN_B 0x0 | ||
772 | #define DISCON_B 0x20 /* Disconnect indicator */ | ||
773 | #define nDISCON_B 0x0 | ||
774 | #define SESSION_REQ_B 0x40 /* Session Request */ | ||
775 | #define nSESSION_REQ_B 0x0 | ||
776 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | ||
777 | #define nVBUS_ERROR_B 0x0 | ||
778 | |||
779 | /* Bit masks for USB_INTRUSBE */ | ||
780 | |||
781 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | ||
782 | #define nSUSPEND_BE 0x0 | ||
783 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | ||
784 | #define nRESUME_BE 0x0 | ||
785 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | ||
786 | #define nRESET_OR_BABLE_BE 0x0 | ||
787 | #define SOF_BE 0x8 /* Start of frame int enable */ | ||
788 | #define nSOF_BE 0x0 | ||
789 | #define CONN_BE 0x10 /* Connection indicator int enable */ | ||
790 | #define nCONN_BE 0x0 | ||
791 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | ||
792 | #define nDISCON_BE 0x0 | ||
793 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | ||
794 | #define nSESSION_REQ_BE 0x0 | ||
795 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | ||
796 | #define nVBUS_ERROR_BE 0x0 | ||
797 | |||
798 | /* Bit masks for USB_FRAME */ | ||
799 | |||
800 | #define FRAME_NUMBER 0x7ff /* Frame number */ | ||
801 | |||
802 | /* Bit masks for USB_INDEX */ | ||
803 | |||
804 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | ||
805 | |||
806 | /* Bit masks for USB_GLOBAL_CTL */ | ||
807 | |||
808 | #define GLOBAL_ENA 0x1 /* enables USB module */ | ||
809 | #define nGLOBAL_ENA 0x0 | ||
810 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | ||
811 | #define nEP1_TX_ENA 0x0 | ||
812 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | ||
813 | #define nEP2_TX_ENA 0x0 | ||
814 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | ||
815 | #define nEP3_TX_ENA 0x0 | ||
816 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | ||
817 | #define nEP4_TX_ENA 0x0 | ||
818 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | ||
819 | #define nEP5_TX_ENA 0x0 | ||
820 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | ||
821 | #define nEP6_TX_ENA 0x0 | ||
822 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | ||
823 | #define nEP7_TX_ENA 0x0 | ||
824 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | ||
825 | #define nEP1_RX_ENA 0x0 | ||
826 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | ||
827 | #define nEP2_RX_ENA 0x0 | ||
828 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | ||
829 | #define nEP3_RX_ENA 0x0 | ||
830 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | ||
831 | #define nEP4_RX_ENA 0x0 | ||
832 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | ||
833 | #define nEP5_RX_ENA 0x0 | ||
834 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | ||
835 | #define nEP6_RX_ENA 0x0 | ||
836 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | ||
837 | #define nEP7_RX_ENA 0x0 | ||
838 | |||
839 | /* Bit masks for USB_OTG_DEV_CTL */ | ||
840 | |||
841 | #define SESSION 0x1 /* session indicator */ | ||
842 | #define nSESSION 0x0 | ||
843 | #define HOST_REQ 0x2 /* Host negotiation request */ | ||
844 | #define nHOST_REQ 0x0 | ||
845 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | ||
846 | #define nHOST_MODE 0x0 | ||
847 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | ||
848 | #define nVBUS0 0x0 | ||
849 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | ||
850 | #define nVBUS1 0x0 | ||
851 | #define LSDEV 0x20 /* Low-speed indicator */ | ||
852 | #define nLSDEV 0x0 | ||
853 | #define FSDEV 0x40 /* Full or High-speed indicator */ | ||
854 | #define nFSDEV 0x0 | ||
855 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | ||
856 | #define nB_DEVICE 0x0 | ||
857 | |||
858 | /* Bit masks for USB_OTG_VBUS_IRQ */ | ||
859 | |||
860 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | ||
861 | #define nDRIVE_VBUS_ON 0x0 | ||
862 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | ||
863 | #define nDRIVE_VBUS_OFF 0x0 | ||
864 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | ||
865 | #define nCHRG_VBUS_START 0x0 | ||
866 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | ||
867 | #define nCHRG_VBUS_END 0x0 | ||
868 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | ||
869 | #define nDISCHRG_VBUS_START 0x0 | ||
870 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | ||
871 | #define nDISCHRG_VBUS_END 0x0 | ||
872 | |||
873 | /* Bit masks for USB_OTG_VBUS_MASK */ | ||
874 | |||
875 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | ||
876 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
877 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | ||
878 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
879 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | ||
880 | #define nCHRG_VBUS_START_ENA 0x0 | ||
881 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | ||
882 | #define nCHRG_VBUS_END_ENA 0x0 | ||
883 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | ||
884 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
885 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | ||
886 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
887 | |||
888 | /* Bit masks for USB_CSR0 */ | ||
889 | |||
890 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | ||
891 | #define nRXPKTRDY 0x0 | ||
892 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | ||
893 | #define nTXPKTRDY 0x0 | ||
894 | #define STALL_SENT 0x4 /* STALL handshake sent */ | ||
895 | #define nSTALL_SENT 0x0 | ||
896 | #define DATAEND 0x8 /* Data end indicator */ | ||
897 | #define nDATAEND 0x0 | ||
898 | #define SETUPEND 0x10 /* Setup end */ | ||
899 | #define nSETUPEND 0x0 | ||
900 | #define SENDSTALL 0x20 /* Send STALL handshake */ | ||
901 | #define nSENDSTALL 0x0 | ||
902 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | ||
903 | #define nSERVICED_RXPKTRDY 0x0 | ||
904 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | ||
905 | #define nSERVICED_SETUPEND 0x0 | ||
906 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | ||
907 | #define nFLUSHFIFO 0x0 | ||
908 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | ||
909 | #define nSTALL_RECEIVED_H 0x0 | ||
910 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | ||
911 | #define nSETUPPKT_H 0x0 | ||
912 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | ||
913 | #define nERROR_H 0x0 | ||
914 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | ||
915 | #define nREQPKT_H 0x0 | ||
916 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | ||
917 | #define nSTATUSPKT_H 0x0 | ||
918 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | ||
919 | #define nNAK_TIMEOUT_H 0x0 | ||
920 | |||
921 | /* Bit masks for USB_COUNT0 */ | ||
922 | |||
923 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | ||
924 | |||
925 | /* Bit masks for USB_NAKLIMIT0 */ | ||
926 | |||
927 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | ||
928 | |||
929 | /* Bit masks for USB_TX_MAX_PACKET */ | ||
930 | |||
931 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | ||
932 | |||
933 | /* Bit masks for USB_RX_MAX_PACKET */ | ||
934 | |||
935 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | ||
936 | |||
937 | /* Bit masks for USB_TXCSR */ | ||
938 | |||
939 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | ||
940 | #define nTXPKTRDY_T 0x0 | ||
941 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | ||
942 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
943 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | ||
944 | #define nUNDERRUN_T 0x0 | ||
945 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | ||
946 | #define nFLUSHFIFO_T 0x0 | ||
947 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | ||
948 | #define nSTALL_SEND_T 0x0 | ||
949 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | ||
950 | #define nSTALL_SENT_T 0x0 | ||
951 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | ||
952 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
953 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | ||
954 | #define nINCOMPTX_T 0x0 | ||
955 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | ||
956 | #define nDMAREQMODE_T 0x0 | ||
957 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | ||
958 | #define nFORCE_DATATOGGLE_T 0x0 | ||
959 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | ||
960 | #define nDMAREQ_ENA_T 0x0 | ||
961 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | ||
962 | #define nISO_T 0x0 | ||
963 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | ||
964 | #define nAUTOSET_T 0x0 | ||
965 | #define ERROR_TH 0x4 /* error condition host mode */ | ||
966 | #define nERROR_TH 0x0 | ||
967 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | ||
968 | #define nSTALL_RECEIVED_TH 0x0 | ||
969 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | ||
970 | #define nNAK_TIMEOUT_TH 0x0 | ||
971 | |||
972 | /* Bit masks for USB_TXCOUNT */ | ||
973 | |||
974 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
975 | |||
976 | /* Bit masks for USB_RXCSR */ | ||
977 | |||
978 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | ||
979 | #define nRXPKTRDY_R 0x0 | ||
980 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | ||
981 | #define nFIFO_FULL_R 0x0 | ||
982 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | ||
983 | #define nOVERRUN_R 0x0 | ||
984 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | ||
985 | #define nDATAERROR_R 0x0 | ||
986 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | ||
987 | #define nFLUSHFIFO_R 0x0 | ||
988 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | ||
989 | #define nSTALL_SEND_R 0x0 | ||
990 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | ||
991 | #define nSTALL_SENT_R 0x0 | ||
992 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | ||
993 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
994 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | ||
995 | #define nINCOMPRX_R 0x0 | ||
996 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | ||
997 | #define nDMAREQMODE_R 0x0 | ||
998 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | ||
999 | #define nDISNYET_R 0x0 | ||
1000 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | ||
1001 | #define nDMAREQ_ENA_R 0x0 | ||
1002 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | ||
1003 | #define nISO_R 0x0 | ||
1004 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | ||
1005 | #define nAUTOCLEAR_R 0x0 | ||
1006 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | ||
1007 | #define nERROR_RH 0x0 | ||
1008 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | ||
1009 | #define nREQPKT_RH 0x0 | ||
1010 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | ||
1011 | #define nSTALL_RECEIVED_RH 0x0 | ||
1012 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | ||
1013 | #define nINCOMPRX_RH 0x0 | ||
1014 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | ||
1015 | #define nDMAREQMODE_RH 0x0 | ||
1016 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | ||
1017 | #define nAUTOREQ_RH 0x0 | ||
1018 | |||
1019 | /* Bit masks for USB_RXCOUNT */ | ||
1020 | |||
1021 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | ||
1022 | |||
1023 | /* Bit masks for USB_TXTYPE */ | ||
1024 | |||
1025 | #define TARGET_EP_NO_T 0xf /* EP number */ | ||
1026 | #define PROTOCOL_T 0xc /* transfer type */ | ||
1027 | |||
1028 | /* Bit masks for USB_TXINTERVAL */ | ||
1029 | |||
1030 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | ||
1031 | |||
1032 | /* Bit masks for USB_RXTYPE */ | ||
1033 | |||
1034 | #define TARGET_EP_NO_R 0xf /* EP number */ | ||
1035 | #define PROTOCOL_R 0xc /* transfer type */ | ||
1036 | |||
1037 | /* Bit masks for USB_RXINTERVAL */ | ||
1038 | |||
1039 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | ||
1040 | |||
1041 | /* Bit masks for USB_DMA_INTERRUPT */ | ||
1042 | |||
1043 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | ||
1044 | #define nDMA0_INT 0x0 | ||
1045 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | ||
1046 | #define nDMA1_INT 0x0 | ||
1047 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | ||
1048 | #define nDMA2_INT 0x0 | ||
1049 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | ||
1050 | #define nDMA3_INT 0x0 | ||
1051 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | ||
1052 | #define nDMA4_INT 0x0 | ||
1053 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | ||
1054 | #define nDMA5_INT 0x0 | ||
1055 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | ||
1056 | #define nDMA6_INT 0x0 | ||
1057 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | ||
1058 | #define nDMA7_INT 0x0 | ||
1059 | |||
1060 | /* Bit masks for USB_DMAxCONTROL */ | ||
1061 | |||
1062 | #define DMA_ENA 0x1 /* DMA enable */ | ||
1063 | #define nDMA_ENA 0x0 | ||
1064 | #define DIRECTION 0x2 /* direction of DMA transfer */ | ||
1065 | #define nDIRECTION 0x0 | ||
1066 | #define MODE 0x4 /* DMA Bus error */ | ||
1067 | #define nMODE 0x0 | ||
1068 | #define INT_ENA 0x8 /* Interrupt enable */ | ||
1069 | #define nINT_ENA 0x0 | ||
1070 | #define EPNUM 0xf0 /* EP number */ | ||
1071 | #define BUSERROR 0x100 /* DMA Bus error */ | ||
1072 | #define nBUSERROR 0x0 | ||
1073 | |||
1074 | /* Bit masks for USB_DMAxADDRHIGH */ | ||
1075 | |||
1076 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | ||
1077 | |||
1078 | /* Bit masks for USB_DMAxADDRLOW */ | ||
1079 | |||
1080 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | ||
1081 | |||
1082 | /* Bit masks for USB_DMAxCOUNTHIGH */ | ||
1083 | |||
1084 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | ||
1085 | |||
1086 | /* Bit masks for USB_DMAxCOUNTLOW */ | ||
1087 | |||
1088 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | ||
1089 | |||
1090 | #endif /* _DEF_BF527_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h new file mode 100644 index 000000000000..fc69cf93f149 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |||
@@ -0,0 +1,2014 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/defBF52x_base.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF52X_H | ||
32 | #define _DEF_BF52X_H | ||
33 | |||
34 | |||
35 | /* ************************************************************** */ | ||
36 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */ | ||
37 | /* ************************************************************** */ | ||
38 | |||
39 | /* ==== begin from defBF534.h ==== */ | ||
40 | |||
41 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
42 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ | ||
43 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ | ||
44 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ | ||
45 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ | ||
46 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ | ||
47 | #define CHIPID 0xFFC00014 /* Device ID Register */ | ||
48 | |||
49 | |||
50 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
51 | #define SWRST 0xFFC00100 /* Software Reset Register */ | ||
52 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | ||
53 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | ||
54 | |||
55 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | ||
56 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | ||
57 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | ||
58 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | ||
59 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | ||
60 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | ||
61 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | ||
62 | |||
63 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ | ||
64 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | ||
65 | #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ | ||
66 | #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ | ||
67 | #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ | ||
68 | #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ | ||
69 | #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ | ||
70 | #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ | ||
71 | |||
72 | |||
73 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
74 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | ||
75 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | ||
76 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | ||
77 | |||
78 | |||
79 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
80 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | ||
81 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | ||
82 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | ||
83 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | ||
84 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | ||
85 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | ||
86 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ | ||
87 | |||
88 | |||
89 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
90 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | ||
91 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | ||
92 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
93 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
94 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
95 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
96 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | ||
97 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | ||
98 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | ||
99 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ | ||
100 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
101 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | ||
102 | |||
103 | |||
104 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | ||
105 | #define SPI0_REGBASE 0xFFC00500 | ||
106 | #define SPI_CTL 0xFFC00500 /* SPI Control Register */ | ||
107 | #define SPI_FLG 0xFFC00504 /* SPI Flag register */ | ||
108 | #define SPI_STAT 0xFFC00508 /* SPI Status register */ | ||
109 | #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | ||
110 | #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | ||
111 | #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ | ||
112 | #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | ||
113 | |||
114 | |||
115 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
116 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | ||
117 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | ||
118 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | ||
119 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | ||
120 | |||
121 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | ||
122 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | ||
123 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | ||
124 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | ||
125 | |||
126 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | ||
127 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | ||
128 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | ||
129 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | ||
130 | |||
131 | #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ | ||
132 | #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ | ||
133 | #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ | ||
134 | #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ | ||
135 | |||
136 | #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ | ||
137 | #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ | ||
138 | #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ | ||
139 | #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ | ||
140 | |||
141 | #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ | ||
142 | #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ | ||
143 | #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ | ||
144 | #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ | ||
145 | |||
146 | #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ | ||
147 | #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ | ||
148 | #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ | ||
149 | #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ | ||
150 | |||
151 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | ||
152 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | ||
153 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | ||
154 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | ||
155 | |||
156 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | ||
157 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | ||
158 | #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ | ||
159 | |||
160 | |||
161 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
162 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ | ||
163 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ | ||
164 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ | ||
165 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ | ||
166 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ | ||
167 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ | ||
168 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ | ||
169 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ | ||
170 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ | ||
171 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ | ||
172 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ | ||
173 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ | ||
174 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ | ||
175 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ | ||
176 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ | ||
177 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ | ||
178 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ | ||
179 | |||
180 | |||
181 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
182 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
183 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
184 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
185 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
186 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
187 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
188 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
189 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
190 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
191 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
192 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
193 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
194 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
195 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
196 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
197 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
198 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
199 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
200 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
201 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
202 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
203 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
204 | |||
205 | |||
206 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
207 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
208 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
209 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
210 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
211 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
212 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
213 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
214 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
215 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
216 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
217 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
218 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
219 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
220 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
221 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
222 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
223 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
224 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
225 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
226 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
227 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
228 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
229 | |||
230 | |||
231 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
232 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
233 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
234 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
235 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
236 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
237 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
238 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
239 | |||
240 | |||
241 | /* DMA Traffic Control Registers */ | ||
242 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
243 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
244 | |||
245 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
246 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
247 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
248 | |||
249 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | ||
250 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
251 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | ||
252 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | ||
253 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | ||
254 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | ||
255 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | ||
256 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | ||
257 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
258 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | ||
259 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | ||
260 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | ||
261 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | ||
262 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | ||
263 | |||
264 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
265 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | ||
266 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | ||
267 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | ||
268 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | ||
269 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | ||
270 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | ||
271 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
272 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | ||
273 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | ||
274 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | ||
275 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | ||
276 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | ||
277 | |||
278 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
279 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | ||
280 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | ||
281 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | ||
282 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | ||
283 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | ||
284 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | ||
285 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
286 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | ||
287 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | ||
288 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | ||
289 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | ||
290 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | ||
291 | |||
292 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
293 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | ||
294 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | ||
295 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | ||
296 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | ||
297 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | ||
298 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | ||
299 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
300 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | ||
301 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | ||
302 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | ||
303 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | ||
304 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | ||
305 | |||
306 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
307 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | ||
308 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | ||
309 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | ||
310 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | ||
311 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | ||
312 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | ||
313 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
314 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | ||
315 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | ||
316 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | ||
317 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | ||
318 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | ||
319 | |||
320 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
321 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | ||
322 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | ||
323 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | ||
324 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | ||
325 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | ||
326 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | ||
327 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
328 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | ||
329 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | ||
330 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | ||
331 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | ||
332 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | ||
333 | |||
334 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
335 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | ||
336 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | ||
337 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | ||
338 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | ||
339 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | ||
340 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | ||
341 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
342 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | ||
343 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | ||
344 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | ||
345 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | ||
346 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | ||
347 | |||
348 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
349 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | ||
350 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | ||
351 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | ||
352 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | ||
353 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | ||
354 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | ||
355 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
356 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | ||
357 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | ||
358 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | ||
359 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | ||
360 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | ||
361 | |||
362 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
363 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ | ||
364 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ | ||
365 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ | ||
366 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ | ||
367 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ | ||
368 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ | ||
369 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
370 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ | ||
371 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ | ||
372 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ | ||
373 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ | ||
374 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ | ||
375 | |||
376 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
377 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ | ||
378 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ | ||
379 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ | ||
380 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ | ||
381 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ | ||
382 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ | ||
383 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
384 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ | ||
385 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ | ||
386 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ | ||
387 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ | ||
388 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ | ||
389 | |||
390 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
391 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ | ||
392 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ | ||
393 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ | ||
394 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ | ||
395 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ | ||
396 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ | ||
397 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
398 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ | ||
399 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ | ||
400 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ | ||
401 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ | ||
402 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ | ||
403 | |||
404 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
405 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ | ||
406 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ | ||
407 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ | ||
408 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ | ||
409 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ | ||
410 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ | ||
411 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
412 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ | ||
413 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ | ||
414 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ | ||
415 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ | ||
416 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ | ||
417 | |||
418 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | ||
419 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ | ||
420 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ | ||
421 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ | ||
422 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ | ||
423 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ | ||
424 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ | ||
425 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | ||
426 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ | ||
427 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | ||
428 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | ||
429 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ | ||
430 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ | ||
431 | |||
432 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | ||
433 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ | ||
434 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ | ||
435 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ | ||
436 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ | ||
437 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ | ||
438 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ | ||
439 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | ||
440 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ | ||
441 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | ||
442 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ | ||
443 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ | ||
444 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ | ||
445 | |||
446 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | ||
447 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ | ||
448 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ | ||
449 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ | ||
450 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ | ||
451 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ | ||
452 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ | ||
453 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | ||
454 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ | ||
455 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | ||
456 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | ||
457 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ | ||
458 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | ||
459 | |||
460 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | ||
461 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ | ||
462 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ | ||
463 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ | ||
464 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ | ||
465 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ | ||
466 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ | ||
467 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | ||
468 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ | ||
469 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | ||
470 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ | ||
471 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ | ||
472 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ | ||
473 | |||
474 | |||
475 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
476 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | ||
477 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | ||
478 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | ||
479 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | ||
480 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | ||
481 | |||
482 | |||
483 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
484 | #define TWI0_REGBASE 0xFFC01400 | ||
485 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | ||
486 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | ||
487 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | ||
488 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | ||
489 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | ||
490 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | ||
491 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | ||
492 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | ||
493 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | ||
494 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | ||
495 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | ||
496 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | ||
497 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | ||
498 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | ||
499 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | ||
500 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | ||
501 | |||
502 | |||
503 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
504 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | ||
505 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ | ||
506 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ | ||
507 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ | ||
508 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ | ||
509 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ | ||
510 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ | ||
511 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ | ||
512 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ | ||
513 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ | ||
514 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ | ||
515 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ | ||
516 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ | ||
517 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ | ||
518 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ | ||
519 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ | ||
520 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ | ||
521 | |||
522 | |||
523 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
524 | #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ | ||
525 | #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ | ||
526 | #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ | ||
527 | #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ | ||
528 | #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ | ||
529 | #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ | ||
530 | #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ | ||
531 | #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ | ||
532 | #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ | ||
533 | #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ | ||
534 | #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ | ||
535 | #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ | ||
536 | #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ | ||
537 | #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ | ||
538 | #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ | ||
539 | #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ | ||
540 | #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ | ||
541 | |||
542 | |||
543 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
544 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | ||
545 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | ||
546 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | ||
547 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | ||
548 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | ||
549 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | ||
550 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | ||
551 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | ||
552 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | ||
553 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ | ||
554 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | ||
555 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | ||
556 | |||
557 | |||
558 | /* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */ | ||
559 | |||
560 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
561 | #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ | ||
562 | #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ | ||
563 | #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ | ||
564 | #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ | ||
565 | |||
566 | |||
567 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
568 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | ||
569 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | ||
570 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | ||
571 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ | ||
572 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ | ||
573 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | ||
574 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | ||
575 | |||
576 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | ||
577 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | ||
578 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | ||
579 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ | ||
580 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ | ||
581 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | ||
582 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | ||
583 | |||
584 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
585 | #define PORTF_MUX 0xFFC03210 /* Port F mux control */ | ||
586 | #define PORTG_MUX 0xFFC03214 /* Port G mux control */ | ||
587 | #define PORTH_MUX 0xFFC03218 /* Port H mux control */ | ||
588 | #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ | ||
589 | #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ | ||
590 | #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ | ||
591 | #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ | ||
592 | #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ | ||
593 | #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ | ||
594 | #define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ | ||
595 | #define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ | ||
596 | #define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ | ||
597 | #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ | ||
598 | #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ | ||
599 | #define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ | ||
600 | |||
601 | |||
602 | /*********************************************************************************** | ||
603 | ** System MMR Register Bits And Macros | ||
604 | ** | ||
605 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
606 | ** Use these macros carefully, as any that do left shifts for field | ||
607 | ** depositing will result in the lower order bits being destroyed. Any | ||
608 | ** macro that shifts left to properly position the bit-field should be | ||
609 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
610 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
611 | ** the macro is used. | ||
612 | *************************************************************************************/ | ||
613 | /* | ||
614 | ** ********************* PLL AND RESET MASKS ****************************************/ | ||
615 | /* PLL_CTL Masks */ | ||
616 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
617 | #define PLL_OFF 0x0002 /* PLL Not Powered */ | ||
618 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
619 | #define PDWN 0x0020 /* Enter Deep Sleep Mode */ | ||
620 | #define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | ||
621 | #define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | ||
622 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
623 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ | ||
624 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | ||
625 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
626 | |||
627 | /* PLL_DIV Masks */ | ||
628 | #define SSEL 0x000F /* System Select */ | ||
629 | #define CSEL 0x0030 /* Core Select */ | ||
630 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ | ||
631 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ | ||
632 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ | ||
633 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ | ||
634 | /* PLL_DIV Macros */ | ||
635 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
636 | |||
637 | /* VR_CTL Masks */ | ||
638 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | ||
639 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
640 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
641 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
642 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
643 | |||
644 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
645 | #define GAIN_5 0x0000 /* GAIN = 5 */ | ||
646 | #define GAIN_10 0x0004 /* GAIN = 10 */ | ||
647 | #define GAIN_20 0x0008 /* GAIN = 20 */ | ||
648 | #define GAIN_50 0x000C /* GAIN = 50 */ | ||
649 | |||
650 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
651 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
652 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
653 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
654 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
655 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
656 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
657 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
658 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
659 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
660 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
661 | |||
662 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
663 | #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ | ||
664 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ | ||
665 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ | ||
666 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ | ||
667 | #define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ | ||
668 | |||
669 | /* PLL_STAT Masks */ | ||
670 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
671 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
672 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
673 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
674 | |||
675 | /* CHIPID Masks */ | ||
676 | #define CHIPID_VERSION 0xF0000000 | ||
677 | #define CHIPID_FAMILY 0x0FFFF000 | ||
678 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
679 | |||
680 | /* SWRST Masks */ | ||
681 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | ||
682 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | ||
683 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | ||
684 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | ||
685 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | ||
686 | |||
687 | /* SYSCR Masks */ | ||
688 | #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ | ||
689 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | ||
690 | |||
691 | |||
692 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | ||
693 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | ||
694 | |||
695 | #if 0 | ||
696 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | ||
697 | |||
698 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | ||
699 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | ||
700 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | ||
701 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | ||
702 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | ||
703 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | ||
704 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | ||
705 | |||
706 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | ||
707 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | ||
708 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | ||
709 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | ||
710 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | ||
711 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | ||
712 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | ||
713 | #define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ | ||
714 | |||
715 | #define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ | ||
716 | #define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ | ||
717 | #define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ | ||
718 | #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ | ||
719 | #define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ | ||
720 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ | ||
721 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ | ||
722 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ | ||
723 | #define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ | ||
724 | #define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ | ||
725 | |||
726 | #define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ | ||
727 | #define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ | ||
728 | #define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ | ||
729 | #define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ | ||
730 | #define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ | ||
731 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ | ||
732 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ | ||
733 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ | ||
734 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | ||
735 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | ||
736 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | ||
737 | #endif | ||
738 | |||
739 | /* SIC_IAR0 Macros */ | ||
740 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | ||
741 | #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | ||
742 | #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | ||
743 | #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | ||
744 | #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | ||
745 | #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | ||
746 | #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | ||
747 | #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | ||
748 | |||
749 | /* SIC_IAR1 Macros */ | ||
750 | #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ | ||
751 | #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | ||
752 | #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | ||
753 | #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | ||
754 | #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | ||
755 | #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | ||
756 | #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | ||
757 | #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | ||
758 | |||
759 | /* SIC_IAR2 Macros */ | ||
760 | #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ | ||
761 | #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | ||
762 | #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | ||
763 | #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | ||
764 | #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | ||
765 | #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | ||
766 | #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | ||
767 | #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | ||
768 | |||
769 | /* SIC_IAR3 Macros */ | ||
770 | #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ | ||
771 | #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ | ||
772 | #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ | ||
773 | #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ | ||
774 | #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ | ||
775 | #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ | ||
776 | #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ | ||
777 | #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ | ||
778 | |||
779 | |||
780 | /* SIC_IMASK Masks */ | ||
781 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
782 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
783 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | ||
784 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | ||
785 | |||
786 | /* SIC_IWR Masks */ | ||
787 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
788 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
789 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | ||
790 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | ||
791 | |||
792 | |||
793 | /* ********* WATCHDOG TIMER MASKS ******************** */ | ||
794 | |||
795 | /* Watchdog Timer WDOG_CTL Register Masks */ | ||
796 | |||
797 | #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ | ||
798 | #define WDEV_RESET 0x0000 /* generate reset event on roll over */ | ||
799 | #define WDEV_NMI 0x0002 /* generate NMI event on roll over */ | ||
800 | #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ | ||
801 | #define WDEV_NONE 0x0006 /* no event on roll over */ | ||
802 | #define WDEN 0x0FF0 /* enable watchdog */ | ||
803 | #define WDDIS 0x0AD0 /* disable watchdog */ | ||
804 | #define WDRO 0x8000 /* watchdog rolled over latch */ | ||
805 | |||
806 | /* depreciated WDOG_CTL Register Masks for legacy code */ | ||
807 | |||
808 | |||
809 | #define ICTL WDEV | ||
810 | #define ENABLE_RESET WDEV_RESET | ||
811 | #define WDOG_RESET WDEV_RESET | ||
812 | #define ENABLE_NMI WDEV_NMI | ||
813 | #define WDOG_NMI WDEV_NMI | ||
814 | #define ENABLE_GPI WDEV_GPI | ||
815 | #define WDOG_GPI WDEV_GPI | ||
816 | #define DISABLE_EVT WDEV_NONE | ||
817 | #define WDOG_NONE WDEV_NONE | ||
818 | |||
819 | #define TMR_EN WDEN | ||
820 | #define TMR_DIS WDDIS | ||
821 | #define TRO WDRO | ||
822 | #define ICTL_P0 0x01 | ||
823 | #define ICTL_P1 0x02 | ||
824 | #define TRO_P 0x0F | ||
825 | |||
826 | |||
827 | |||
828 | /* *************** REAL TIME CLOCK MASKS **************************/ | ||
829 | /* RTC_STAT and RTC_ALARM Masks */ | ||
830 | #define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ | ||
831 | #define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ | ||
832 | #define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ | ||
833 | #define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ | ||
834 | |||
835 | /* RTC_ALARM Macro z=day y=hr x=min w=sec */ | ||
836 | #define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) | ||
837 | |||
838 | /* RTC_ICTL and RTC_ISTAT Masks */ | ||
839 | #define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ | ||
840 | #define ALARM 0x0002 /* Alarm Interrupt Enable */ | ||
841 | #define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ | ||
842 | #define MINUTE 0x0008 /* Minutes Interrupt Enable */ | ||
843 | #define HOUR 0x0010 /* Hours Interrupt Enable */ | ||
844 | #define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ | ||
845 | #define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ | ||
846 | #define WRITE_PENDING 0x4000 /* Write Pending Status */ | ||
847 | #define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ | ||
848 | |||
849 | /* RTC_FAST / RTC_PREN Mask */ | ||
850 | #define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ | ||
851 | |||
852 | |||
853 | /* ************** UART CONTROLLER MASKS *************************/ | ||
854 | /* UARTx_LCR Masks */ | ||
855 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | ||
856 | #define STB 0x04 /* Stop Bits */ | ||
857 | #define PEN 0x08 /* Parity Enable */ | ||
858 | #define EPS 0x10 /* Even Parity Select */ | ||
859 | #define STP 0x20 /* Stick Parity */ | ||
860 | #define SB 0x40 /* Set Break */ | ||
861 | #define DLAB 0x80 /* Divisor Latch Access */ | ||
862 | |||
863 | /* UARTx_MCR Mask */ | ||
864 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | ||
865 | #define LOOP_ENA_P 0x04 | ||
866 | |||
867 | /* UARTx_LSR Masks */ | ||
868 | #define DR 0x01 /* Data Ready */ | ||
869 | #define OE 0x02 /* Overrun Error */ | ||
870 | #define PE 0x04 /* Parity Error */ | ||
871 | #define FE 0x08 /* Framing Error */ | ||
872 | #define BI 0x10 /* Break Interrupt */ | ||
873 | #define THRE 0x20 /* THR Empty */ | ||
874 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | ||
875 | |||
876 | /* UARTx_IER Masks */ | ||
877 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | ||
878 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | ||
879 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | ||
880 | |||
881 | /* UARTx_IIR Masks */ | ||
882 | #define NINT 0x01 /* Pending Interrupt */ | ||
883 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | ||
884 | #define IIR_RX_READY 0x04 /* Receive data ready */ | ||
885 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | ||
886 | #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ | ||
887 | |||
888 | /* UARTx_GCTL Masks */ | ||
889 | #define UCEN 0x01 /* Enable UARTx Clocks */ | ||
890 | #define IREN 0x02 /* Enable IrDA Mode */ | ||
891 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ | ||
892 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | ||
893 | #define FPE 0x10 /* Force Parity Error On Transmit */ | ||
894 | #define FFE 0x20 /* Force Framing Error On Transmit */ | ||
895 | |||
896 | |||
897 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ | ||
898 | /* SPI_CTL Masks */ | ||
899 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | ||
900 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
901 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
902 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
903 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
904 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | ||
905 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | ||
906 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | ||
907 | #define EMISO 0x0020 /* Enable MISO As Output */ | ||
908 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | ||
909 | #define LSBF 0x0200 /* LSB First */ | ||
910 | #define CPHA 0x0400 /* Clock Phase */ | ||
911 | #define CPOL 0x0800 /* Clock Polarity */ | ||
912 | #define MSTR 0x1000 /* Master/Slave* */ | ||
913 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
914 | #define SPE 0x4000 /* SPI Enable */ | ||
915 | |||
916 | /* SPI_FLG Masks */ | ||
917 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ | ||
918 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ | ||
919 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ | ||
920 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ | ||
921 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ | ||
922 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ | ||
923 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ | ||
924 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ | ||
925 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ | ||
926 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ | ||
927 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ | ||
928 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ | ||
929 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ | ||
930 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ | ||
931 | |||
932 | /* SPI_STAT Masks */ | ||
933 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ | ||
934 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ | ||
935 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ | ||
936 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ | ||
937 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ | ||
938 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ | ||
939 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ | ||
940 | |||
941 | |||
942 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | ||
943 | /* TIMER_ENABLE Masks */ | ||
944 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | ||
945 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | ||
946 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | ||
947 | #define TIMEN3 0x0008 /* Enable Timer 3 */ | ||
948 | #define TIMEN4 0x0010 /* Enable Timer 4 */ | ||
949 | #define TIMEN5 0x0020 /* Enable Timer 5 */ | ||
950 | #define TIMEN6 0x0040 /* Enable Timer 6 */ | ||
951 | #define TIMEN7 0x0080 /* Enable Timer 7 */ | ||
952 | |||
953 | /* TIMER_DISABLE Masks */ | ||
954 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ | ||
955 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ | ||
956 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ | ||
957 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ | ||
958 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ | ||
959 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ | ||
960 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ | ||
961 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ | ||
962 | |||
963 | /* TIMER_STATUS Masks */ | ||
964 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ | ||
965 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ | ||
966 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ | ||
967 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ | ||
968 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ | ||
969 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ | ||
970 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ | ||
971 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ | ||
972 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ | ||
973 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ | ||
974 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ | ||
975 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ | ||
976 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ | ||
977 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ | ||
978 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ | ||
979 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ | ||
980 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ | ||
981 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ | ||
982 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ | ||
983 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ | ||
984 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | ||
985 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | ||
986 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | ||
987 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | ||
988 | |||
989 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
990 | #define TOVL_ERR0 TOVF_ERR0 | ||
991 | #define TOVL_ERR1 TOVF_ERR1 | ||
992 | #define TOVL_ERR2 TOVF_ERR2 | ||
993 | #define TOVL_ERR3 TOVF_ERR3 | ||
994 | #define TOVL_ERR4 TOVF_ERR4 | ||
995 | #define TOVL_ERR5 TOVF_ERR5 | ||
996 | #define TOVL_ERR6 TOVF_ERR6 | ||
997 | #define TOVL_ERR7 TOVF_ERR7 | ||
998 | |||
999 | /* TIMERx_CONFIG Masks */ | ||
1000 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ | ||
1001 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ | ||
1002 | #define EXT_CLK 0x0003 /* External Clock Mode */ | ||
1003 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ | ||
1004 | #define PERIOD_CNT 0x0008 /* Period Count */ | ||
1005 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ | ||
1006 | #define TIN_SEL 0x0020 /* Timer Input Select */ | ||
1007 | #define OUT_DIS 0x0040 /* Output Pad Disable */ | ||
1008 | #define CLK_SEL 0x0080 /* Timer Clock Select */ | ||
1009 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ | ||
1010 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ | ||
1011 | #define ERR_TYP 0xC000 /* Error Type */ | ||
1012 | |||
1013 | |||
1014 | /* ****************** GPIO PORTS F, G, H MASKS ***********************/ | ||
1015 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | ||
1016 | /* Port F Masks */ | ||
1017 | #define PF0 0x0001 | ||
1018 | #define PF1 0x0002 | ||
1019 | #define PF2 0x0004 | ||
1020 | #define PF3 0x0008 | ||
1021 | #define PF4 0x0010 | ||
1022 | #define PF5 0x0020 | ||
1023 | #define PF6 0x0040 | ||
1024 | #define PF7 0x0080 | ||
1025 | #define PF8 0x0100 | ||
1026 | #define PF9 0x0200 | ||
1027 | #define PF10 0x0400 | ||
1028 | #define PF11 0x0800 | ||
1029 | #define PF12 0x1000 | ||
1030 | #define PF13 0x2000 | ||
1031 | #define PF14 0x4000 | ||
1032 | #define PF15 0x8000 | ||
1033 | |||
1034 | /* Port G Masks */ | ||
1035 | #define PG0 0x0001 | ||
1036 | #define PG1 0x0002 | ||
1037 | #define PG2 0x0004 | ||
1038 | #define PG3 0x0008 | ||
1039 | #define PG4 0x0010 | ||
1040 | #define PG5 0x0020 | ||
1041 | #define PG6 0x0040 | ||
1042 | #define PG7 0x0080 | ||
1043 | #define PG8 0x0100 | ||
1044 | #define PG9 0x0200 | ||
1045 | #define PG10 0x0400 | ||
1046 | #define PG11 0x0800 | ||
1047 | #define PG12 0x1000 | ||
1048 | #define PG13 0x2000 | ||
1049 | #define PG14 0x4000 | ||
1050 | #define PG15 0x8000 | ||
1051 | |||
1052 | /* Port H Masks */ | ||
1053 | #define PH0 0x0001 | ||
1054 | #define PH1 0x0002 | ||
1055 | #define PH2 0x0004 | ||
1056 | #define PH3 0x0008 | ||
1057 | #define PH4 0x0010 | ||
1058 | #define PH5 0x0020 | ||
1059 | #define PH6 0x0040 | ||
1060 | #define PH7 0x0080 | ||
1061 | #define PH8 0x0100 | ||
1062 | #define PH9 0x0200 | ||
1063 | #define PH10 0x0400 | ||
1064 | #define PH11 0x0800 | ||
1065 | #define PH12 0x1000 | ||
1066 | #define PH13 0x2000 | ||
1067 | #define PH14 0x4000 | ||
1068 | #define PH15 0x8000 | ||
1069 | |||
1070 | |||
1071 | /* ******************* SERIAL PORT MASKS **************************************/ | ||
1072 | /* SPORTx_TCR1 Masks */ | ||
1073 | #define TSPEN 0x0001 /* Transmit Enable */ | ||
1074 | #define ITCLK 0x0002 /* Internal Transmit Clock Select */ | ||
1075 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
1076 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
1077 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
1078 | #define TLSBIT 0x0010 /* Transmit Bit Order */ | ||
1079 | #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ | ||
1080 | #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ | ||
1081 | #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ | ||
1082 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | ||
1083 | #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ | ||
1084 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | ||
1085 | |||
1086 | /* SPORTx_TCR2 Masks and Macro */ | ||
1087 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
1088 | #define TXSE 0x0100 /* TX Secondary Enable */ | ||
1089 | #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ | ||
1090 | #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ | ||
1091 | |||
1092 | /* SPORTx_RCR1 Masks */ | ||
1093 | #define RSPEN 0x0001 /* Receive Enable */ | ||
1094 | #define IRCLK 0x0002 /* Internal Receive Clock Select */ | ||
1095 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
1096 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
1097 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
1098 | #define RLSBIT 0x0010 /* Receive Bit Order */ | ||
1099 | #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ | ||
1100 | #define RFSR 0x0400 /* Receive Frame Sync Required Select */ | ||
1101 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | ||
1102 | #define LARFS 0x2000 /* Late Receive Frame Sync Select */ | ||
1103 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | ||
1104 | |||
1105 | /* SPORTx_RCR2 Masks */ | ||
1106 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ | ||
1107 | #define RXSE 0x0100 /* RX Secondary Enable */ | ||
1108 | #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ | ||
1109 | #define RRFST 0x0400 /* Right-First Data Order */ | ||
1110 | |||
1111 | /* SPORTx_STAT Masks */ | ||
1112 | #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ | ||
1113 | #define RUVF 0x0002 /* Sticky Receive Underflow Status */ | ||
1114 | #define ROVF 0x0004 /* Sticky Receive Overflow Status */ | ||
1115 | #define TXF 0x0008 /* Transmit FIFO Full Status */ | ||
1116 | #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ | ||
1117 | #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ | ||
1118 | #define TXHRE 0x0040 /* Transmit Hold Register Empty */ | ||
1119 | |||
1120 | /* SPORTx_MCMC1 Macros */ | ||
1121 | #define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
1122 | |||
1123 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
1124 | #define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
1125 | |||
1126 | /* SPORTx_MCMC2 Masks */ | ||
1127 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
1128 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
1129 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
1130 | #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ | ||
1131 | #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ | ||
1132 | #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ | ||
1133 | #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ | ||
1134 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
1135 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
1136 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
1137 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
1138 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
1139 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
1140 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
1141 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
1142 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
1143 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
1144 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
1145 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
1146 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
1147 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
1148 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
1149 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
1150 | |||
1151 | |||
1152 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | ||
1153 | /* EBIU_AMGCTL Masks */ | ||
1154 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
1155 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
1156 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | ||
1157 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | ||
1158 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | ||
1159 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | ||
1160 | |||
1161 | /* EBIU_AMBCTL0 Masks */ | ||
1162 | #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ | ||
1163 | #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ | ||
1164 | #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ | ||
1165 | #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ | ||
1166 | #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ | ||
1167 | #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ | ||
1168 | #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
1169 | #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
1170 | #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
1171 | #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
1172 | #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
1173 | #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
1174 | #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
1175 | #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
1176 | #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ | ||
1177 | #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ | ||
1178 | #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ | ||
1179 | #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ | ||
1180 | #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ | ||
1181 | #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ | ||
1182 | #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ | ||
1183 | #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ | ||
1184 | #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ | ||
1185 | #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ | ||
1186 | #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ | ||
1187 | #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ | ||
1188 | #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ | ||
1189 | #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ | ||
1190 | #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ | ||
1191 | #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ | ||
1192 | #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ | ||
1193 | #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ | ||
1194 | #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ | ||
1195 | #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ | ||
1196 | #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ | ||
1197 | #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ | ||
1198 | #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ | ||
1199 | #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ | ||
1200 | #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ | ||
1201 | #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ | ||
1202 | #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ | ||
1203 | #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ | ||
1204 | #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ | ||
1205 | #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ | ||
1206 | |||
1207 | #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ | ||
1208 | #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ | ||
1209 | #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ | ||
1210 | #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ | ||
1211 | #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ | ||
1212 | #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ | ||
1213 | #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
1214 | #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
1215 | #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
1216 | #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
1217 | #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
1218 | #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
1219 | #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
1220 | #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
1221 | #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ | ||
1222 | #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ | ||
1223 | #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ | ||
1224 | #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ | ||
1225 | #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ | ||
1226 | #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ | ||
1227 | #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ | ||
1228 | #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ | ||
1229 | #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ | ||
1230 | #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ | ||
1231 | #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ | ||
1232 | #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ | ||
1233 | #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ | ||
1234 | #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ | ||
1235 | #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ | ||
1236 | #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ | ||
1237 | #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ | ||
1238 | #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ | ||
1239 | #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ | ||
1240 | #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ | ||
1241 | #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ | ||
1242 | #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ | ||
1243 | #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ | ||
1244 | #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ | ||
1245 | #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ | ||
1246 | #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ | ||
1247 | #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ | ||
1248 | #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ | ||
1249 | #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ | ||
1250 | #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ | ||
1251 | |||
1252 | /* EBIU_AMBCTL1 Masks */ | ||
1253 | #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ | ||
1254 | #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ | ||
1255 | #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ | ||
1256 | #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ | ||
1257 | #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ | ||
1258 | #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ | ||
1259 | #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
1260 | #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
1261 | #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
1262 | #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
1263 | #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
1264 | #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
1265 | #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
1266 | #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
1267 | #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ | ||
1268 | #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ | ||
1269 | #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ | ||
1270 | #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ | ||
1271 | #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ | ||
1272 | #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ | ||
1273 | #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ | ||
1274 | #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ | ||
1275 | #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ | ||
1276 | #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ | ||
1277 | #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ | ||
1278 | #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ | ||
1279 | #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ | ||
1280 | #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ | ||
1281 | #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ | ||
1282 | #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ | ||
1283 | #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ | ||
1284 | #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ | ||
1285 | #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ | ||
1286 | #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ | ||
1287 | #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ | ||
1288 | #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ | ||
1289 | #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ | ||
1290 | #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ | ||
1291 | #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ | ||
1292 | #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ | ||
1293 | #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ | ||
1294 | #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ | ||
1295 | #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ | ||
1296 | #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ | ||
1297 | |||
1298 | #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ | ||
1299 | #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ | ||
1300 | #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ | ||
1301 | #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ | ||
1302 | #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ | ||
1303 | #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ | ||
1304 | #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
1305 | #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
1306 | #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
1307 | #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
1308 | #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
1309 | #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
1310 | #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
1311 | #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
1312 | #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ | ||
1313 | #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ | ||
1314 | #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ | ||
1315 | #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ | ||
1316 | #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ | ||
1317 | #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ | ||
1318 | #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ | ||
1319 | #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ | ||
1320 | #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ | ||
1321 | #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ | ||
1322 | #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ | ||
1323 | #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ | ||
1324 | #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ | ||
1325 | #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ | ||
1326 | #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ | ||
1327 | #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ | ||
1328 | #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ | ||
1329 | #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ | ||
1330 | #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ | ||
1331 | #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ | ||
1332 | #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ | ||
1333 | #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ | ||
1334 | #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ | ||
1335 | #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ | ||
1336 | #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ | ||
1337 | #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ | ||
1338 | #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ | ||
1339 | #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ | ||
1340 | #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ | ||
1341 | #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ | ||
1342 | |||
1343 | |||
1344 | /* ********************** SDRAM CONTROLLER MASKS **********************************************/ | ||
1345 | /* EBIU_SDGCTL Masks */ | ||
1346 | #define SCTLE 0x00000001 /* Enable SDRAM Signals */ | ||
1347 | #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ | ||
1348 | #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ | ||
1349 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | ||
1350 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | ||
1351 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | ||
1352 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
1353 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
1354 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
1355 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
1356 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
1357 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
1358 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
1359 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
1360 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
1361 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
1362 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
1363 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
1364 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
1365 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
1366 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
1367 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
1368 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
1369 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
1370 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
1371 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
1372 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
1373 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
1374 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
1375 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
1376 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
1377 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
1378 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
1379 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
1380 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
1381 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
1382 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
1383 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
1384 | #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ | ||
1385 | #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ | ||
1386 | #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ | ||
1387 | #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ | ||
1388 | #define EBUFE 0x02000000 /* Enable External Buffering Timing */ | ||
1389 | #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ | ||
1390 | #define EMREN 0x10000000 /* Extended Mode Register Enable */ | ||
1391 | #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ | ||
1392 | #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ | ||
1393 | |||
1394 | /* EBIU_SDBCTL Masks */ | ||
1395 | #define EBE 0x0001 /* Enable SDRAM External Bank */ | ||
1396 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ | ||
1397 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ | ||
1398 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ | ||
1399 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ | ||
1400 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ | ||
1401 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ | ||
1402 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ | ||
1403 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ | ||
1404 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ | ||
1405 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ | ||
1406 | |||
1407 | /* EBIU_SDSTAT Masks */ | ||
1408 | #define SDCI 0x0001 /* SDRAM Controller Idle */ | ||
1409 | #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ | ||
1410 | #define SDPUA 0x0004 /* SDRAM Power-Up Active */ | ||
1411 | #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ | ||
1412 | #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ | ||
1413 | #define BGSTAT 0x0020 /* Bus Grant Status */ | ||
1414 | |||
1415 | |||
1416 | /* ************************** DMA CONTROLLER MASKS ********************************/ | ||
1417 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | ||
1418 | #define DMAEN 0x0001 /* DMA Channel Enable */ | ||
1419 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | ||
1420 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ | ||
1421 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ | ||
1422 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ | ||
1423 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ | ||
1424 | #define RESTART 0x0020 /* DMA Buffer Clear */ | ||
1425 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ | ||
1426 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | ||
1427 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
1428 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
1429 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
1430 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
1431 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
1432 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
1433 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
1434 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
1435 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
1436 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
1437 | #define NDSIZE 0x0900 /* Next Descriptor Size */ | ||
1438 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
1439 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
1440 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
1441 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
1442 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
1443 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
1444 | |||
1445 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | ||
1446 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | ||
1447 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ | ||
1448 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ | ||
1449 | #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ | ||
1450 | #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ | ||
1451 | #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ | ||
1452 | #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ | ||
1453 | #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ | ||
1454 | #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ | ||
1455 | #define PMAP_SPI 0x7000 /* SPI Port DMA */ | ||
1456 | #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ | ||
1457 | #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ | ||
1458 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | ||
1459 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | ||
1460 | |||
1461 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | ||
1462 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ | ||
1463 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ | ||
1464 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | ||
1465 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | ||
1466 | |||
1467 | |||
1468 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | ||
1469 | /* PPI_CONTROL Masks */ | ||
1470 | #define PORT_EN 0x0001 /* PPI Port Enable */ | ||
1471 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | ||
1472 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | ||
1473 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | ||
1474 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | ||
1475 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | ||
1476 | #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ | ||
1477 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | ||
1478 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | ||
1479 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | ||
1480 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | ||
1481 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | ||
1482 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | ||
1483 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | ||
1484 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | ||
1485 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | ||
1486 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | ||
1487 | #define DLENGTH 0x3800 /* PPI Data Length */ | ||
1488 | #define POLC 0x4000 /* PPI Clock Polarity */ | ||
1489 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | ||
1490 | |||
1491 | /* PPI_STATUS Masks */ | ||
1492 | #define FLD 0x0400 /* Field Indicator */ | ||
1493 | #define FT_ERR 0x0800 /* Frame Track Error */ | ||
1494 | #define OVR 0x1000 /* FIFO Overflow Error */ | ||
1495 | #define UNDR 0x2000 /* FIFO Underrun Error */ | ||
1496 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | ||
1497 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | ||
1498 | |||
1499 | |||
1500 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
1501 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
1502 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
1503 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
1504 | |||
1505 | /* TWI_PRESCALE Masks */ | ||
1506 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
1507 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
1508 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
1509 | |||
1510 | /* TWI_SLAVE_CTRL Masks */ | ||
1511 | #define SEN 0x0001 /* Slave Enable */ | ||
1512 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
1513 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
1514 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
1515 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
1516 | |||
1517 | /* TWI_SLAVE_STAT Masks */ | ||
1518 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
1519 | #define GCALL 0x0002 /* General Call Indicator */ | ||
1520 | |||
1521 | /* TWI_MASTER_CTRL Masks */ | ||
1522 | #define MEN 0x0001 /* Master Mode Enable */ | ||
1523 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
1524 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
1525 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
1526 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
1527 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
1528 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
1529 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
1530 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
1531 | |||
1532 | /* TWI_MASTER_STAT Masks */ | ||
1533 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
1534 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
1535 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
1536 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
1537 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
1538 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
1539 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
1540 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
1541 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
1542 | |||
1543 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
1544 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
1545 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
1546 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
1547 | #define SOVF 0x0008 /* Slave Overflow */ | ||
1548 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
1549 | #define MERR 0x0020 /* Master Transfer Error */ | ||
1550 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
1551 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
1552 | |||
1553 | /* TWI_FIFO_CTRL Masks */ | ||
1554 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
1555 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
1556 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
1557 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
1558 | |||
1559 | /* TWI_FIFO_STAT Masks */ | ||
1560 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
1561 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
1562 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
1563 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
1564 | |||
1565 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
1566 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
1567 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
1568 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
1569 | |||
1570 | |||
1571 | /* Omit CAN masks from defBF534.h */ | ||
1572 | |||
1573 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | ||
1574 | /* PORT_MUX Masks */ | ||
1575 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | ||
1576 | #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ | ||
1577 | #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ | ||
1578 | |||
1579 | #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ | ||
1580 | #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ | ||
1581 | #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ | ||
1582 | #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ | ||
1583 | |||
1584 | #define PFDE 0x0008 /* Port F DMA Request Enable */ | ||
1585 | #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ | ||
1586 | #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ | ||
1587 | |||
1588 | #define PFTE 0x0010 /* Port F Timer Enable */ | ||
1589 | #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ | ||
1590 | #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ | ||
1591 | |||
1592 | #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ | ||
1593 | #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ | ||
1594 | #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ | ||
1595 | |||
1596 | #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ | ||
1597 | #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ | ||
1598 | #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ | ||
1599 | |||
1600 | #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ | ||
1601 | #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ | ||
1602 | #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ | ||
1603 | |||
1604 | #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ | ||
1605 | #define PFFE_TIMER 0x0000 /* Enable TMR2 */ | ||
1606 | #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ | ||
1607 | |||
1608 | #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ | ||
1609 | #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ | ||
1610 | #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ | ||
1611 | |||
1612 | #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ | ||
1613 | #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ | ||
1614 | #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ | ||
1615 | |||
1616 | #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ | ||
1617 | #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ | ||
1618 | #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ | ||
1619 | |||
1620 | |||
1621 | /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ | ||
1622 | /* HDMAx_CTL Masks */ | ||
1623 | #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ | ||
1624 | #define REP 0x0002 /* HDMA Request Polarity */ | ||
1625 | #define UTE 0x0004 /* Urgency Threshold Enable */ | ||
1626 | #define OIE 0x0010 /* Overflow Interrupt Enable */ | ||
1627 | #define BDIE 0x0020 /* Block Done Interrupt Enable */ | ||
1628 | #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ | ||
1629 | #define DRQ 0x0300 /* HDMA Request Type */ | ||
1630 | #define DRQ_NONE 0x0000 /* No Request */ | ||
1631 | #define DRQ_SINGLE 0x0100 /* Channels Request Single */ | ||
1632 | #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ | ||
1633 | #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ | ||
1634 | #define RBC 0x1000 /* Reload BCNT With IBCNT */ | ||
1635 | #define PS 0x2000 /* HDMA Pin Status */ | ||
1636 | #define OI 0x4000 /* Overflow Interrupt Generated */ | ||
1637 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | ||
1638 | |||
1639 | /* entry addresses of the user-callable Boot ROM functions */ | ||
1640 | |||
1641 | #define _BOOTROM_RESET 0xEF000000 | ||
1642 | #define _BOOTROM_FINAL_INIT 0xEF000002 | ||
1643 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | ||
1644 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | ||
1645 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | ||
1646 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | ||
1647 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | ||
1648 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | ||
1649 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | ||
1650 | |||
1651 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
1652 | #define PGDE_UART PFDE_UART | ||
1653 | #define PGDE_DMA PFDE_DMA | ||
1654 | #define CKELOW SCKELOW | ||
1655 | |||
1656 | /* ==== end from defBF534.h ==== */ | ||
1657 | |||
1658 | /* HOST Port Registers */ | ||
1659 | |||
1660 | #define HOST_CONTROL 0xffc03400 /* HOST Control Register */ | ||
1661 | #define HOST_STATUS 0xffc03404 /* HOST Status Register */ | ||
1662 | #define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ | ||
1663 | |||
1664 | /* Counter Registers */ | ||
1665 | |||
1666 | #define CNT_CONFIG 0xffc03500 /* Configuration Register */ | ||
1667 | #define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ | ||
1668 | #define CNT_STATUS 0xffc03508 /* Status Register */ | ||
1669 | #define CNT_COMMAND 0xffc0350c /* Command Register */ | ||
1670 | #define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ | ||
1671 | #define CNT_COUNTER 0xffc03514 /* Counter Register */ | ||
1672 | #define CNT_MAX 0xffc03518 /* Maximal Count Register */ | ||
1673 | #define CNT_MIN 0xffc0351c /* Minimal Count Register */ | ||
1674 | |||
1675 | /* OTP/FUSE Registers */ | ||
1676 | |||
1677 | #define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ | ||
1678 | #define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ | ||
1679 | #define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ | ||
1680 | #define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ | ||
1681 | |||
1682 | /* Security Registers */ | ||
1683 | |||
1684 | #define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ | ||
1685 | #define SECURE_CONTROL 0xffc03624 /* Secure Control */ | ||
1686 | #define SECURE_STATUS 0xffc03628 /* Secure Status */ | ||
1687 | |||
1688 | /* OTP Read/Write Data Buffer Registers */ | ||
1689 | |||
1690 | #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1691 | #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1692 | #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1693 | #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1694 | |||
1695 | /* NFC Registers */ | ||
1696 | |||
1697 | #define NFC_CTL 0xffc03700 /* NAND Control Register */ | ||
1698 | #define NFC_STAT 0xffc03704 /* NAND Status Register */ | ||
1699 | #define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */ | ||
1700 | #define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */ | ||
1701 | #define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */ | ||
1702 | #define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */ | ||
1703 | #define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */ | ||
1704 | #define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */ | ||
1705 | #define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */ | ||
1706 | #define NFC_RST 0xffc03724 /* NAND ECC Reset Register */ | ||
1707 | #define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */ | ||
1708 | #define NFC_READ 0xffc0372c /* NAND Read Data Register */ | ||
1709 | #define NFC_ADDR 0xffc03740 /* NAND Address Register */ | ||
1710 | #define NFC_CMD 0xffc03744 /* NAND Command Register */ | ||
1711 | #define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */ | ||
1712 | #define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */ | ||
1713 | |||
1714 | /* ********************************************************** */ | ||
1715 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
1716 | /* and MULTI BIT READ MACROS */ | ||
1717 | /* ********************************************************** */ | ||
1718 | |||
1719 | /* Bit masks for HOST_CONTROL */ | ||
1720 | |||
1721 | #define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ | ||
1722 | #define HOST_CNTR_nHOST_EN 0x0 | ||
1723 | #define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ | ||
1724 | #define HOST_CNTR_nHOST_END 0x0 | ||
1725 | #define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ | ||
1726 | #define HOST_CNTR_nDATA_SIZE 0x0 | ||
1727 | #define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ | ||
1728 | #define HOST_CNTR_nHOST_RST 0x0 | ||
1729 | #define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ | ||
1730 | #define HOST_CNTR_nHRDY_OVR 0x0 | ||
1731 | #define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ | ||
1732 | #define HOST_CNTR_nINT_MODE 0x0 | ||
1733 | #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ | ||
1734 | #define HOST_CNTR_ nBT_EN 0x0 | ||
1735 | #define HOST_CNTR_EHW 0x100 /* Enable Host Write */ | ||
1736 | #define HOST_CNTR_nEHW 0x0 | ||
1737 | #define HOST_CNTR_EHR 0x200 /* Enable Host Read */ | ||
1738 | #define HOST_CNTR_nEHR 0x0 | ||
1739 | #define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ | ||
1740 | #define HOST_CNTR_nBDR 0x0 | ||
1741 | |||
1742 | /* Bit masks for HOST_STATUS */ | ||
1743 | |||
1744 | #define HOST_STAT_READY 0x1 /* DMA Ready */ | ||
1745 | #define HOST_STAT_nREADY 0x0 | ||
1746 | #define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ | ||
1747 | #define HOST_STAT_nFIFOFULL 0x0 | ||
1748 | #define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ | ||
1749 | #define HOST_STAT_nFIFOEMPTY 0x0 | ||
1750 | #define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ | ||
1751 | #define HOST_STAT_nCOMPLETE 0x0 | ||
1752 | #define HOST_STAT_HSHK 0x10 /* Host Handshake */ | ||
1753 | #define HOST_STAT_nHSHK 0x0 | ||
1754 | #define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ | ||
1755 | #define HOST_STAT_nTIMEOUT 0x0 | ||
1756 | #define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ | ||
1757 | #define HOST_STAT_nHIRQ 0x0 | ||
1758 | #define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
1759 | #define HOST_STAT_nALLOW_CNFG 0x0 | ||
1760 | #define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ | ||
1761 | #define HOST_STAT_nDMA_DIR 0x0 | ||
1762 | #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ | ||
1763 | #define HOST_STAT_nBTE 0x0 | ||
1764 | #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ | ||
1765 | #define HOST_STAT_nHOSTRD_DONE 0x0 | ||
1766 | |||
1767 | /* Bit masks for HOST_TIMEOUT */ | ||
1768 | |||
1769 | #define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
1770 | |||
1771 | /* Bit masks for CNT_CONFIG */ | ||
1772 | |||
1773 | #define CNTE 0x1 /* Counter Enable */ | ||
1774 | #define nCNTE 0x0 | ||
1775 | #define DEBE 0x2 /* Debounce Enable */ | ||
1776 | #define nDEBE 0x0 | ||
1777 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ | ||
1778 | #define nCDGINV 0x0 | ||
1779 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ | ||
1780 | #define nCUDINV 0x0 | ||
1781 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ | ||
1782 | #define nCZMINV 0x0 | ||
1783 | #define CNTMODE 0x700 /* Counter Operating Mode */ | ||
1784 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ | ||
1785 | #define nZMZC 0x0 | ||
1786 | #define BNDMODE 0x3000 /* Boundary register Mode */ | ||
1787 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ | ||
1788 | #define nINPDIS 0x0 | ||
1789 | |||
1790 | /* Bit masks for CNT_IMASK */ | ||
1791 | |||
1792 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ | ||
1793 | #define nICIE 0x0 | ||
1794 | #define UCIE 0x2 /* Up count Interrupt Enable */ | ||
1795 | #define nUCIE 0x0 | ||
1796 | #define DCIE 0x4 /* Down count Interrupt Enable */ | ||
1797 | #define nDCIE 0x0 | ||
1798 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ | ||
1799 | #define nMINCIE 0x0 | ||
1800 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ | ||
1801 | #define nMAXCIE 0x0 | ||
1802 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ | ||
1803 | #define nCOV31IE 0x0 | ||
1804 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ | ||
1805 | #define nCOV15IE 0x0 | ||
1806 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ | ||
1807 | #define nCZEROIE 0x0 | ||
1808 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ | ||
1809 | #define nCZMIE 0x0 | ||
1810 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ | ||
1811 | #define nCZMEIE 0x0 | ||
1812 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ | ||
1813 | #define nCZMZIE 0x0 | ||
1814 | |||
1815 | /* Bit masks for CNT_STATUS */ | ||
1816 | |||
1817 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ | ||
1818 | #define nICII 0x0 | ||
1819 | #define UCII 0x2 /* Up count Interrupt Identifier */ | ||
1820 | #define nUCII 0x0 | ||
1821 | #define DCII 0x4 /* Down count Interrupt Identifier */ | ||
1822 | #define nDCII 0x0 | ||
1823 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ | ||
1824 | #define nMINCII 0x0 | ||
1825 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ | ||
1826 | #define nMAXCII 0x0 | ||
1827 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ | ||
1828 | #define nCOV31II 0x0 | ||
1829 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ | ||
1830 | #define nCOV15II 0x0 | ||
1831 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ | ||
1832 | #define nCZEROII 0x0 | ||
1833 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ | ||
1834 | #define nCZMII 0x0 | ||
1835 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ | ||
1836 | #define nCZMEII 0x0 | ||
1837 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ | ||
1838 | #define nCZMZII 0x0 | ||
1839 | |||
1840 | /* Bit masks for CNT_COMMAND */ | ||
1841 | |||
1842 | #define W1LCNT 0xf /* Load Counter Register */ | ||
1843 | #define W1LMIN 0xf0 /* Load Min Register */ | ||
1844 | #define W1LMAX 0xf00 /* Load Max Register */ | ||
1845 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ | ||
1846 | #define nW1ZMONCE 0x0 | ||
1847 | |||
1848 | /* Bit masks for CNT_DEBOUNCE */ | ||
1849 | |||
1850 | #define DPRESCALE 0xf /* Load Counter Register */ | ||
1851 | |||
1852 | /* Bit masks for OTP_CONTROL */ | ||
1853 | |||
1854 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ | ||
1855 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ | ||
1856 | #define nFIEN 0x0 | ||
1857 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ | ||
1858 | #define nFTESTDEC 0x0 | ||
1859 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ | ||
1860 | #define nFWRTEST 0x0 | ||
1861 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ | ||
1862 | #define nFRDEN 0x0 | ||
1863 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ | ||
1864 | #define nFWREN 0x0 | ||
1865 | |||
1866 | /* Bit masks for OTP_BEN */ | ||
1867 | |||
1868 | #define FBEN 0xffff /* OTP/Fuse Byte Enable */ | ||
1869 | |||
1870 | /* Bit masks for OTP_STATUS */ | ||
1871 | |||
1872 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ | ||
1873 | #define nFCOMP 0x0 | ||
1874 | #define FERROR 0x2 /* OTP/Fuse Access Error */ | ||
1875 | #define nFERROR 0x0 | ||
1876 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ | ||
1877 | #define nMMRGLOAD 0x0 | ||
1878 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ | ||
1879 | #define nMMRGLOCK 0x0 | ||
1880 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ | ||
1881 | #define nFPGMEN 0x0 | ||
1882 | |||
1883 | /* Bit masks for OTP_TIMING */ | ||
1884 | |||
1885 | #define USECDIV 0xff /* Micro Second Divider */ | ||
1886 | #define READACC 0x7f00 /* Read Access Time */ | ||
1887 | #define CPUMPRL 0x38000 /* Charge Pump Release Time */ | ||
1888 | #define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ | ||
1889 | #define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ | ||
1890 | #define PGMTIME 0xff000000 /* Program Time */ | ||
1891 | |||
1892 | /* Bit masks for SECURE_SYSSWT */ | ||
1893 | |||
1894 | #define EMUDABL 0x1 /* Emulation Disable. */ | ||
1895 | #define nEMUDABL 0x0 | ||
1896 | #define RSTDABL 0x2 /* Reset Disable */ | ||
1897 | #define nRSTDABL 0x0 | ||
1898 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | ||
1899 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | ||
1900 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | ||
1901 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | ||
1902 | #define nDMA0OVR 0x0 | ||
1903 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | ||
1904 | #define nDMA1OVR 0x0 | ||
1905 | #define EMUOVR 0x4000 /* Emulation Override */ | ||
1906 | #define nEMUOVR 0x0 | ||
1907 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | ||
1908 | #define nOTPSEN 0x0 | ||
1909 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | ||
1910 | |||
1911 | /* Bit masks for SECURE_CONTROL */ | ||
1912 | |||
1913 | #define SECURE0 0x1 /* SECURE 0 */ | ||
1914 | #define nSECURE0 0x0 | ||
1915 | #define SECURE1 0x2 /* SECURE 1 */ | ||
1916 | #define nSECURE1 0x0 | ||
1917 | #define SECURE2 0x4 /* SECURE 2 */ | ||
1918 | #define nSECURE2 0x0 | ||
1919 | #define SECURE3 0x8 /* SECURE 3 */ | ||
1920 | #define nSECURE3 0x0 | ||
1921 | |||
1922 | /* Bit masks for SECURE_STATUS */ | ||
1923 | |||
1924 | #define SECMODE 0x3 /* Secured Mode Control State */ | ||
1925 | #define NMI 0x4 /* Non Maskable Interrupt */ | ||
1926 | #define nNMI 0x0 | ||
1927 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | ||
1928 | #define nAFVALID 0x0 | ||
1929 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | ||
1930 | #define nAFEXIT 0x0 | ||
1931 | #define SECSTAT 0xe0 /* Secure Status */ | ||
1932 | |||
1933 | /* Bit masks for NFC_CTL */ | ||
1934 | |||
1935 | #define WR_DLY 0xf /* Write Strobe Delay */ | ||
1936 | #define RD_DLY 0xf0 /* Read Strobe Delay */ | ||
1937 | #define NWIDTH 0x100 /* NAND Data Width */ | ||
1938 | #define nNWIDTH 0x0 | ||
1939 | #define PG_SIZE 0x200 /* Page Size */ | ||
1940 | #define nPG_SIZE 0x0 | ||
1941 | |||
1942 | /* Bit masks for NFC_STAT */ | ||
1943 | |||
1944 | #define NBUSY 0x1 /* Not Busy */ | ||
1945 | #define nNBUSY 0x0 | ||
1946 | #define WB_FULL 0x2 /* Write Buffer Full */ | ||
1947 | #define nWB_FULL 0x0 | ||
1948 | #define PG_WR_STAT 0x4 /* Page Write Pending */ | ||
1949 | #define nPG_WR_STAT 0x0 | ||
1950 | #define PG_RD_STAT 0x8 /* Page Read Pending */ | ||
1951 | #define nPG_RD_STAT 0x0 | ||
1952 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | ||
1953 | #define nWB_EMPTY 0x0 | ||
1954 | |||
1955 | /* Bit masks for NFC_IRQSTAT */ | ||
1956 | |||
1957 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ | ||
1958 | #define nNBUSYIRQ 0x0 | ||
1959 | #define WB_OVF 0x2 /* Write Buffer Overflow */ | ||
1960 | #define nWB_OVF 0x0 | ||
1961 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ | ||
1962 | #define nWB_EDGE 0x0 | ||
1963 | #define RD_RDY 0x8 /* Read Data Ready */ | ||
1964 | #define nRD_RDY 0x0 | ||
1965 | #define WR_DONE 0x10 /* Page Write Done */ | ||
1966 | #define nWR_DONE 0x0 | ||
1967 | |||
1968 | /* Bit masks for NFC_IRQMASK */ | ||
1969 | |||
1970 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ | ||
1971 | #define nMASK_BUSYIRQ 0x0 | ||
1972 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ | ||
1973 | #define nMASK_WBOVF 0x0 | ||
1974 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ | ||
1975 | #define nMASK_WBEMPTY 0x0 | ||
1976 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ | ||
1977 | #define nMASK_RDRDY 0x0 | ||
1978 | #define MASK_WRDONE 0x10 /* Mask Write Done */ | ||
1979 | #define nMASK_WRDONE 0x0 | ||
1980 | |||
1981 | /* Bit masks for NFC_RST */ | ||
1982 | |||
1983 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ | ||
1984 | #define nECC_RST 0x0 | ||
1985 | |||
1986 | /* Bit masks for NFC_PGCTL */ | ||
1987 | |||
1988 | #define PG_RD_START 0x1 /* Page Read Start */ | ||
1989 | #define nPG_RD_START 0x0 | ||
1990 | #define PG_WR_START 0x2 /* Page Write Start */ | ||
1991 | #define nPG_WR_START 0x0 | ||
1992 | |||
1993 | /* Bit masks for NFC_ECC0 */ | ||
1994 | |||
1995 | #define ECC0 0x7ff /* Parity Calculation Result0 */ | ||
1996 | |||
1997 | /* Bit masks for NFC_ECC1 */ | ||
1998 | |||
1999 | #define ECC1 0x7ff /* Parity Calculation Result1 */ | ||
2000 | |||
2001 | /* Bit masks for NFC_ECC2 */ | ||
2002 | |||
2003 | #define ECC2 0x7ff /* Parity Calculation Result2 */ | ||
2004 | |||
2005 | /* Bit masks for NFC_ECC3 */ | ||
2006 | |||
2007 | #define ECC3 0x7ff /* Parity Calculation Result3 */ | ||
2008 | |||
2009 | /* Bit masks for NFC_COUNT */ | ||
2010 | |||
2011 | #define ECCCNT 0x3ff /* Transfer Count */ | ||
2012 | |||
2013 | |||
2014 | #endif /* _DEF_BF52X_H */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h new file mode 100644 index 000000000000..49dd693223e8 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/dma.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * file: include/asm-blackfin/mach-bf527/dma.h | ||
3 | * based on: include/asm-blackfin/mach-bf537/dma.h | ||
4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
5 | * | ||
6 | * created: | ||
7 | * description: | ||
8 | * system DMA map | ||
9 | * rev: | ||
10 | * | ||
11 | * modified: | ||
12 | * | ||
13 | * | ||
14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * this program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the gnu general public license as published by | ||
18 | * the free software foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * this program is distributed in the hope that it will be useful, | ||
22 | * but without any warranty; without even the implied warranty of | ||
23 | * merchantability or fitness for a particular purpose. see the | ||
24 | * gnu general public license for more details. | ||
25 | * | ||
26 | * you should have received a copy of the gnu general public license | ||
27 | * along with this program; see the file copying. | ||
28 | * if not, write to the free software foundation, | ||
29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
30 | */ | ||
31 | |||
32 | #ifndef _MACH_DMA_H_ | ||
33 | #define _MACH_DMA_H_ | ||
34 | |||
35 | #define MAX_BLACKFIN_DMA_CHANNEL 16 | ||
36 | |||
37 | #define CH_PPI 0 /* PPI receive/transmit or NFC */ | ||
38 | #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ | ||
39 | #define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ | ||
40 | #define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ | ||
41 | #define CH_SPORT0_RX 3 /* SPORT0 receive */ | ||
42 | #define CH_SPORT0_TX 4 /* SPORT0 transmit */ | ||
43 | #define CH_SPORT1_RX 5 /* SPORT1 receive */ | ||
44 | #define CH_SPORT1_TX 6 /* SPORT1 transmit */ | ||
45 | #define CH_SPI 7 /* SPI transmit/receive */ | ||
46 | #define CH_UART0_RX 8 /* UART0 receive */ | ||
47 | #define CH_UART0_TX 9 /* UART0 transmit */ | ||
48 | #define CH_UART1_RX 10 /* UART1 receive */ | ||
49 | #define CH_UART1_TX 11 /* UART1 transmit */ | ||
50 | |||
51 | #define CH_MEM_STREAM0_DEST 12 /* TX */ | ||
52 | #define CH_MEM_STREAM0_SRC 13 /* RX */ | ||
53 | #define CH_MEM_STREAM1_DEST 14 /* TX */ | ||
54 | #define CH_MEM_STREAM1_SRC 15 /* RX */ | ||
55 | |||
56 | #if defined(CONFIG_BF527_NAND_D_PORTF) | ||
57 | #define CH_NFC CH_PPI /* PPI receive/transmit or NFC */ | ||
58 | #elif defined(CONFIG_BF527_NAND_D_PORTH) | ||
59 | #define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ | ||
60 | #endif | ||
61 | |||
62 | #endif | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h new file mode 100644 index 000000000000..4e2b3f2020e5 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/irq.h | |||
@@ -0,0 +1,259 @@ | |||
1 | /* | ||
2 | * file: include/asm-blackfin/mach-bf527/irq.h | ||
3 | * based on: include/asm-blackfin/mach-bf537/irq.h | ||
4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
5 | * | ||
6 | * created: | ||
7 | * description: | ||
8 | * system mmr register map | ||
9 | * rev: | ||
10 | * | ||
11 | * modified: | ||
12 | * | ||
13 | * | ||
14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * this program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the gnu general public license as published by | ||
18 | * the free software foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * this program is distributed in the hope that it will be useful, | ||
22 | * but without any warranty; without even the implied warranty of | ||
23 | * merchantability or fitness for a particular purpose. see the | ||
24 | * gnu general public license for more details. | ||
25 | * | ||
26 | * you should have received a copy of the gnu general public license | ||
27 | * along with this program; see the file copying. | ||
28 | * if not, write to the free software foundation, | ||
29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
30 | */ | ||
31 | |||
32 | #ifndef _BF527_IRQ_H_ | ||
33 | #define _BF527_IRQ_H_ | ||
34 | |||
35 | /* | ||
36 | * Interrupt source definitions | ||
37 | Event Source Core Event Name | ||
38 | Core Emulation ** | ||
39 | Events (highest priority) EMU 0 | ||
40 | Reset RST 1 | ||
41 | NMI NMI 2 | ||
42 | Exception EVX 3 | ||
43 | Reserved -- 4 | ||
44 | Hardware Error IVHW 5 | ||
45 | Core Timer IVTMR 6 * | ||
46 | |||
47 | ..... | ||
48 | |||
49 | Software Interrupt 1 IVG14 31 | ||
50 | Software Interrupt 2 -- | ||
51 | (lowest priority) IVG15 32 * | ||
52 | */ | ||
53 | |||
54 | #define NR_PERI_INTS (2 * 32) | ||
55 | |||
56 | /* The ABSTRACT IRQ definitions */ | ||
57 | /** the first seven of the following are fixed, the rest you change if you need to **/ | ||
58 | #define IRQ_EMU 0 /* Emulation */ | ||
59 | #define IRQ_RST 1 /* reset */ | ||
60 | #define IRQ_NMI 2 /* Non Maskable */ | ||
61 | #define IRQ_EVX 3 /* Exception */ | ||
62 | #define IRQ_UNUSED 4 /* - unused interrupt */ | ||
63 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
64 | #define IRQ_CORETMR 6 /* Core timer */ | ||
65 | |||
66 | #define BFIN_IRQ(x) ((x) + 7) | ||
67 | |||
68 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ | ||
69 | #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ | ||
70 | #define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ | ||
71 | #define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ | ||
72 | #define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ | ||
73 | #define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ | ||
74 | #define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ | ||
75 | #define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ | ||
76 | #define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ | ||
77 | #define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ | ||
78 | #define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ | ||
79 | #define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ | ||
80 | #define IRQ_RTC BFIN_IRQ(14) /* RTC */ | ||
81 | #define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ | ||
82 | #define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ | ||
83 | #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ | ||
84 | #define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ | ||
85 | #define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ | ||
86 | #define IRQ_TWI BFIN_IRQ(20) /* TWI */ | ||
87 | #define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ | ||
88 | #define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ | ||
89 | #define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ | ||
90 | #define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ | ||
91 | #define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ | ||
92 | #define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ | ||
93 | #define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ | ||
94 | #define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ | ||
95 | #define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ | ||
96 | #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ | ||
97 | #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ | ||
98 | #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ | ||
99 | #define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ | ||
100 | #define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ | ||
101 | #define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ | ||
102 | #define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ | ||
103 | #define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ | ||
104 | #define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ | ||
105 | #define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ | ||
106 | #define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ | ||
107 | #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ | ||
108 | #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ | ||
109 | #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ | ||
110 | #define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ | ||
111 | #define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ | ||
112 | #define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ | ||
113 | #define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ | ||
114 | #define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */ | ||
115 | #define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */ | ||
116 | #define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */ | ||
117 | #define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */ | ||
118 | #define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */ | ||
119 | #define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */ | ||
120 | #define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */ | ||
121 | #define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ | ||
122 | #define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ | ||
123 | |||
124 | #define SYS_IRQS BFIN_IRQ(63) /* 70 */ | ||
125 | |||
126 | #define IRQ_PF0 71 | ||
127 | #define IRQ_PF1 72 | ||
128 | #define IRQ_PF2 73 | ||
129 | #define IRQ_PF3 74 | ||
130 | #define IRQ_PF4 75 | ||
131 | #define IRQ_PF5 76 | ||
132 | #define IRQ_PF6 77 | ||
133 | #define IRQ_PF7 78 | ||
134 | #define IRQ_PF8 79 | ||
135 | #define IRQ_PF9 80 | ||
136 | #define IRQ_PF10 81 | ||
137 | #define IRQ_PF11 82 | ||
138 | #define IRQ_PF12 83 | ||
139 | #define IRQ_PF13 84 | ||
140 | #define IRQ_PF14 85 | ||
141 | #define IRQ_PF15 86 | ||
142 | |||
143 | #define IRQ_PG0 87 | ||
144 | #define IRQ_PG1 88 | ||
145 | #define IRQ_PG2 89 | ||
146 | #define IRQ_PG3 90 | ||
147 | #define IRQ_PG4 91 | ||
148 | #define IRQ_PG5 92 | ||
149 | #define IRQ_PG6 93 | ||
150 | #define IRQ_PG7 94 | ||
151 | #define IRQ_PG8 95 | ||
152 | #define IRQ_PG9 96 | ||
153 | #define IRQ_PG10 97 | ||
154 | #define IRQ_PG11 98 | ||
155 | #define IRQ_PG12 99 | ||
156 | #define IRQ_PG13 100 | ||
157 | #define IRQ_PG14 101 | ||
158 | #define IRQ_PG15 102 | ||
159 | |||
160 | #define IRQ_PH0 103 | ||
161 | #define IRQ_PH1 104 | ||
162 | #define IRQ_PH2 105 | ||
163 | #define IRQ_PH3 106 | ||
164 | #define IRQ_PH4 107 | ||
165 | #define IRQ_PH5 108 | ||
166 | #define IRQ_PH6 109 | ||
167 | #define IRQ_PH7 110 | ||
168 | #define IRQ_PH8 111 | ||
169 | #define IRQ_PH9 112 | ||
170 | #define IRQ_PH10 113 | ||
171 | #define IRQ_PH11 114 | ||
172 | #define IRQ_PH12 115 | ||
173 | #define IRQ_PH13 116 | ||
174 | #define IRQ_PH14 117 | ||
175 | #define IRQ_PH15 118 | ||
176 | |||
177 | #define GPIO_IRQ_BASE IRQ_PF0 | ||
178 | |||
179 | #define NR_IRQS (IRQ_PH15+1) | ||
180 | |||
181 | #define IVG7 7 | ||
182 | #define IVG8 8 | ||
183 | #define IVG9 9 | ||
184 | #define IVG10 10 | ||
185 | #define IVG11 11 | ||
186 | #define IVG12 12 | ||
187 | #define IVG13 13 | ||
188 | #define IVG14 14 | ||
189 | #define IVG15 15 | ||
190 | |||
191 | /* IAR0 BIT FIELDS */ | ||
192 | #define IRQ_PLL_WAKEUP_POS 0 | ||
193 | #define IRQ_DMA0_ERROR_POS 4 | ||
194 | #define IRQ_DMAR0_BLK_POS 8 | ||
195 | #define IRQ_DMAR1_BLK_POS 12 | ||
196 | #define IRQ_DMAR0_OVR_POS 16 | ||
197 | #define IRQ_DMAR1_OVR_POS 20 | ||
198 | #define IRQ_PPI_ERROR_POS 24 | ||
199 | #define IRQ_MAC_ERROR_POS 28 | ||
200 | |||
201 | /* IAR1 BIT FIELDS */ | ||
202 | #define IRQ_SPORT0_ERROR_POS 0 | ||
203 | #define IRQ_SPORT1_ERROR_POS 4 | ||
204 | #define IRQ_UART0_ERROR_POS 16 | ||
205 | #define IRQ_UART1_ERROR_POS 20 | ||
206 | #define IRQ_RTC_POS 24 | ||
207 | #define IRQ_PPI_POS 28 | ||
208 | |||
209 | /* IAR2 BIT FIELDS */ | ||
210 | #define IRQ_SPORT0_RX_POS 0 | ||
211 | #define IRQ_SPORT0_TX_POS 4 | ||
212 | #define IRQ_SPORT1_RX_POS 8 | ||
213 | #define IRQ_SPORT1_TX_POS 12 | ||
214 | #define IRQ_TWI_POS 16 | ||
215 | #define IRQ_SPI_POS 20 | ||
216 | #define IRQ_UART0_RX_POS 24 | ||
217 | #define IRQ_UART0_TX_POS 28 | ||
218 | |||
219 | /* IAR3 BIT FIELDS */ | ||
220 | #define IRQ_UART1_RX_POS 0 | ||
221 | #define IRQ_UART1_TX_POS 4 | ||
222 | #define IRQ_OPTSEC_POS 8 | ||
223 | #define IRQ_CNT_POS 12 | ||
224 | #define IRQ_MAC_RX_POS 16 | ||
225 | #define IRQ_PORTH_INTA_POS 20 | ||
226 | #define IRQ_MAC_TX_POS 24 | ||
227 | #define IRQ_PORTH_INTB_POS 28 | ||
228 | |||
229 | /* IAR4 BIT FIELDS */ | ||
230 | #define IRQ_TMR0_POS 0 | ||
231 | #define IRQ_TMR1_POS 4 | ||
232 | #define IRQ_TMR2_POS 8 | ||
233 | #define IRQ_TMR3_POS 12 | ||
234 | #define IRQ_TMR4_POS 16 | ||
235 | #define IRQ_TMR5_POS 20 | ||
236 | #define IRQ_TMR6_POS 24 | ||
237 | #define IRQ_TMR7_POS 28 | ||
238 | |||
239 | /* IAR5 BIT FIELDS */ | ||
240 | #define IRQ_PORTG_INTA_POS 0 | ||
241 | #define IRQ_PORTG_INTB_POS 4 | ||
242 | #define IRQ_MEM_DMA0_POS 8 | ||
243 | #define IRQ_MEM_DMA1_POS 12 | ||
244 | #define IRQ_WATCH_POS 16 | ||
245 | #define IRQ_PORTF_INTA_POS 20 | ||
246 | #define IRQ_PORTF_INTB_POS 24 | ||
247 | #define IRQ_SPI_ERROR_POS 28 | ||
248 | |||
249 | /* IAR6 BIT FIELDS */ | ||
250 | #define IRQ_NFC_ERROR_POS 0 | ||
251 | #define IRQ_HDMA_ERROR_POS 4 | ||
252 | #define IRQ_HDMA_POS 8 | ||
253 | #define IRQ_USB_EINT_POS 12 | ||
254 | #define IRQ_USB_INT0_POS 16 | ||
255 | #define IRQ_USB_INT1_POS 20 | ||
256 | #define IRQ_USB_INT2_POS 24 | ||
257 | #define IRQ_USB_DMA_POS 28 | ||
258 | |||
259 | #endif /* _BF527_IRQ_H_ */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_init.h b/arch/blackfin/mach-bf527/include/mach/mem_init.h new file mode 100644 index 000000000000..cbe03f4a5698 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/mem_init.h | |||
@@ -0,0 +1,310 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/mem_init.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * Copyright 2004-2007 Analog Devices Inc. | ||
13 | * | ||
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License as published by | ||
18 | * the Free Software Foundation; either version 2, or (at your option) | ||
19 | * any later version. | ||
20 | * | ||
21 | * This program is distributed in the hope that it will be useful, | ||
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
24 | * GNU General Public License for more details. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License | ||
27 | * along with this program; see the file COPYING. | ||
28 | * If not, write to the Free Software Foundation, | ||
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
30 | */ | ||
31 | |||
32 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75) | ||
33 | #if (CONFIG_SCLK_HZ > 119402985) | ||
34 | #define SDRAM_tRP TRP_2 | ||
35 | #define SDRAM_tRP_num 2 | ||
36 | #define SDRAM_tRAS TRAS_7 | ||
37 | #define SDRAM_tRAS_num 7 | ||
38 | #define SDRAM_tRCD TRCD_2 | ||
39 | #define SDRAM_tWR TWR_2 | ||
40 | #endif | ||
41 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
42 | #define SDRAM_tRP TRP_2 | ||
43 | #define SDRAM_tRP_num 2 | ||
44 | #define SDRAM_tRAS TRAS_6 | ||
45 | #define SDRAM_tRAS_num 6 | ||
46 | #define SDRAM_tRCD TRCD_2 | ||
47 | #define SDRAM_tWR TWR_2 | ||
48 | #endif | ||
49 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
50 | #define SDRAM_tRP TRP_2 | ||
51 | #define SDRAM_tRP_num 2 | ||
52 | #define SDRAM_tRAS TRAS_5 | ||
53 | #define SDRAM_tRAS_num 5 | ||
54 | #define SDRAM_tRCD TRCD_2 | ||
55 | #define SDRAM_tWR TWR_2 | ||
56 | #endif | ||
57 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
58 | #define SDRAM_tRP TRP_2 | ||
59 | #define SDRAM_tRP_num 2 | ||
60 | #define SDRAM_tRAS TRAS_4 | ||
61 | #define SDRAM_tRAS_num 4 | ||
62 | #define SDRAM_tRCD TRCD_2 | ||
63 | #define SDRAM_tWR TWR_2 | ||
64 | #endif | ||
65 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
66 | #define SDRAM_tRP TRP_2 | ||
67 | #define SDRAM_tRP_num 2 | ||
68 | #define SDRAM_tRAS TRAS_3 | ||
69 | #define SDRAM_tRAS_num 3 | ||
70 | #define SDRAM_tRCD TRCD_2 | ||
71 | #define SDRAM_tWR TWR_2 | ||
72 | #endif | ||
73 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
74 | #define SDRAM_tRP TRP_1 | ||
75 | #define SDRAM_tRP_num 1 | ||
76 | #define SDRAM_tRAS TRAS_4 | ||
77 | #define SDRAM_tRAS_num 3 | ||
78 | #define SDRAM_tRCD TRCD_1 | ||
79 | #define SDRAM_tWR TWR_2 | ||
80 | #endif | ||
81 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
82 | #define SDRAM_tRP TRP_1 | ||
83 | #define SDRAM_tRP_num 1 | ||
84 | #define SDRAM_tRAS TRAS_3 | ||
85 | #define SDRAM_tRAS_num 3 | ||
86 | #define SDRAM_tRCD TRCD_1 | ||
87 | #define SDRAM_tWR TWR_2 | ||
88 | #endif | ||
89 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
90 | #define SDRAM_tRP TRP_1 | ||
91 | #define SDRAM_tRP_num 1 | ||
92 | #define SDRAM_tRAS TRAS_2 | ||
93 | #define SDRAM_tRAS_num 2 | ||
94 | #define SDRAM_tRCD TRCD_1 | ||
95 | #define SDRAM_tWR TWR_2 | ||
96 | #endif | ||
97 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
98 | #define SDRAM_tRP TRP_1 | ||
99 | #define SDRAM_tRP_num 1 | ||
100 | #define SDRAM_tRAS TRAS_1 | ||
101 | #define SDRAM_tRAS_num 1 | ||
102 | #define SDRAM_tRCD TRCD_1 | ||
103 | #define SDRAM_tWR TWR_2 | ||
104 | #endif | ||
105 | #endif | ||
106 | |||
107 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | ||
108 | /*SDRAM INFORMATION: */ | ||
109 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
110 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
111 | #define SDRAM_CL CL_3 | ||
112 | #endif | ||
113 | |||
114 | #if (CONFIG_MEM_MT48LC16M8A2TG_75) | ||
115 | /*SDRAM INFORMATION: */ | ||
116 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
117 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | ||
118 | #define SDRAM_CL CL_3 | ||
119 | #endif | ||
120 | |||
121 | #if (CONFIG_MEM_MT48LC32M8A2_75) | ||
122 | /*SDRAM INFORMATION: */ | ||
123 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
124 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
125 | #define SDRAM_CL CL_3 | ||
126 | #endif | ||
127 | |||
128 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | ||
129 | /*SDRAM INFORMATION: */ | ||
130 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
131 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
132 | #define SDRAM_CL CL_3 | ||
133 | #endif | ||
134 | |||
135 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
136 | /*SDRAM INFORMATION: Modify this for your board */ | ||
137 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
138 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
139 | #define SDRAM_CL CL_3 | ||
140 | #endif | ||
141 | |||
142 | #if (CONFIG_MEM_MT48LC32M16A2TG_75) | ||
143 | /*SDRAM INFORMATION: */ | ||
144 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
145 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
146 | #define SDRAM_CL CL_3 | ||
147 | #endif | ||
148 | |||
149 | /* Equation from section 17 (p17-46) of BF533 HRM */ | ||
150 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | ||
151 | |||
152 | /* Enable SCLK Out */ | ||
153 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
154 | |||
155 | #if defined CONFIG_CLKIN_HALF | ||
156 | #define CLKIN_HALF 1 | ||
157 | #else | ||
158 | #define CLKIN_HALF 0 | ||
159 | #endif | ||
160 | |||
161 | #if defined CONFIG_PLL_BYPASS | ||
162 | #define PLL_BYPASS 1 | ||
163 | #else | ||
164 | #define PLL_BYPASS 0 | ||
165 | #endif | ||
166 | |||
167 | /***************************************Currently Not Being Used *********************************/ | ||
168 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
169 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
170 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
171 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
172 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
173 | |||
174 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
175 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
176 | #endif | ||
177 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
178 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
179 | #endif | ||
180 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
181 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
182 | #endif | ||
183 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
184 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
185 | #endif | ||
186 | |||
187 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
188 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
189 | #endif | ||
190 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
191 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
192 | #endif | ||
193 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
194 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
195 | #endif | ||
196 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
197 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
198 | #endif | ||
199 | |||
200 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
201 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
202 | #endif | ||
203 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
204 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
205 | #endif | ||
206 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
207 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
208 | #endif | ||
209 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
210 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
211 | #endif | ||
212 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
213 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
214 | #endif | ||
215 | |||
216 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
217 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
218 | #endif | ||
219 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
220 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
221 | #endif | ||
222 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
223 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
224 | #endif | ||
225 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
226 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
227 | #endif | ||
228 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
229 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
230 | #endif | ||
231 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
232 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
233 | #endif | ||
234 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
235 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
236 | #endif | ||
237 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
238 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
239 | #endif | ||
240 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
241 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
242 | #endif | ||
243 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
244 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
245 | #endif | ||
246 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
247 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
248 | #endif | ||
249 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
250 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
251 | #endif | ||
252 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
253 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
254 | #endif | ||
255 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
256 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
257 | #endif | ||
258 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
259 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
260 | #endif | ||
261 | |||
262 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
263 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
264 | #endif | ||
265 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
266 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
267 | #endif | ||
268 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
269 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
270 | #endif | ||
271 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
272 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
273 | #endif | ||
274 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
275 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
276 | #endif | ||
277 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
278 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
279 | #endif | ||
280 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
281 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
282 | #endif | ||
283 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
284 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
285 | #endif | ||
286 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
287 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
288 | #endif | ||
289 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
290 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
291 | #endif | ||
292 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
293 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
294 | #endif | ||
295 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
296 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
297 | #endif | ||
298 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
299 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
300 | #endif | ||
301 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
302 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
303 | #endif | ||
304 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
305 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
306 | #endif | ||
307 | |||
308 | #define flash_EBIU_AMBCTL0 \ | ||
309 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
310 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h new file mode 100644 index 000000000000..ef46dc991cd4 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h | |||
@@ -0,0 +1,102 @@ | |||
1 | /* | ||
2 | * file: include/asm-blackfin/mach-bf527/mem_map.h | ||
3 | * based on: include/asm-blackfin/mach-bf537/mem_map.h | ||
4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
5 | * | ||
6 | * created: | ||
7 | * description: | ||
8 | * Memory MAP Common header file for blackfin BF527/5/2 of processors. | ||
9 | * rev: | ||
10 | * | ||
11 | * modified: | ||
12 | * | ||
13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * this program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the gnu general public license as published by | ||
17 | * the free software foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * this program is distributed in the hope that it will be useful, | ||
21 | * but without any warranty; without even the implied warranty of | ||
22 | * merchantability or fitness for a particular purpose. see the | ||
23 | * gnu general public license for more details. | ||
24 | * | ||
25 | * you should have received a copy of the gnu general public license | ||
26 | * along with this program; see the file copying. | ||
27 | * if not, write to the free software foundation, | ||
28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
29 | */ | ||
30 | |||
31 | #ifndef _MEM_MAP_527_H_ | ||
32 | #define _MEM_MAP_527_H_ | ||
33 | |||
34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | ||
35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | ||
36 | |||
37 | /* Async Memory Banks */ | ||
38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | ||
39 | #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ | ||
40 | #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ | ||
41 | #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ | ||
42 | #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ | ||
43 | #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ | ||
44 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | ||
45 | #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ | ||
46 | |||
47 | /* Boot ROM Memory */ | ||
48 | |||
49 | #define BOOT_ROM_START 0xEF000000 | ||
50 | #define BOOT_ROM_LENGTH 0x8000 | ||
51 | |||
52 | /* Level 1 Memory */ | ||
53 | |||
54 | /* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */ | ||
55 | |||
56 | #ifdef CONFIG_BFIN_ICACHE | ||
57 | #define BFIN_ICACHESIZE (16*1024) | ||
58 | #else | ||
59 | #define BFIN_ICACHESIZE (0*1024) | ||
60 | #endif | ||
61 | |||
62 | #define L1_CODE_START 0xFFA00000 | ||
63 | #define L1_DATA_A_START 0xFF800000 | ||
64 | #define L1_DATA_B_START 0xFF900000 | ||
65 | |||
66 | #define L1_CODE_LENGTH 0xC000 | ||
67 | |||
68 | #ifdef CONFIG_BFIN_DCACHE | ||
69 | |||
70 | #ifdef CONFIG_BFIN_DCACHE_BANKA | ||
71 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | ||
72 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
73 | #define L1_DATA_B_LENGTH 0x8000 | ||
74 | #define BFIN_DCACHESIZE (16*1024) | ||
75 | #define BFIN_DSUPBANKS 1 | ||
76 | #else | ||
77 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | ||
78 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
79 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | ||
80 | #define BFIN_DCACHESIZE (32*1024) | ||
81 | #define BFIN_DSUPBANKS 2 | ||
82 | #endif | ||
83 | |||
84 | #else | ||
85 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | ||
86 | #define L1_DATA_A_LENGTH 0x8000 | ||
87 | #define L1_DATA_B_LENGTH 0x8000 | ||
88 | #define BFIN_DCACHESIZE (0*1024) | ||
89 | #define BFIN_DSUPBANKS 0 | ||
90 | #endif /*CONFIG_BFIN_DCACHE */ | ||
91 | |||
92 | /* Level 2 Memory - none */ | ||
93 | |||
94 | #define L2_START 0 | ||
95 | #define L2_LENGTH 0 | ||
96 | |||
97 | /* Scratch Pad Memory */ | ||
98 | |||
99 | #define L1_SCRATCH_START 0xFFB00000 | ||
100 | #define L1_SCRATCH_LENGTH 0x1000 | ||
101 | |||
102 | #endif /* _MEM_MAP_527_H_ */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h new file mode 100644 index 000000000000..ae4d205bfcf5 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/portmux.h | |||
@@ -0,0 +1,207 @@ | |||
1 | #ifndef _MACH_PORTMUX_H_ | ||
2 | #define _MACH_PORTMUX_H_ | ||
3 | |||
4 | #define MAX_RESOURCES MAX_BLACKFIN_GPIOS | ||
5 | |||
6 | #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) | ||
7 | #define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) | ||
8 | #define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) | ||
9 | #define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) | ||
10 | #define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) | ||
11 | #define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) | ||
12 | #define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) | ||
13 | #define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) | ||
14 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) | ||
15 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) | ||
16 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) | ||
17 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) | ||
18 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) | ||
19 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) | ||
20 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) | ||
21 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) | ||
22 | |||
23 | #if defined(CONFIG_BF527_SPORT0_PORTF) | ||
24 | #define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) | ||
25 | #define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) | ||
26 | #define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) | ||
27 | #define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) | ||
28 | #define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) | ||
29 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) | ||
30 | #define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) | ||
31 | #define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) | ||
32 | #elif defined(CONFIG_BF527_SPORT0_PORTG) | ||
33 | #define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) | ||
34 | #define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) | ||
35 | #define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) | ||
36 | #define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) | ||
37 | #define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) | ||
38 | #define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) | ||
39 | #if defined(CONFIG_BF527_SPORT0_TSCLK_PG10) | ||
40 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) | ||
41 | #elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14) | ||
42 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) | ||
43 | #endif | ||
44 | #define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) | ||
45 | #endif | ||
46 | |||
47 | #define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) | ||
48 | #define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) | ||
49 | #define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) | ||
50 | #define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) | ||
51 | #define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) | ||
52 | #define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) | ||
53 | #define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | ||
54 | #define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | ||
55 | |||
56 | #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) | ||
57 | #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) | ||
58 | |||
59 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) | ||
60 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) | ||
61 | |||
62 | #if defined(CONFIG_BF527_UART1_PORTF) | ||
63 | #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) | ||
64 | #define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) | ||
65 | #elif defined(CONFIG_BF527_UART1_PORTG) | ||
66 | #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) | ||
67 | #define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) | ||
68 | #endif | ||
69 | |||
70 | #define P_HWAIT (P_DONTCARE) | ||
71 | |||
72 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) | ||
73 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) | ||
74 | #define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) | ||
75 | #define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) | ||
76 | #define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) | ||
77 | #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) | ||
78 | #define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) | ||
79 | #define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) | ||
80 | #define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) | ||
81 | #define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) | ||
82 | #define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) | ||
83 | /* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */ | ||
84 | #define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) | ||
85 | #define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) | ||
86 | #define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) | ||
87 | #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) | ||
88 | #define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) | ||
89 | #define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) | ||
90 | #define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) | ||
91 | |||
92 | #define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) | ||
93 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) | ||
94 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) | ||
95 | |||
96 | #define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) | ||
97 | #define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) | ||
98 | #define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) | ||
99 | #define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) | ||
100 | #define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) | ||
101 | |||
102 | #if defined(CONFIG_BF527_NAND_D_PORTF) | ||
103 | #define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) | ||
104 | #define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) | ||
105 | #define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) | ||
106 | #define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) | ||
107 | #define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) | ||
108 | #define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) | ||
109 | #define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) | ||
110 | #define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) | ||
111 | #elif defined(CONFIG_BF527_NAND_D_PORTH) | ||
112 | #define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) | ||
113 | #define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) | ||
114 | #define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) | ||
115 | #define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) | ||
116 | #define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) | ||
117 | #define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) | ||
118 | #define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) | ||
119 | #define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) | ||
120 | #endif | ||
121 | |||
122 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) | ||
123 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) | ||
124 | #define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) | ||
125 | #define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) | ||
126 | #define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) | ||
127 | #define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) | ||
128 | #define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) | ||
129 | #define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) | ||
130 | |||
131 | #define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) | ||
132 | #define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) | ||
133 | #define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) | ||
134 | #define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) | ||
135 | #define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) | ||
136 | #define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2)) | ||
137 | #define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) | ||
138 | #define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) | ||
139 | #define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) | ||
140 | #define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2)) | ||
141 | #define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2)) | ||
142 | #define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2)) | ||
143 | #define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2)) | ||
144 | #define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2)) | ||
145 | #define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2)) | ||
146 | #define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2)) | ||
147 | |||
148 | #define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) | ||
149 | #define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) | ||
150 | #define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1)) | ||
151 | #define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1)) | ||
152 | #define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) | ||
153 | #define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) | ||
154 | #define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) | ||
155 | #define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) | ||
156 | #define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1)) | ||
157 | #define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1)) | ||
158 | #define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1)) | ||
159 | #define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1)) | ||
160 | #define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1)) | ||
161 | #define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) | ||
162 | #define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) | ||
163 | #define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) | ||
164 | #define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) | ||
165 | #define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) | ||
166 | |||
167 | #define P_TWI0_SCL (P_DONTCARE) | ||
168 | #define P_TWI0_SDA (P_DONTCARE) | ||
169 | #define P_PPI0_FS1 (P_DONTCARE) | ||
170 | #define P_TMR0 (P_DONTCARE) | ||
171 | #define P_TMRCLK (P_DONTCARE) | ||
172 | #define P_PPI0_CLK (P_DONTCARE) | ||
173 | |||
174 | #define P_MII0 {\ | ||
175 | P_MII0_ETxD0, \ | ||
176 | P_MII0_ETxD1, \ | ||
177 | P_MII0_ETxD2, \ | ||
178 | P_MII0_ETxD3, \ | ||
179 | P_MII0_ETxEN, \ | ||
180 | P_MII0_TxCLK, \ | ||
181 | P_MII0_PHYINT, \ | ||
182 | P_MII0_COL, \ | ||
183 | P_MII0_ERxD0, \ | ||
184 | P_MII0_ERxD1, \ | ||
185 | P_MII0_ERxD2, \ | ||
186 | P_MII0_ERxD3, \ | ||
187 | P_MII0_ERxDV, \ | ||
188 | P_MII0_ERxCLK, \ | ||
189 | P_MII0_ERxER, \ | ||
190 | P_MII0_CRS, \ | ||
191 | P_MDC, \ | ||
192 | P_MDIO, 0} | ||
193 | |||
194 | #define P_RMII0 {\ | ||
195 | P_MII0_ETxD0, \ | ||
196 | P_MII0_ETxD1, \ | ||
197 | P_MII0_ETxEN, \ | ||
198 | P_MII0_ERxD0, \ | ||
199 | P_MII0_ERxD1, \ | ||
200 | P_MII0_ERxER, \ | ||
201 | P_RMII0_REF_CLK, \ | ||
202 | P_RMII0_MDINT, \ | ||
203 | P_RMII0_CRS_DV, \ | ||
204 | P_MDC, \ | ||
205 | P_MDIO, 0} | ||
206 | |||
207 | #endif /* _MACH_PORTMUX_H_ */ | ||