diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-10-28 04:22:41 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-10-28 04:22:41 -0400 |
commit | 3529e0414b600faa1b6d822569b3343131235813 (patch) | |
tree | 9bed201d1b4f5f338cbe5bacf5a8287463720d74 /arch/blackfin/mach-bf527 | |
parent | 6a87d29bc684d845fe8338a8ce279f743d343250 (diff) |
Blackfin arch: update anomaly lists to match latest sheets
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r-- | arch/blackfin/mach-bf527/include/mach/anomaly.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 62373e61c585..8d09e6d5c9cd 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
@@ -28,7 +28,7 @@ | |||
28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
29 | #define ANOMALY_05000074 (1) | 29 | #define ANOMALY_05000074 (1) |
30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
31 | #define ANOMALY_05000119 (1) | 31 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
33 | #define ANOMALY_05000122 (1) | 33 | #define ANOMALY_05000122 (1) |
34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
@@ -37,8 +37,6 @@ | |||
37 | #define ANOMALY_05000265 (1) | 37 | #define ANOMALY_05000265 (1) |
38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
39 | #define ANOMALY_05000310 (1) | 39 | #define ANOMALY_05000310 (1) |
40 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
41 | #define ANOMALY_05000312 (ANOMALY_BF527) | ||
42 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 40 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
43 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) | 41 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) |
44 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
@@ -153,6 +151,8 @@ | |||
153 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) | 151 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) |
154 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ | 152 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
155 | #define ANOMALY_05000432 (ANOMALY_BF526) | 153 | #define ANOMALY_05000432 (ANOMALY_BF526) |
154 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
155 | #define ANOMALY_05000443 (1) | ||
156 | 156 | ||
157 | /* Anomalies that don't exist on this proc */ | 157 | /* Anomalies that don't exist on this proc */ |
158 | #define ANOMALY_05000125 (0) | 158 | #define ANOMALY_05000125 (0) |
@@ -168,6 +168,7 @@ | |||
168 | #define ANOMALY_05000285 (0) | 168 | #define ANOMALY_05000285 (0) |
169 | #define ANOMALY_05000307 (0) | 169 | #define ANOMALY_05000307 (0) |
170 | #define ANOMALY_05000311 (0) | 170 | #define ANOMALY_05000311 (0) |
171 | #define ANOMALY_05000312 (0) | ||
171 | #define ANOMALY_05000323 (0) | 172 | #define ANOMALY_05000323 (0) |
172 | #define ANOMALY_05000363 (0) | 173 | #define ANOMALY_05000363 (0) |
173 | 174 | ||