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authorMichael Hennerich <michael.hennerich@analog.com>2007-10-21 04:54:27 -0400
committerBryan Wu <bryan.wu@analog.com>2007-10-21 04:54:27 -0400
commit590031450a52c373bf72f5fb156fbcc0c78c6f2c (patch)
tree0e631bc6e8af9422635535459aaaf10fdddab357 /arch/blackfin/mach-bf527
parentcfa76f024f7c9e65169425804e5b32e71f66d0ee (diff)
Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/Kconfig251
-rw-r--r--arch/blackfin/mach-bf527/Makefile9
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile7
-rw-r--r--arch/blackfin/mach-bf527/boards/eth_mac.c50
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c737
-rw-r--r--arch/blackfin/mach-bf527/cpu.c161
-rw-r--r--arch/blackfin/mach-bf527/dma.c115
-rw-r--r--arch/blackfin/mach-bf527/head.S456
-rw-r--r--arch/blackfin/mach-bf527/ints-priority.c100
9 files changed, 1886 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
new file mode 100644
index 000000000000..50321f723dee
--- /dev/null
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -0,0 +1,251 @@
1if (BF52x)
2
3menu "BF527 Specific Configuration"
4
5comment "Alternative Multiplexing Scheme"
6
7choice
8 prompt "SPORT0"
9 default BF527_SPORT0_PORTG
10 help
11 Select PORT used for SPORT0. See Hardware Reference Manual
12
13config BF527_SPORT0_PORTF
14 bool "PORT F"
15 help
16 PORT F
17
18config BF527_SPORT0_PORTG
19 bool "PORT G"
20 help
21 PORT G
22endchoice
23
24choice
25 prompt "SPORT0 TSCLK Location"
26 depends on BF527_SPORT0_PORTG
27 default BF527_SPORT0_TSCLK_PG10
28 help
29 Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
30
31config BF527_SPORT0_TSCLK_PG10
32 bool "PORT PG10"
33 help
34 PORT PG10
35
36config BF527_SPORT0_TSCLK_PG14
37 bool "PORT PG14"
38 help
39 PORT PG14
40endchoice
41
42choice
43 prompt "UART1"
44 default BF527_UART1_PORTG
45 help
46 Select PORT used for UART1. See Hardware Reference Manual
47
48config BF527_UART1_PORTF
49 bool "PORT F"
50 help
51 PORT F
52
53config BF527_UART1_PORTG
54 bool "PORT G"
55 help
56 PORT G
57endchoice
58
59choice
60 prompt "NAND (NFC) Data"
61 default BF527_NAND_D_PORTH
62 help
63 Select PORT used for NAND Data Bus. See Hardware Reference Manual
64
65config BF527_NAND_D_PORTF
66 bool "PORT F"
67 help
68 PORT F
69
70config BF527_NAND_D_PORTH
71 bool "PORT H"
72 help
73 PORT H
74endchoice
75
76comment "Interrupt Priority Assignment"
77menu "Priority"
78
79config IRQ_PLL_WAKEUP
80 int "IRQ_PLL_WAKEUP"
81 default 7
82config IRQ_DMA0_ERROR
83 int "IRQ_DMA0_ERROR"
84 default 7
85config IRQ_DMAR0_BLK
86 int "IRQ_DMAR0_BLK"
87 default 7
88config IRQ_DMAR1_BLK
89 int "IRQ_DMAR1_BLK"
90 default 7
91config IRQ_DMAR0_OVR
92 int "IRQ_DMAR0_OVR"
93 default 7
94config IRQ_DMAR1_OVR
95 int "IRQ_DMAR1_OVR"
96 default 7
97config IRQ_PPI_ERROR
98 int "IRQ_PPI_ERROR"
99 default 7
100config IRQ_MAC_ERROR
101 int "IRQ_MAC_ERROR"
102 default 7
103config IRQ_SPORT0_ERROR
104 int "IRQ_SPORT0_ERROR"
105 default 7
106config IRQ_SPORT1_ERROR
107 int "IRQ_SPORT1_ERROR"
108 default 7
109config IRQ_UART0_ERROR
110 int "IRQ_UART0_ERROR"
111 default 7
112config IRQ_UART1_ERROR
113 int "IRQ_UART1_ERROR"
114 default 7
115config IRQ_RTC
116 int "IRQ_RTC"
117 default 8
118config IRQ_PPI
119 int "IRQ_PPI"
120 default 8
121config IRQ_SPORT0_RX
122 int "IRQ_SPORT0_RX"
123 default 9
124config IRQ_SPORT0_TX
125 int "IRQ_SPORT0_TX"
126 default 9
127config IRQ_SPORT1_RX
128 int "IRQ_SPORT1_RX"
129 default 9
130config IRQ_SPORT1_TX
131 int "IRQ_SPORT1_TX"
132 default 9
133config IRQ_TWI
134 int "IRQ_TWI"
135 default 10
136config IRQ_SPI
137 int "IRQ_SPI"
138 default 10
139config IRQ_UART0_RX
140 int "IRQ_UART0_RX"
141 default 10
142config IRQ_UART0_TX
143 int "IRQ_UART0_TX"
144 default 10
145config IRQ_UART1_RX
146 int "IRQ_UART1_RX"
147 default 10
148config IRQ_UART1_TX
149 int "IRQ_UART1_TX"
150 default 10
151config IRQ_OPTSEC
152 int "IRQ_OPTSEC"
153 default 11
154config IRQ_CNT
155 int "IRQ_CNT"
156 default 11
157config IRQ_MAC_RX
158 int "IRQ_MAC_RX"
159 default 11
160config IRQ_PORTH_INTA
161 int "IRQ_PORTH_INTA"
162 default 11
163config IRQ_MAC_TX
164 int "IRQ_MAC_TX/NFC"
165 default 11
166config IRQ_PORTH_INTB
167 int "IRQ_PORTH_INTB"
168 default 11
169config IRQ_TMR0
170 int "IRQ_TMR0"
171 default 12
172config IRQ_TMR1
173 int "IRQ_TMR1"
174 default 12
175config IRQ_TMR2
176 int "IRQ_TMR2"
177 default 12
178config IRQ_TMR3
179 int "IRQ_TMR3"
180 default 12
181config IRQ_TMR4
182 int "IRQ_TMR4"
183 default 12
184config IRQ_TMR5
185 int "IRQ_TMR5"
186 default 12
187config IRQ_TMR6
188 int "IRQ_TMR6"
189 default 12
190config IRQ_TMR7
191 int "IRQ_TMR7"
192 default 12
193config IRQ_PORTG_INTA
194 int "IRQ_PORTG_INTA"
195 default 12
196config IRQ_PORTG_INTB
197 int "IRQ_PORTG_INTB"
198 default 12
199config IRQ_MEM_DMA0
200 int "IRQ_MEM_DMA0"
201 default 13
202config IRQ_MEM_DMA1
203 int "IRQ_MEM_DMA1"
204 default 13
205config IRQ_WATCH
206 int "IRQ_WATCH"
207 default 13
208config IRQ_PORTF_INTA
209 int "IRQ_PORTF_INTA"
210 default 13
211config IRQ_PORTF_INTB
212 int "IRQ_PORTF_INTB"
213 default 13
214config IRQ_SPI_ERROR
215 int "IRQ_SPI_ERROR"
216 default 7
217config IRQ_NFC_ERROR
218 int "IRQ_NFC_ERROR"
219 default 7
220config IRQ_HDMA_ERROR
221 int "IRQ_HDMA_ERROR"
222 default 7
223config IRQ_HDMA
224 int "IRQ_HDMA"
225 default 7
226config IRQ_USB_EINT
227 int "IRQ_USB_EINT"
228 default 10
229config IRQ_USB_INT0
230 int "IRQ_USB_INT0"
231 default 10
232config IRQ_USB_INT1
233 int "IRQ_USB_INT1"
234 default 10
235config IRQ_USB_INT2
236 int "IRQ_USB_INT2"
237 default 10
238config IRQ_USB_DMA
239 int "IRQ_USB_DMA"
240 default 10
241
242 help
243 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
244 This applies to all the above. It is not recommended to assign the
245 highest priority number 7 to UART or any other device.
246
247endmenu
248
249endmenu
250
251endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
new file mode 100644
index 000000000000..9f99f5d0bcd1
--- /dev/null
+++ b/arch/blackfin/mach-bf527/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf527/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
new file mode 100644
index 000000000000..912ac8ebc889
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -0,0 +1,7 @@
1#
2# arch/blackfin/mach-bf532/boards/Makefile
3#
4
5obj-y += eth_mac.o
6obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
7
diff --git a/arch/blackfin/mach-bf527/boards/eth_mac.c b/arch/blackfin/mach-bf527/boards/eth_mac.c
new file mode 100644
index 000000000000..a725cc8a9290
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/eth_mac.c
@@ -0,0 +1,50 @@
1/*
2 * arch/blackfin/mach-bf537/board/eth_mac.c
3 *
4 * Copyright (C) 2007 Analog Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/module.h>
21#include <asm/blackfin.h>
22
23#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
24
25/*
26 * Currently the MAC address is saved in Flash by U-Boot
27 */
28#define FLASH_MAC 0x203f0000
29
30void get_bf537_ether_addr(char *addr)
31{
32 unsigned int flash_mac = (unsigned int) FLASH_MAC;
33 *(u32 *)(&(addr[0])) = bfin_read32(flash_mac);
34 flash_mac += 4;
35 *(u16 *)(&(addr[4])) = bfin_read16(flash_mac);
36}
37
38#else
39
40/*
41 * Provide MAC address function for other specific board setting
42 */
43void get_bf537_ether_addr(char *addr)
44{
45 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
46}
47
48#endif
49
50EXPORT_SYMBOL(get_bf537_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
new file mode 100644
index 000000000000..09fb624af5ac
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -0,0 +1,737 @@
1/*
2 * File: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/stamp.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h>
39#endif
40#include <linux/pata_platform.h>
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <linux/usb_sl811.h>
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
47#include <linux/spi/ad7877.h>
48
49/*
50 * Name the Board for the /proc/cpuinfo
51 */
52char *bfin_board_name = "ADDS-BF527-EZKIT";
53
54/*
55 * Driver needs to know address, irq and flag pin.
56 */
57
58#define ISP1761_BASE 0x203C0000
59#define ISP1761_IRQ IRQ_PF7
60
61#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
62static struct resource bfin_isp1761_resources[] = {
63 [0] = {
64 .name = "isp1761-regs",
65 .start = ISP1761_BASE + 0x00000000,
66 .end = ISP1761_BASE + 0x000fffff,
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = ISP1761_IRQ,
71 .end = ISP1761_IRQ,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device bfin_isp1761_device = {
77 .name = "isp1761",
78 .id = 0,
79 .num_resources = ARRAY_SIZE(bfin_isp1761_resources),
80 .resource = bfin_isp1761_resources,
81};
82
83static struct platform_device *bfin_isp1761_devices[] = {
84 &bfin_isp1761_device,
85};
86
87int __init bfin_isp1761_init(void)
88{
89 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
90
91 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
92 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
93
94 return platform_add_devices(bfin_isp1761_devices, num_devices);
95}
96
97void __exit bfin_isp1761_exit(void)
98{
99 platform_device_unregister(&bfin_isp1761_device);
100}
101
102arch_initcall(bfin_isp1761_init);
103#endif
104
105#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
106static struct resource bfin_pcmcia_cf_resources[] = {
107 {
108 .start = 0x20310000, /* IO PORT */
109 .end = 0x20312000,
110 .flags = IORESOURCE_MEM,
111 }, {
112 .start = 0x20311000, /* Attribute Memory */
113 .end = 0x20311FFF,
114 .flags = IORESOURCE_MEM,
115 }, {
116 .start = IRQ_PF4,
117 .end = IRQ_PF4,
118 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
119 }, {
120 .start = 6, /* Card Detect PF6 */
121 .end = 6,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device bfin_pcmcia_cf_device = {
127 .name = "bfin_cf_pcmcia",
128 .id = -1,
129 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
130 .resource = bfin_pcmcia_cf_resources,
131};
132#endif
133
134#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
135static struct platform_device rtc_device = {
136 .name = "rtc-bfin",
137 .id = -1,
138};
139#endif
140
141#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
142static struct resource smc91x_resources[] = {
143 {
144 .name = "smc91x-regs",
145 .start = 0x20300300,
146 .end = 0x20300300 + 16,
147 .flags = IORESOURCE_MEM,
148 }, {
149
150 .start = IRQ_PF7,
151 .end = IRQ_PF7,
152 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
153 },
154};
155static struct platform_device smc91x_device = {
156 .name = "smc91x",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(smc91x_resources),
159 .resource = smc91x_resources,
160};
161#endif
162
163#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
164static struct resource dm9000_resources[] = {
165 [0] = {
166 .start = 0x203FB800,
167 .end = 0x203FB800 + 8,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = IRQ_PF9,
172 .end = IRQ_PF9,
173 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
174 },
175};
176
177static struct platform_device dm9000_device = {
178 .name = "dm9000",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(dm9000_resources),
181 .resource = dm9000_resources,
182};
183#endif
184
185#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
186static struct resource sl811_hcd_resources[] = {
187 {
188 .start = 0x20340000,
189 .end = 0x20340000,
190 .flags = IORESOURCE_MEM,
191 }, {
192 .start = 0x20340004,
193 .end = 0x20340004,
194 .flags = IORESOURCE_MEM,
195 }, {
196 .start = CONFIG_USB_SL811_BFIN_IRQ,
197 .end = CONFIG_USB_SL811_BFIN_IRQ,
198 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
199 },
200};
201
202#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
203void sl811_port_power(struct device *dev, int is_on)
204{
205 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
206 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
207
208 if (is_on)
209 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
210 else
211 gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
212}
213#endif
214
215static struct sl811_platform_data sl811_priv = {
216 .potpg = 10,
217 .power = 250, /* == 500mA */
218#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
219 .port_power = &sl811_port_power,
220#endif
221};
222
223static struct platform_device sl811_hcd_device = {
224 .name = "sl811-hcd",
225 .id = 0,
226 .dev = {
227 .platform_data = &sl811_priv,
228 },
229 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
230 .resource = sl811_hcd_resources,
231};
232#endif
233
234#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
235static struct resource isp1362_hcd_resources[] = {
236 {
237 .start = 0x20360000,
238 .end = 0x20360000,
239 .flags = IORESOURCE_MEM,
240 }, {
241 .start = 0x20360004,
242 .end = 0x20360004,
243 .flags = IORESOURCE_MEM,
244 }, {
245 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
246 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
247 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
248 },
249};
250
251static struct isp1362_platform_data isp1362_priv = {
252 .sel15Kres = 1,
253 .clknotstop = 0,
254 .oc_enable = 0,
255 .int_act_high = 0,
256 .int_edge_triggered = 0,
257 .remote_wakeup_connected = 0,
258 .no_power_switching = 1,
259 .power_switching_mode = 0,
260};
261
262static struct platform_device isp1362_hcd_device = {
263 .name = "isp1362-hcd",
264 .id = 0,
265 .dev = {
266 .platform_data = &isp1362_priv,
267 },
268 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
269 .resource = isp1362_hcd_resources,
270};
271#endif
272
273#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
274static struct platform_device bfin_mac_device = {
275 .name = "bfin_mac",
276};
277#endif
278
279#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
280static struct resource net2272_bfin_resources[] = {
281 {
282 .start = 0x20300000,
283 .end = 0x20300000 + 0x100,
284 .flags = IORESOURCE_MEM,
285 }, {
286 .start = IRQ_PF7,
287 .end = IRQ_PF7,
288 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
289 },
290};
291
292static struct platform_device net2272_bfin_device = {
293 .name = "net2272",
294 .id = -1,
295 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
296 .resource = net2272_bfin_resources,
297};
298#endif
299
300#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
301/* all SPI peripherals info goes here */
302
303#if defined(CONFIG_MTD_M25P80) \
304 || defined(CONFIG_MTD_M25P80_MODULE)
305static struct mtd_partition bfin_spi_flash_partitions[] = {
306 {
307 .name = "bootloader",
308 .size = 0x00020000,
309 .offset = 0,
310 .mask_flags = MTD_CAP_ROM
311 }, {
312 .name = "kernel",
313 .size = 0xe0000,
314 .offset = 0x20000
315 }, {
316 .name = "file system",
317 .size = 0x700000,
318 .offset = 0x00100000,
319 }
320};
321
322static struct flash_platform_data bfin_spi_flash_data = {
323 .name = "m25p80",
324 .parts = bfin_spi_flash_partitions,
325 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
326 .type = "m25p64",
327};
328
329/* SPI flash chip (m25p64) */
330static struct bfin5xx_spi_chip spi_flash_chip_info = {
331 .enable_dma = 0, /* use dma transfer with this chip*/
332 .bits_per_word = 8,
333};
334#endif
335
336#if defined(CONFIG_SPI_ADC_BF533) \
337 || defined(CONFIG_SPI_ADC_BF533_MODULE)
338/* SPI ADC chip */
339static struct bfin5xx_spi_chip spi_adc_chip_info = {
340 .enable_dma = 1, /* use dma transfer with this chip*/
341 .bits_per_word = 16,
342};
343#endif
344
345#if defined(CONFIG_SND_BLACKFIN_AD1836) \
346 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0,
349 .bits_per_word = 16,
350};
351#endif
352
353#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
354static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
355 .enable_dma = 0,
356 .bits_per_word = 16,
357};
358#endif
359
360#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
361static struct bfin5xx_spi_chip spi_mmc_chip_info = {
362 .enable_dma = 1,
363 .bits_per_word = 8,
364};
365#endif
366
367#if defined(CONFIG_PBX)
368static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
369 .ctl_reg = 0x4, /* send zero */
370 .enable_dma = 0,
371 .bits_per_word = 8,
372 .cs_change_per_word = 1,
373};
374#endif
375
376#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
377static struct bfin5xx_spi_chip ad5304_chip_info = {
378 .enable_dma = 0,
379 .bits_per_word = 16,
380};
381#endif
382
383#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
384static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
385 .enable_dma = 0,
386 .bits_per_word = 16,
387};
388
389static const struct ad7877_platform_data bfin_ad7877_ts_info = {
390 .model = 7877,
391 .vref_delay_usecs = 50, /* internal, no capacitor */
392 .x_plate_ohms = 419,
393 .y_plate_ohms = 486,
394 .pressure_max = 1000,
395 .pressure_min = 0,
396 .stopacq_polarity = 1,
397 .first_conversion_delay = 3,
398 .acquisition_time = 1,
399 .averaging = 1,
400 .pen_down_acc_interval = 1,
401};
402#endif
403
404static struct spi_board_info bfin_spi_board_info[] __initdata = {
405#if defined(CONFIG_MTD_M25P80) \
406 || defined(CONFIG_MTD_M25P80_MODULE)
407 {
408 /* the modalias must be the same as spi device driver name */
409 .modalias = "m25p80", /* Name of spi_driver for this device */
410 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
411 .bus_num = 0, /* Framework bus number */
412 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
413 .platform_data = &bfin_spi_flash_data,
414 .controller_data = &spi_flash_chip_info,
415 .mode = SPI_MODE_3,
416 },
417#endif
418
419#if defined(CONFIG_SPI_ADC_BF533) \
420 || defined(CONFIG_SPI_ADC_BF533_MODULE)
421 {
422 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
423 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
424 .bus_num = 0, /* Framework bus number */
425 .chip_select = 1, /* Framework chip select. */
426 .platform_data = NULL, /* No spi_driver specific config */
427 .controller_data = &spi_adc_chip_info,
428 },
429#endif
430
431#if defined(CONFIG_SND_BLACKFIN_AD1836) \
432 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
433 {
434 .modalias = "ad1836-spi",
435 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
436 .bus_num = 0,
437 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
438 .controller_data = &ad1836_spi_chip_info,
439 },
440#endif
441#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
442 {
443 .modalias = "ad9960-spi",
444 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
445 .bus_num = 0,
446 .chip_select = 1,
447 .controller_data = &ad9960_spi_chip_info,
448 },
449#endif
450#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
451 {
452 .modalias = "spi_mmc_dummy",
453 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
454 .bus_num = 0,
455 .chip_select = 0,
456 .platform_data = NULL,
457 .controller_data = &spi_mmc_chip_info,
458 .mode = SPI_MODE_3,
459 },
460 {
461 .modalias = "spi_mmc",
462 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
463 .bus_num = 0,
464 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
465 .platform_data = NULL,
466 .controller_data = &spi_mmc_chip_info,
467 .mode = SPI_MODE_3,
468 },
469#endif
470#if defined(CONFIG_PBX)
471 {
472 .modalias = "fxs-spi",
473 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
474 .bus_num = 0,
475 .chip_select = 8 - CONFIG_J11_JUMPER,
476 .controller_data = &spi_si3xxx_chip_info,
477 .mode = SPI_MODE_3,
478 },
479 {
480 .modalias = "fxo-spi",
481 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
482 .bus_num = 0,
483 .chip_select = 8 - CONFIG_J19_JUMPER,
484 .controller_data = &spi_si3xxx_chip_info,
485 .mode = SPI_MODE_3,
486 },
487#endif
488#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
489 {
490 .modalias = "ad5304_spi",
491 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
492 .bus_num = 0,
493 .chip_select = 2,
494 .platform_data = NULL,
495 .controller_data = &ad5304_chip_info,
496 .mode = SPI_MODE_2,
497 },
498#endif
499#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
500 {
501 .modalias = "ad7877",
502 .platform_data = &bfin_ad7877_ts_info,
503 .irq = IRQ_PF6,
504 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
505 .bus_num = 1,
506 .chip_select = 1,
507 .controller_data = &spi_ad7877_chip_info,
508 },
509#endif
510};
511
512/* SPI controller data */
513static struct bfin5xx_spi_master bfin_spi0_info = {
514 .num_chipselect = 8,
515 .enable_dma = 1, /* master has the ability to do dma transfer */
516};
517
518/* SPI (0) */
519static struct resource bfin_spi0_resource[] = {
520 [0] = {
521 .start = SPI0_REGBASE,
522 .end = SPI0_REGBASE + 0xFF,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = CH_SPI,
527 .end = CH_SPI,
528 .flags = IORESOURCE_IRQ,
529 },
530};
531
532static struct platform_device bfin_spi0_device = {
533 .name = "bfin-spi",
534 .id = 0, /* Bus number */
535 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
536 .resource = bfin_spi0_resource,
537 .dev = {
538 .platform_data = &bfin_spi0_info, /* Passed to driver */
539 },
540};
541#endif /* spi master and devices */
542
543#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
544static struct platform_device bfin_fb_device = {
545 .name = "bf537-lq035",
546};
547#endif
548
549#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
550static struct platform_device bfin_fb_adv7393_device = {
551 .name = "bfin-adv7393",
552};
553#endif
554
555#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
556static struct resource bfin_uart_resources[] = {
557#ifdef CONFIG_SERIAL_BFIN_UART0
558 {
559 .start = 0xFFC00400,
560 .end = 0xFFC004FF,
561 .flags = IORESOURCE_MEM,
562 },
563#endif
564#ifdef CONFIG_SERIAL_BFIN_UART1
565 {
566 .start = 0xFFC02000,
567 .end = 0xFFC020FF,
568 .flags = IORESOURCE_MEM,
569 },
570#endif
571};
572
573static struct platform_device bfin_uart_device = {
574 .name = "bfin-uart",
575 .id = 1,
576 .num_resources = ARRAY_SIZE(bfin_uart_resources),
577 .resource = bfin_uart_resources,
578};
579#endif
580
581#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
582static struct resource bfin_twi0_resource[] = {
583 [0] = {
584 .start = TWI0_REGBASE,
585 .end = TWI0_REGBASE,
586 .flags = IORESOURCE_MEM,
587 },
588 [1] = {
589 .start = IRQ_TWI,
590 .end = IRQ_TWI,
591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595static struct platform_device i2c_bfin_twi_device = {
596 .name = "i2c-bfin-twi",
597 .id = 0,
598 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
599 .resource = bfin_twi0_resource,
600};
601#endif
602
603#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
604static struct platform_device bfin_sport0_uart_device = {
605 .name = "bfin-sport-uart",
606 .id = 0,
607};
608
609static struct platform_device bfin_sport1_uart_device = {
610 .name = "bfin-sport-uart",
611 .id = 1,
612};
613#endif
614
615#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
616#define PATA_INT 55
617
618static struct pata_platform_info bfin_pata_platform_data = {
619 .ioport_shift = 1,
620 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
621};
622
623static struct resource bfin_pata_resources[] = {
624 {
625 .start = 0x20314020,
626 .end = 0x2031403F,
627 .flags = IORESOURCE_MEM,
628 },
629 {
630 .start = 0x2031401C,
631 .end = 0x2031401F,
632 .flags = IORESOURCE_MEM,
633 },
634 {
635 .start = PATA_INT,
636 .end = PATA_INT,
637 .flags = IORESOURCE_IRQ,
638 },
639};
640
641static struct platform_device bfin_pata_device = {
642 .name = "pata_platform",
643 .id = -1,
644 .num_resources = ARRAY_SIZE(bfin_pata_resources),
645 .resource = bfin_pata_resources,
646 .dev = {
647 .platform_data = &bfin_pata_platform_data,
648 }
649};
650#endif
651
652static struct platform_device *stamp_devices[] __initdata = {
653#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
654 &bfin_pcmcia_cf_device,
655#endif
656
657#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
658 &rtc_device,
659#endif
660
661#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
662 &sl811_hcd_device,
663#endif
664
665#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
666 &isp1362_hcd_device,
667#endif
668
669#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
670 &smc91x_device,
671#endif
672
673#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
674 &dm9000_device,
675#endif
676
677#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
678 &bfin_mac_device,
679#endif
680
681#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
682 &net2272_bfin_device,
683#endif
684
685#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
686 &bfin_spi0_device,
687#endif
688
689#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
690 &bfin_fb_device,
691#endif
692
693#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
694 &bfin_fb_adv7393_device,
695#endif
696
697#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
698 &bfin_uart_device,
699#endif
700
701#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
702 &i2c_bfin_twi_device,
703#endif
704
705#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
706 &bfin_sport0_uart_device,
707 &bfin_sport1_uart_device,
708#endif
709
710#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
711 &bfin_pata_device,
712#endif
713};
714
715static int __init stamp_init(void)
716{
717 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
718 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
719#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
720 spi_register_board_info(bfin_spi_board_info,
721 ARRAY_SIZE(bfin_spi_board_info));
722#endif
723
724#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
725 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
726#endif
727 return 0;
728}
729
730arch_initcall(stamp_init);
731
732void native_machine_restart(char *cmd)
733{
734 /* workaround reboot hang when booting from SPI */
735 if ((bfin_read_SYSCR() & 0x7) == 0x3)
736 bfin_gpio_reset_spi0_ssel1();
737}
diff --git a/arch/blackfin/mach-bf527/cpu.c b/arch/blackfin/mach-bf527/cpu.c
new file mode 100644
index 000000000000..1975402b1dbc
--- /dev/null
+++ b/arch/blackfin/mach-bf527/cpu.c
@@ -0,0 +1,161 @@
1/*
2 * File: arch/blackfin/mach-bf527/cpu.c
3 * Based on: arch/blackfin/mach-bf537/cpu.c
4 * Author: michael.kang@analog.com
5 *
6 * Created:
7 * Description: clock scaling for the bf527
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=11059200 */
39#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */
40#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */
41#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */
42#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */
43#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */
44#define VCO(x) VCO##x
45
46#define MFREQ(x) {VCO(x), VCO(x)/4}, {VCO(x), VCO(x)/2}, {VCO(x), VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf527_freq_table[] = {
49 MFREQ(1),
50 MFREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 MFREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf527_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69
70 return cclk_mhz;
71}
72
73static int bf527_target(struct cpufreq_policy *policy,
74 unsigned int target_freq, unsigned int relation)
75{
76 unsigned long cclk_mhz;
77 unsigned long vco_mhz;
78 unsigned long flags;
79 unsigned int index;
80 struct cpufreq_freqs freqs;
81
82 if (cpufreq_frequency_table_target
83 (policy, bf527_freq_table, target_freq, relation, &index))
84 return -EINVAL;
85
86 cclk_mhz = bf527_freq_table[index].frequency;
87 vco_mhz = bf527_freq_table[index].index;
88
89 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
90 freqs.old = bf527_getfreq(0);
91 freqs.new = cclk_mhz;
92 freqs.cpu = 0;
93
94 pr_debug
95 ("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
96 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
97
98 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
99 local_irq_save(flags);
100 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
101 local_irq_restore(flags);
102 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
103
104 vco_mhz = get_vco();
105 cclk_mhz = get_cclk();
106 return 0;
107}
108
109/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
110 * this platform, anyway.
111 */
112static int bf527_verify_speed(struct cpufreq_policy *policy)
113{
114 return cpufreq_frequency_table_verify(policy, &bf527_freq_table);
115}
116
117static int __init __bf527_cpu_init(struct cpufreq_policy *policy)
118{
119 if (policy->cpu != 0)
120 return -EINVAL;
121
122 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
123
124 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
125 /*Now ,only support one cpu */
126 policy->cur = bf527_getfreq(0);
127 cpufreq_frequency_table_get_attr(bf527_freq_table, policy->cpu);
128 return cpufreq_frequency_table_cpuinfo(policy, bf527_freq_table);
129}
130
131static struct freq_attr *bf527_freq_attr[] = {
132 &cpufreq_freq_attr_scaling_available_freqs,
133 NULL,
134};
135
136static struct cpufreq_driver bf527_driver = {
137 .verify = bf527_verify_speed,
138 .target = bf527_target,
139 .get = bf527_getfreq,
140 .init = __bf527_cpu_init,
141 .name = "bf527",
142 .owner = THIS_MODULE,
143 .attr = bf527_freq_attr,
144};
145
146static int __init bf527_cpu_init(void)
147{
148 return cpufreq_register_driver(&bf527_driver);
149}
150
151static void __exit bf527_cpu_exit(void)
152{
153 cpufreq_unregister_driver(&bf527_driver);
154}
155
156MODULE_AUTHOR("Mickael Kang");
157MODULE_DESCRIPTION("cpufreq driver for bf527 CPU");
158MODULE_LICENSE("GPL");
159
160module_init(bf527_cpu_init);
161module_exit(bf527_cpu_exit);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
new file mode 100644
index 000000000000..522de24cc394
--- /dev/null
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -0,0 +1,115 @@
1/*
2 * File: arch/blackfin/mach-bf527/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA11_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
49};
50
51int channel2irq(unsigned int channel)
52{
53 int ret_irq = -1;
54
55 switch (channel) {
56 case CH_PPI:
57 ret_irq = IRQ_PPI;
58 break;
59
60 case CH_EMAC_RX:
61 ret_irq = IRQ_MAC_RX;
62 break;
63
64 case CH_EMAC_TX:
65 ret_irq = IRQ_MAC_TX;
66 break;
67
68 case CH_UART1_RX:
69 ret_irq = IRQ_UART1_RX;
70 break;
71
72 case CH_UART1_TX:
73 ret_irq = IRQ_UART1_TX;
74 break;
75
76 case CH_SPORT0_RX:
77 ret_irq = IRQ_SPORT0_RX;
78 break;
79
80 case CH_SPORT0_TX:
81 ret_irq = IRQ_SPORT0_TX;
82 break;
83
84 case CH_SPORT1_RX:
85 ret_irq = IRQ_SPORT1_RX;
86 break;
87
88 case CH_SPORT1_TX:
89 ret_irq = IRQ_SPORT1_TX;
90 break;
91
92 case CH_SPI:
93 ret_irq = IRQ_SPI;
94 break;
95
96 case CH_UART0_RX:
97 ret_irq = IRQ_UART0_RX;
98 break;
99
100 case CH_UART0_TX:
101 ret_irq = IRQ_UART0_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108
109 case CH_MEM_STREAM1_SRC:
110 case CH_MEM_STREAM1_DEST:
111 ret_irq = IRQ_MEM_DMA1;
112 break;
113 }
114 return ret_irq;
115}
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
new file mode 100644
index 000000000000..cdb00a084965
--- /dev/null
+++ b/arch/blackfin/mach-bf527/head.S
@@ -0,0 +1,456 @@
1/*
2 * File: arch/blackfin/mach-bf527/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF537
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#if CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h>
38#endif
39
40.global __rambase
41.global __ramstart
42.global __ramend
43.extern ___bss_stop
44.extern ___bss_start
45.extern _bf53x_relocate_l1_mem
46
47#define INITIAL_STACK 0xFFB01000
48
49__INIT
50
51ENTRY(__start)
52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0;
54 /* Enable Cycle Counter and Nesting Of Interrupts */
55#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
56 R0 = SYSCFG_SNEN;
57#else
58 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
59#endif
60 SYSCFG = R0;
61 R0 = 0;
62
63 /* Clear Out All the data and pointer Registers */
64 R1 = R0;
65 R2 = R0;
66 R3 = R0;
67 R4 = R0;
68 R5 = R0;
69 R6 = R0;
70
71 P0 = R0;
72 P1 = R0;
73 P2 = R0;
74 P3 = R0;
75 P4 = R0;
76 P5 = R0;
77
78 LC0 = r0;
79 LC1 = r0;
80 L0 = r0;
81 L1 = r0;
82 L2 = r0;
83 L3 = r0;
84
85 /* Clear Out All the DAG Registers */
86 B0 = r0;
87 B1 = r0;
88 B2 = r0;
89 B3 = r0;
90
91 I0 = r0;
92 I1 = r0;
93 I2 = r0;
94 I3 = r0;
95
96 M0 = r0;
97 M1 = r0;
98 M2 = r0;
99 M3 = r0;
100
101 trace_buffer_init(p0,r0);
102 P0 = R1;
103 R0 = R1;
104
105 /* Turn off the icache */
106 p0.l = LO(IMEM_CONTROL);
107 p0.h = HI(IMEM_CONTROL);
108 R1 = [p0];
109 R0 = ~ENICPLB;
110 R0 = R0 & R1;
111
112 /* Anomaly 05000125 */
113#if ANOMALY_05000125
114 CLI R2;
115 SSYNC;
116#endif
117 [p0] = R0;
118 SSYNC;
119#if ANOMALY_05000125
120 STI R2;
121#endif
122
123 /* Turn off the dcache */
124 p0.l = LO(DMEM_CONTROL);
125 p0.h = HI(DMEM_CONTROL);
126 R1 = [p0];
127 R0 = ~ENDCPLB;
128 R0 = R0 & R1;
129
130 /* Anomaly 05000125 */
131#if ANOMALY_05000125
132 CLI R2;
133 SSYNC;
134#endif
135 [p0] = R0;
136 SSYNC;
137#if ANOMALY_05000125
138 STI R2;
139#endif
140
141
142#if defined(CONFIG_BF527)
143 p0.h = hi(EMAC_SYSTAT);
144 p0.l = lo(EMAC_SYSTAT);
145 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
146 R0.l = 0xFFFF;
147 [P0] = R0;
148 SSYNC;
149#endif
150
151 /* Initialise UART - when booting from u-boot, the UART is not disabled
152 * so if we dont initalize here, our serial console gets hosed */
153 p0.h = hi(UART1_LCR);
154 p0.l = lo(UART1_LCR);
155 r0 = 0x0(Z);
156 w[p0] = r0.L; /* To enable DLL writes */
157 ssync;
158
159 p0.h = hi(UART1_DLL);
160 p0.l = lo(UART1_DLL);
161 r0 = 0x0(Z);
162 w[p0] = r0.L;
163 ssync;
164
165 p0.h = hi(UART1_DLH);
166 p0.l = lo(UART1_DLH);
167 r0 = 0x00(Z);
168 w[p0] = r0.L;
169 ssync;
170
171 p0.h = hi(UART1_GCTL);
172 p0.l = lo(UART1_GCTL);
173 r0 = 0x0(Z);
174 w[p0] = r0.L; /* To enable UART clock */
175 ssync;
176
177 /* Initialize stack pointer */
178 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK);
180 fp = sp;
181 usp = sp;
182
183#ifdef CONFIG_EARLY_PRINTK
184 SP += -12;
185 call _init_early_exception_vectors;
186 SP += 12;
187#endif
188
189 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
190 call _bf53x_relocate_l1_mem;
191#if CONFIG_BFIN_KERNEL_CLOCK
192 call _start_dma_code;
193#endif
194
195 /* Code for initializing Async memory banks */
196
197 p2.h = hi(EBIU_AMBCTL1);
198 p2.l = lo(EBIU_AMBCTL1);
199 r0.h = hi(AMBCTL1VAL);
200 r0.l = lo(AMBCTL1VAL);
201 [p2] = r0;
202 ssync;
203
204 p2.h = hi(EBIU_AMBCTL0);
205 p2.l = lo(EBIU_AMBCTL0);
206 r0.h = hi(AMBCTL0VAL);
207 r0.l = lo(AMBCTL0VAL);
208 [p2] = r0;
209 ssync;
210
211 p2.h = hi(EBIU_AMGCTL);
212 p2.l = lo(EBIU_AMGCTL);
213 r0 = AMGCTLVAL;
214 w[p2] = r0;
215 ssync;
216
217 /* This section keeps the processor in supervisor mode
218 * during kernel boot. Switches to user mode at end of boot.
219 * See page 3-9 of Hardware Reference manual for documentation.
220 */
221
222 /* EVT15 = _real_start */
223
224 p0.l = lo(EVT15);
225 p0.h = hi(EVT15);
226 p1.l = _real_start;
227 p1.h = _real_start;
228 [p0] = p1;
229 csync;
230
231 p0.l = lo(IMASK);
232 p0.h = hi(IMASK);
233 p1.l = IMASK_IVG15;
234 p1.h = 0x0;
235 [p0] = p1;
236 csync;
237
238 raise 15;
239 p0.l = .LWAIT_HERE;
240 p0.h = .LWAIT_HERE;
241 reti = p0;
242#if ANOMALY_05000281
243 nop; nop; nop;
244#endif
245 rti;
246
247.LWAIT_HERE:
248 jump .LWAIT_HERE;
249ENDPROC(__start)
250
251ENTRY(_real_start)
252 [ -- sp ] = reti;
253 p0.l = lo(WDOG_CTL);
254 p0.h = hi(WDOG_CTL);
255 r0 = 0xAD6(z);
256 w[p0] = r0; /* watchdog off for now */
257 ssync;
258
259 /* Code update for BSS size == 0
260 * Zero out the bss region.
261 */
262
263 p1.l = ___bss_start;
264 p1.h = ___bss_start;
265 p2.l = ___bss_stop;
266 p2.h = ___bss_stop;
267 r0 = 0;
268 p2 -= p1;
269 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
270.L_clear_bss:
271 B[p1++] = r0;
272
273 /* In case there is a NULL pointer reference
274 * Zero out region before stext
275 */
276
277 p1.l = 0x0;
278 p1.h = 0x0;
279 r0.l = __stext;
280 r0.h = __stext;
281 r0 = r0 >> 1;
282 p2 = r0;
283 r0 = 0;
284 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
285.L_clear_zero:
286 W[p1++] = r0;
287
288 /* pass the uboot arguments to the global value command line */
289 R0 = R7;
290 call _cmdline_init;
291
292 p1.l = __rambase;
293 p1.h = __rambase;
294 r0.l = __sdata;
295 r0.h = __sdata;
296 [p1] = r0;
297
298 p1.l = __ramstart;
299 p1.h = __ramstart;
300 p3.l = ___bss_stop;
301 p3.h = ___bss_stop;
302
303 r1 = p3;
304 [p1] = r1;
305
306 /*
307 * load the current thread pointer and stack
308 */
309 r1.l = _init_thread_union;
310 r1.h = _init_thread_union;
311
312 r2.l = 0x2000;
313 r2.h = 0x0000;
314 r1 = r1 + r2;
315 sp = r1;
316 usp = sp;
317 fp = sp;
318 jump.l _start_kernel;
319ENDPROC(_real_start)
320
321__FINIT
322
323.section .l1.text
324#if CONFIG_BFIN_KERNEL_CLOCK
325ENTRY(_start_dma_code)
326
327 /* Enable PHY CLK buffer output */
328 p0.h = hi(VR_CTL);
329 p0.l = lo(VR_CTL);
330 r0.l = w[p0];
331 bitset(r0, 14);
332 w[p0] = r0.l;
333 ssync;
334
335 p0.h = hi(SIC_IWR0);
336 p0.l = lo(SIC_IWR0);
337 r0.l = 0x1;
338 r0.h = 0x0;
339 [p0] = r0;
340 SSYNC;
341
342 /*
343 * Set PLL_CTL
344 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
345 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
346 * - [7] = output delay (add 200ps of delay to mem signals)
347 * - [6] = input delay (add 200ps of input delay to mem signals)
348 * - [5] = PDWN : 1=All Clocks off
349 * - [3] = STOPCK : 1=Core Clock off
350 * - [1] = PLL_OFF : 1=Disable Power to PLL
351 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
352 * all other bits set to zero
353 */
354
355 p0.h = hi(PLL_LOCKCNT);
356 p0.l = lo(PLL_LOCKCNT);
357 r0 = 0x300(Z);
358 w[p0] = r0.l;
359 ssync;
360
361 P2.H = hi(EBIU_SDGCTL);
362 P2.L = lo(EBIU_SDGCTL);
363 R0 = [P2];
364 BITSET (R0, 24);
365 [P2] = R0;
366 SSYNC;
367
368 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
369 r0 = r0 << 9; /* Shift it over, */
370 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
371 r0 = r1 | r0;
372 r1 = PLL_BYPASS; /* Bypass the PLL? */
373 r1 = r1 << 8; /* Shift it over */
374 r0 = r1 | r0; /* add them all together */
375
376 p0.h = hi(PLL_CTL);
377 p0.l = lo(PLL_CTL); /* Load the address */
378 cli r2; /* Disable interrupts */
379 ssync;
380 w[p0] = r0.l; /* Set the value */
381 idle; /* Wait for the PLL to stablize */
382 sti r2; /* Enable interrupts */
383
384.Lcheck_again:
385 p0.h = hi(PLL_STAT);
386 p0.l = lo(PLL_STAT);
387 R0 = W[P0](Z);
388 CC = BITTST(R0,5);
389 if ! CC jump .Lcheck_again;
390
391 /* Configure SCLK & CCLK Dividers */
392 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
393 p0.h = hi(PLL_DIV);
394 p0.l = lo(PLL_DIV);
395 w[p0] = r0.l;
396 ssync;
397
398 p0.l = lo(EBIU_SDRRC);
399 p0.h = hi(EBIU_SDRRC);
400 r0 = mem_SDRRC;
401 w[p0] = r0.l;
402 ssync;
403
404 p0.l = LO(EBIU_SDBCTL);
405 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
406 r0 = mem_SDBCTL;
407 w[p0] = r0.l;
408 ssync;
409
410 P2.H = hi(EBIU_SDGCTL);
411 P2.L = lo(EBIU_SDGCTL);
412 R0 = [P2];
413 BITCLR (R0, 24);
414 p0.h = hi(EBIU_SDSTAT);
415 p0.l = lo(EBIU_SDSTAT);
416 r2.l = w[p0];
417 cc = bittst(r2,3);
418 if !cc jump .Lskip;
419 NOP;
420 BITSET (R0, 23);
421.Lskip:
422 [P2] = R0;
423 SSYNC;
424
425 R0.L = lo(mem_SDGCTL);
426 R0.H = hi(mem_SDGCTL);
427 R1 = [p2];
428 R1 = R1 | R0;
429 [P2] = R1;
430 SSYNC;
431
432 p0.h = hi(SIC_IWR0);
433 p0.l = lo(SIC_IWR0);
434 r0.l = lo(IWR_ENABLE_ALL);
435 r0.h = hi(IWR_ENABLE_ALL);
436 [p0] = r0;
437 SSYNC;
438
439 RTS;
440ENDPROC(_start_dma_code)
441#endif /* CONFIG_BFIN_KERNEL_CLOCK */
442
443.data
444
445/*
446 * Set up the usable of RAM stuff. Size of RAM is determined then
447 * an initial stack set up at the end.
448 */
449
450.align 4
451__rambase:
452.long 0
453__ramstart:
454.long 0
455__ramend:
456.long 0
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
new file mode 100644
index 000000000000..1fa389793968
--- /dev/null
+++ b/arch/blackfin/mach-bf527/ints-priority.c
@@ -0,0 +1,100 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
39 ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
40 ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
41 ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
42 ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
43 ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
44 ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
45
46
47 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
48 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
49 ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
50 ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
51 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
52 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
53
54 bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
55 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
56 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
57 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
58 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
59 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
60 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
61 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
64 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
65 ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
66 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
67 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
68 ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
69 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
70 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
73 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
74 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
75 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
76 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
77 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
78 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
79 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
82 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
83 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
84 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
85 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
86 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
87 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
88 ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
91 ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
92 ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
93 ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
94 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
95 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
96 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
97 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
98
99 SSYNC();
100}
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