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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:17:10 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:17:10 -0400
commit7e64acabfdb530b1b7d3db2592d75d102827baf3 (patch)
tree9cd5d29f86a700fa474f063462bad928d292b567 /arch/blackfin/mach-bf527
parent1375204611f417541e55ee09e248acdbbb94356d (diff)
Blackfin arch: move async memory programming into common setup_arch() as the banks dont really need to be setup fully as early as head.S
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/head.S22
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index 180d3c85a4c1..9173dcecd158 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -170,28 +170,6 @@ ENTRY(__start)
170 call _start_dma_code; 170 call _start_dma_code;
171#endif 171#endif
172 172
173 /* Code for initializing Async memory banks */
174
175 p2.h = hi(EBIU_AMBCTL1);
176 p2.l = lo(EBIU_AMBCTL1);
177 r0.h = hi(AMBCTL1VAL);
178 r0.l = lo(AMBCTL1VAL);
179 [p2] = r0;
180 ssync;
181
182 p2.h = hi(EBIU_AMBCTL0);
183 p2.l = lo(EBIU_AMBCTL0);
184 r0.h = hi(AMBCTL0VAL);
185 r0.l = lo(AMBCTL0VAL);
186 [p2] = r0;
187 ssync;
188
189 p2.h = hi(EBIU_AMGCTL);
190 p2.l = lo(EBIU_AMGCTL);
191 r0 = AMGCTLVAL;
192 w[p2] = r0;
193 ssync;
194
195 /* This section keeps the processor in supervisor mode 173 /* This section keeps the processor in supervisor mode
196 * during kernel boot. Switches to user mode at end of boot. 174 * during kernel boot. Switches to user mode at end of boot.
197 * See page 3-9 of Hardware Reference manual for documentation. 175 * See page 3-9 of Hardware Reference manual for documentation.