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authorMichael Hennerich <michael.hennerich@analog.com>2008-07-14 04:51:57 -0400
committerBryan Wu <cooloney@kernel.org>2008-07-14 04:51:57 -0400
commit68e2fc78e5055740126df8eab0d31005495756c9 (patch)
tree0d43976ff1d3ae8535445f9bcb1687f657f33337 /arch/blackfin/mach-bf527
parent260d5d3517c67c5b68b4e28c5d3e1e3b73976a90 (diff)
Blackfin arch: Fix bug - Kernel does not boot if re-program clocks
Don't write conflicting data to EBIU_SDBCTL after the SDRAM is configured. This can cause data corruption, since we might change SDRAM row and column addressing modes. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/head.S12
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index 57bdb3ba2fed..fe05cc1ef174 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -32,7 +32,7 @@
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h> 33#include <asm/trace.h>
34 34
35#if CONFIG_BFIN_KERNEL_CLOCK 35#ifdef CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 36#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 37#include <asm/mach/mem_init.h>
38#endif 38#endif
@@ -185,7 +185,7 @@ ENTRY(__start)
185 185
186 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ 186 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
187 call _bf53x_relocate_l1_mem; 187 call _bf53x_relocate_l1_mem;
188#if CONFIG_BFIN_KERNEL_CLOCK 188#ifdef CONFIG_BFIN_KERNEL_CLOCK
189 call _start_dma_code; 189 call _start_dma_code;
190#endif 190#endif
191 191
@@ -318,7 +318,7 @@ ENDPROC(_real_start)
318__FINIT 318__FINIT
319 319
320.section .l1.text 320.section .l1.text
321#if CONFIG_BFIN_KERNEL_CLOCK 321#ifdef CONFIG_BFIN_KERNEL_CLOCK
322ENTRY(_start_dma_code) 322ENTRY(_start_dma_code)
323 323
324 /* Enable PHY CLK buffer output */ 324 /* Enable PHY CLK buffer output */
@@ -398,12 +398,6 @@ ENTRY(_start_dma_code)
398 w[p0] = r0.l; 398 w[p0] = r0.l;
399 ssync; 399 ssync;
400 400
401 p0.l = LO(EBIU_SDBCTL);
402 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
403 r0 = mem_SDBCTL;
404 w[p0] = r0.l;
405 ssync;
406
407 P2.H = hi(EBIU_SDGCTL); 401 P2.H = hi(EBIU_SDGCTL);
408 P2.L = lo(EBIU_SDGCTL); 402 P2.L = lo(EBIU_SDGCTL);
409 R0 = [P2]; 403 R0 = [P2];