Merge branch 'master' into for-next

Conflicts:
	arch/arm/mach-omap1/board-nokia770.c

6 files changed, 272 insertions, 260 deletions

diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 1f8cbe9d6b9a..0ba54701af0b 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -79,6 +79,72 @@ config BF527_NAND_D_PORTH
           PORT H
 endchoice
 
+comment "Hysteresis/Schmitt Trigger Control"
+config BFIN_HYSTERESIS_CONTROL
+        bool "Enable Hysteresis Control"
+        help
+          The ADSP-BF52x allows to control input hysteresis for Port F,
+          Port G and Port H and other processor signal inputs.
+          The Schmitt trigger enables can be set only for pin groups.
+          Saying Y will overwrite the default reset or boot loader
+          initialization.
+
+menu "PORT F"
+        depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTF_0_7
+        bool "Enable Hysteresis on PORTF {0...7}"
+config GPIO_HYST_PORTF_8_9
+        bool "Enable Hysteresis on PORTF {8, 9}"
+config GPIO_HYST_PORTF_10
+        bool "Enable Hysteresis on PORTF 10"
+config GPIO_HYST_PORTF_11
+        bool "Enable Hysteresis on PORTF 11"
+config GPIO_HYST_PORTF_12_13
+        bool "Enable Hysteresis on PORTF {12, 13}"
+config GPIO_HYST_PORTF_14_15
+        bool "Enable Hysteresis on PORTF {14, 15}"
+endmenu
+
+menu "PORT G"
+        depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTG_0
+        bool "Enable Hysteresis on PORTG 0"
+config GPIO_HYST_PORTG_1_4
+        bool "Enable Hysteresis on PORTG {1...4}"
+config GPIO_HYST_PORTG_5_6
+        bool "Enable Hysteresis on PORTG {5, 6}"
+config GPIO_HYST_PORTG_7_8
+        bool "Enable Hysteresis on PORTG {7, 8}"
+config GPIO_HYST_PORTG_9
+        bool "Enable Hysteresis on PORTG 9"
+config GPIO_HYST_PORTG_10
+        bool "Enable Hysteresis on PORTG 10"
+config GPIO_HYST_PORTG_11_13
+        bool "Enable Hysteresis on PORTG {11...13}"
+config GPIO_HYST_PORTG_14_15
+        bool "Enable Hysteresis on PORTG {14, 15}"
+endmenu
+
+menu "PORT H"
+        depends on BFIN_HYSTERESIS_CONTROL
+config GPIO_HYST_PORTH_0_7
+        bool "Enable Hysteresis on PORTH {0...7}"
+config GPIO_HYST_PORTH_8
+        bool "Enable Hysteresis on PORTH 8"
+config GPIO_HYST_PORTH_9_15
+        bool "Enable Hysteresis on PORTH {9...15}"
+endmenu
+
+menu "None-GPIO"
+        depends on BFIN_HYSTERESIS_CONTROL
+config NONEGPIO_HYST_TMR0_FS1_PPICLK
+        bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
+config NONEGPIO_HYST_NMI_RST_BMODE
+        bool "Enable Hysteresis on {NMI, RESET, BMODE}"
+config NONEGPIO_HYST_JTAG
+        bool "Enable Hysteresis on JTAG"
+endmenu
+
 comment "Interrupt Priority Assignment"
 menu "Priority"
 
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 02040df8ec80..9358afa05c90 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
  *  - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
@@ -41,7 +41,7 @@
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)    /* note: brokenness is noted in documentation, not anomaly sheet */
+#define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -168,6 +168,8 @@
 #define ANOMALY_05000431 (1)
 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
 #define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
 #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* Preboot Cannot be Used to Alter the PLL_DIV Register */
@@ -204,10 +206,22 @@
 #define ANOMALY_05000467 (1)
 /* PLL Latches Incorrect Settings During Reset */
 #define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
 /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
 #define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
+#define ANOMALY_05000483 (1)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -223,6 +237,7 @@
 #define ANOMALY_05000198 (0)
 #define ANOMALY_05000202 (0)
 #define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
 #define ANOMALY_05000220 (0)
 #define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
@@ -259,6 +274,5 @@
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index ff68c8897087..8ff155b34f64 100644
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -85,6 +85,126 @@
 
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
 
+/**************************** Hysteresis Settings ****************************/
+
+#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
+#ifdef CONFIG_GPIO_HYST_PORTF_0_7
+#define HYST_PORTF_0_7          (1 << 0)
+#else
+#define HYST_PORTF_0_7          (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_8_9
+#define HYST_PORTF_8_9          (1 << 2)
+#else
+#define HYST_PORTF_8_9          (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_10
+#define HYST_PORTF_10           (1 << 4)
+#else
+#define HYST_PORTF_10           (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_11
+#define HYST_PORTF_11           (1 << 6)
+#else
+#define HYST_PORTF_11           (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_12_13
+#define HYST_PORTF_12_13        (1 << 8)
+#else
+#define HYST_PORTF_12_13        (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTF_14_15
+#define HYST_PORTF_14_15        (1 << 10)
+#else
+#define HYST_PORTF_14_15        (0 << 10)
+#endif
+
+#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
+                HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTG_0
+#define HYST_PORTG_0            (1 << 0)
+#else
+#define HYST_PORTG_0            (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_1_4
+#define HYST_PORTG_1_4          (1 << 2)
+#else
+#define HYST_PORTG_1_4          (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_5_6
+#define HYST_PORTG_5_6          (1 << 4)
+#else
+#define HYST_PORTG_5_6          (0 << 4)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_7_8
+#define HYST_PORTG_7_8          (1 << 6)
+#else
+#define HYST_PORTG_7_8          (0 << 6)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_9
+#define HYST_PORTG_9            (1 << 8)
+#else
+#define HYST_PORTG_9            (0 << 8)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_10
+#define HYST_PORTG_10           (1 << 10)
+#else
+#define HYST_PORTG_10           (0 << 10)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_11_13
+#define HYST_PORTG_11_13        (1 << 12)
+#else
+#define HYST_PORTG_11_13        (0 << 12)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTG_14_15
+#define HYST_PORTG_14_15        (1 << 14)
+#else
+#define HYST_PORTG_14_15        (0 << 14)
+#endif
+
+#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
+                HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
+                HYST_PORTG_11_13 | HYST_PORTG_14_15)
+
+#ifdef CONFIG_GPIO_HYST_PORTH_0_7
+#define HYST_PORTH_0_7          (1 << 0)
+#else
+#define HYST_PORTH_0_7          (0 << 0)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTH_8
+#define HYST_PORTH_8            (1 << 2)
+#else
+#define HYST_PORTH_8            (0 << 2)
+#endif
+#ifdef CONFIG_GPIO_HYST_PORTH_9_15
+#define HYST_PORTH_9_15         (1 << 4)
+#else
+#define HYST_PORTH_9_15         (0 << 4)
+#endif
+
+#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
+
+#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
+#define HYST_TMR0_FS1_PPICLK            (1 << 0)
+#else
+#define HYST_TMR0_FS1_PPICLK            (0 << 0)
+#endif
+#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
+#define HYST_NMI_RST_BMODE              (1 << 2)
+#else
+#define HYST_NMI_RST_BMODE              (0 << 2)
+#endif
+#ifdef CONFIG_NONEGPIO_HYST_JTAG
+#define HYST_JTAG                       (1 << 4)
+#else
+#define HYST_JTAG                       (0 << 4)
+#endif
+
+#define HYST_NONEGPIO   (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
+#define HYST_NONEGPIO_MASK              (0x3F)
+#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
+
 #ifdef CONFIG_BF527
 #define CPU "BF527"
 #define CPUID 0x27e0
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 8b18b5359210..5f97f01fcda6 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -458,22 +458,22 @@
 
 /* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
 #define TWI0_REGBASE                    0xFFC01400
-#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
 
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
@@ -1328,7 +1328,7 @@
 #define TWI_ENA         0x0080          /* TWI Enable                                                                   */
 #define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
 
-/* TWI_SLAVE_CTRL Masks                                                                                                                 */
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
 #define SEN                     0x0001          /* Slave Enable                                                                 */
 #define SADD_LEN        0x0002          /* Slave Address Length                                                 */
 #define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
@@ -1339,7 +1339,7 @@
 #define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
 #define GCALL           0x0002          /* General Call Indicator                                               */
 
-/* TWI_MASTER_CTRL Masks                                                                                                        */
+/* TWI_MASTER_CTL Masks                                                                                                 */
 #define MEN                     0x0001          /* Master Mode Enable                                           */
 #define MADD_LEN        0x0002          /* Master Address Length                                        */
 #define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
@@ -1589,114 +1589,6 @@
 
 #define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
 
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* CNT_COMMAND bit field options */
-
-#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
-#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
-#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
-
-#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
-#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
-#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
-
-#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
-#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
-#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
-
-/* CNT_CONFIG bit field options */
-
-#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
-#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
-#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
-#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
-#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
-
-#define BNDMODE_COMP     0x0000  /* boundary compare mode */
-#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
-#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
-#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
-
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
@@ -1738,85 +1630,4 @@
 #define                   nAFEXIT  0x0
 #define                   SECSTAT  0xe0       /* Secure Status */
 
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0
-#define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0
-#define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0
-#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define             nMASK_WBEMPTY  0x0
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0
-#define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-
 #endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index 104bff85290d..f80c2995efdb 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -9,54 +9,54 @@
 
 #define MAX_BLACKFIN_GPIOS 48
 
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PG0        16
-#define GPIO_PG1        17
-#define GPIO_PG2        18
-#define GPIO_PG3        19
-#define GPIO_PG4        20
-#define GPIO_PG5        21
-#define GPIO_PG6        22
-#define GPIO_PG7        23
-#define GPIO_PG8        24
-#define GPIO_PG9        25
-#define GPIO_PG10       26
-#define GPIO_PG11       27
-#define GPIO_PG12       28
-#define GPIO_PG13       29
-#define GPIO_PG14       30
-#define GPIO_PG15       31
-#define GPIO_PH0        32
-#define GPIO_PH1        33
-#define GPIO_PH2        34
-#define GPIO_PH3        35
-#define GPIO_PH4        36
-#define GPIO_PH5        37
-#define GPIO_PH6        38
-#define GPIO_PH7        39
-#define GPIO_PH8        40
-#define GPIO_PH9        41
-#define GPIO_PH10       42
-#define GPIO_PH11       43
-#define GPIO_PH12       44
-#define GPIO_PH13       45
-#define GPIO_PH14       46
-#define GPIO_PH15       47
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PG0        16
+#define GPIO_PG1        17
+#define GPIO_PG2        18
+#define GPIO_PG3        19
+#define GPIO_PG4        20
+#define GPIO_PG5        21
+#define GPIO_PG6        22
+#define GPIO_PG7        23
+#define GPIO_PG8        24
+#define GPIO_PG9        25
+#define GPIO_PG10       26
+#define GPIO_PG11       27
+#define GPIO_PG12       28
+#define GPIO_PG13       29
+#define GPIO_PG14       30
+#define GPIO_PG15       31
+#define GPIO_PH0        32
+#define GPIO_PH1        33
+#define GPIO_PH2        34
+#define GPIO_PH3        35
+#define GPIO_PH4        36
+#define GPIO_PH5        37
+#define GPIO_PH6        38
+#define GPIO_PH7        39
+#define GPIO_PH8        40
+#define GPIO_PH9        41
+#define GPIO_PH10       42
+#define GPIO_PH11       43
+#define GPIO_PH12       44
+#define GPIO_PH13       45
+#define GPIO_PH14       46
+#define GPIO_PH15       47
 
 #define PORT_F GPIO_PF0
 #define PORT_G GPIO_PG0
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
index d4518b6f4adf..08bae421f5c9 100644
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf527/include/mach/portmux.h
@@ -7,7 +7,7 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
 
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
 
 #define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
 #define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@@ -79,6 +79,7 @@
 
 #define P_HWAIT         (P_DONTCARE)
 
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
 
 #define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))