diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-11-17 10:40:30 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-27 15:58:27 -0400 |
| commit | ac0a5042befbe4396b7650358ad35298512d683d (patch) | |
| tree | ed0ce62c139f88153a4f7acd787e3c82d761298c /arch/blackfin/mach-bf527/include | |
| parent | d4348c678977c7093438bbbf2067c49396ae941b (diff) | |
Blackfin: punt duplicate SPORT MMR defines
The common bfin_sport.h header now has unified definitions of these, so
stop polluting the global namespace.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf527/include')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 5f97f01fcda6..3e000756aacd 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |||
| @@ -922,88 +922,6 @@ | |||
| 922 | #define PH14 0x4000 | 922 | #define PH14 0x4000 |
| 923 | #define PH15 0x8000 | 923 | #define PH15 0x8000 |
| 924 | 924 | ||
| 925 | |||
| 926 | /* ******************* SERIAL PORT MASKS **************************************/ | ||
| 927 | /* SPORTx_TCR1 Masks */ | ||
| 928 | #define TSPEN 0x0001 /* Transmit Enable */ | ||
| 929 | #define ITCLK 0x0002 /* Internal Transmit Clock Select */ | ||
| 930 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 931 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 932 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 933 | #define TLSBIT 0x0010 /* Transmit Bit Order */ | ||
| 934 | #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ | ||
| 935 | #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ | ||
| 936 | #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ | ||
| 937 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | ||
| 938 | #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ | ||
| 939 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 940 | |||
| 941 | /* SPORTx_TCR2 Masks and Macro */ | ||
| 942 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
| 943 | #define TXSE 0x0100 /* TX Secondary Enable */ | ||
| 944 | #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ | ||
| 945 | #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ | ||
| 946 | |||
| 947 | /* SPORTx_RCR1 Masks */ | ||
| 948 | #define RSPEN 0x0001 /* Receive Enable */ | ||
| 949 | #define IRCLK 0x0002 /* Internal Receive Clock Select */ | ||
| 950 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 951 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 952 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 953 | #define RLSBIT 0x0010 /* Receive Bit Order */ | ||
| 954 | #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ | ||
| 955 | #define RFSR 0x0400 /* Receive Frame Sync Required Select */ | ||
| 956 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | ||
| 957 | #define LARFS 0x2000 /* Late Receive Frame Sync Select */ | ||
| 958 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 959 | |||
| 960 | /* SPORTx_RCR2 Masks */ | ||
| 961 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ | ||
| 962 | #define RXSE 0x0100 /* RX Secondary Enable */ | ||
| 963 | #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ | ||
| 964 | #define RRFST 0x0400 /* Right-First Data Order */ | ||
| 965 | |||
| 966 | /* SPORTx_STAT Masks */ | ||
| 967 | #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ | ||
| 968 | #define RUVF 0x0002 /* Sticky Receive Underflow Status */ | ||
| 969 | #define ROVF 0x0004 /* Sticky Receive Overflow Status */ | ||
| 970 | #define TXF 0x0008 /* Transmit FIFO Full Status */ | ||
| 971 | #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ | ||
| 972 | #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ | ||
| 973 | #define TXHRE 0x0040 /* Transmit Hold Register Empty */ | ||
| 974 | |||
| 975 | /* SPORTx_MCMC1 Macros */ | ||
| 976 | #define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
| 977 | |||
| 978 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 979 | #define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 980 | |||
| 981 | /* SPORTx_MCMC2 Masks */ | ||
| 982 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
| 983 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
| 984 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
| 985 | #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ | ||
| 986 | #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ | ||
| 987 | #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ | ||
| 988 | #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ | ||
| 989 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
| 990 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
| 991 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
| 992 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
| 993 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
| 994 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
| 995 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
| 996 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
| 997 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
| 998 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
| 999 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
| 1000 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
| 1001 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
| 1002 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
| 1003 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
| 1004 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
| 1005 | |||
| 1006 | |||
| 1007 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | 925 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ |
| 1008 | /* EBIU_AMGCTL Masks */ | 926 | /* EBIU_AMGCTL Masks */ |
| 1009 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | 927 | #define AMCKEN 0x0001 /* Enable CLKOUT */ |