diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-07-26 18:04:59 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-07-26 18:04:59 -0400 |
commit | d9ecdb282c91952796b7542c4f57fd6de6948d7b (patch) | |
tree | fd4de7923968afa7d2981fb037e2255fc2cfa1e1 /arch/blackfin/mach-bf527/head.S | |
parent | 4ef584ba84125b67c17b5aded38e7783cd8cdef0 (diff) | |
parent | 1d1f8b377c48e5aeddaea52eba74cc0539f088cd (diff) |
Merge branch 'for_rmk_13' of git://git.mnementh.co.uk/linux-2.6-im
Diffstat (limited to 'arch/blackfin/mach-bf527/head.S')
-rw-r--r-- | arch/blackfin/mach-bf527/head.S | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index 57bdb3ba2fed..fe05cc1ef174 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S | |||
@@ -32,7 +32,7 @@ | |||
32 | #include <asm/blackfin.h> | 32 | #include <asm/blackfin.h> |
33 | #include <asm/trace.h> | 33 | #include <asm/trace.h> |
34 | 34 | ||
35 | #if CONFIG_BFIN_KERNEL_CLOCK | 35 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
36 | #include <asm/mach-common/clocks.h> | 36 | #include <asm/mach-common/clocks.h> |
37 | #include <asm/mach/mem_init.h> | 37 | #include <asm/mach/mem_init.h> |
38 | #endif | 38 | #endif |
@@ -185,7 +185,7 @@ ENTRY(__start) | |||
185 | 185 | ||
186 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ | 186 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ |
187 | call _bf53x_relocate_l1_mem; | 187 | call _bf53x_relocate_l1_mem; |
188 | #if CONFIG_BFIN_KERNEL_CLOCK | 188 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
189 | call _start_dma_code; | 189 | call _start_dma_code; |
190 | #endif | 190 | #endif |
191 | 191 | ||
@@ -318,7 +318,7 @@ ENDPROC(_real_start) | |||
318 | __FINIT | 318 | __FINIT |
319 | 319 | ||
320 | .section .l1.text | 320 | .section .l1.text |
321 | #if CONFIG_BFIN_KERNEL_CLOCK | 321 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
322 | ENTRY(_start_dma_code) | 322 | ENTRY(_start_dma_code) |
323 | 323 | ||
324 | /* Enable PHY CLK buffer output */ | 324 | /* Enable PHY CLK buffer output */ |
@@ -398,12 +398,6 @@ ENTRY(_start_dma_code) | |||
398 | w[p0] = r0.l; | 398 | w[p0] = r0.l; |
399 | ssync; | 399 | ssync; |
400 | 400 | ||
401 | p0.l = LO(EBIU_SDBCTL); | ||
402 | p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ | ||
403 | r0 = mem_SDBCTL; | ||
404 | w[p0] = r0.l; | ||
405 | ssync; | ||
406 | |||
407 | P2.H = hi(EBIU_SDGCTL); | 401 | P2.H = hi(EBIU_SDGCTL); |
408 | P2.L = lo(EBIU_SDGCTL); | 402 | P2.L = lo(EBIU_SDGCTL); |
409 | R0 = [P2]; | 403 | R0 = [P2]; |