diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-15 02:47:28 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:53 -0500 |
| commit | a8e8e491686bb34eb5aea37f58c9020f48629237 (patch) | |
| tree | 2d079d743fba65f89f44181670ada148955ec867 /arch/blackfin/mach-bf518 | |
| parent | 761ec44add46d4dfdcb3a0607bfecb4cfc0dc0f0 (diff) | |
Blackfin: unify duplicated power masks
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/blackfin.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 52 |
2 files changed, 0 insertions, 58 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h index 6cfb246aebec..9053462be4b1 100644 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h | |||
| @@ -58,10 +58,4 @@ | |||
| 58 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 58 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
| 59 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 59 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
| 60 | 60 | ||
| 61 | /* PLL_DIV Masks */ | ||
| 62 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | ||
| 63 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | ||
| 64 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | ||
| 65 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | ||
| 66 | |||
| 67 | #endif | 61 | #endif |
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index 78253e838f3d..a97a2bbf9f33 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -585,58 +585,6 @@ | |||
| 585 | ** modifier UNLESS the lower order bits are saved and ORed back in when | 585 | ** modifier UNLESS the lower order bits are saved and ORed back in when |
| 586 | ** the macro is used. | 586 | ** the macro is used. |
| 587 | *************************************************************************************/ | 587 | *************************************************************************************/ |
| 588 | /* | ||
| 589 | ** ********************* PLL AND RESET MASKS ****************************************/ | ||
| 590 | /* PLL_CTL Masks */ | ||
| 591 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
| 592 | #define PLL_OFF 0x0002 /* PLL Not Powered */ | ||
| 593 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
| 594 | #define PDWN 0x0020 /* Enter Deep Sleep Mode */ | ||
| 595 | #define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | ||
| 596 | #define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | ||
| 597 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
| 598 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ | ||
| 599 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | ||
| 600 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
| 601 | |||
| 602 | /* PLL_DIV Masks */ | ||
| 603 | #define SSEL 0x000F /* System Select */ | ||
| 604 | #define CSEL 0x0030 /* Core Select */ | ||
| 605 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ | ||
| 606 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ | ||
| 607 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ | ||
| 608 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ | ||
| 609 | /* PLL_DIV Macros */ | ||
| 610 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
| 611 | |||
| 612 | /* VR_CTL Masks */ | ||
| 613 | #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ | ||
| 614 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
| 615 | |||
| 616 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
| 617 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
| 618 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
| 619 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
| 620 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
| 621 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
| 622 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
| 623 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
| 624 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
| 625 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
| 626 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
| 627 | |||
| 628 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
| 629 | #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ | ||
| 630 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ | ||
| 631 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ | ||
| 632 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ | ||
| 633 | #define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ | ||
| 634 | |||
| 635 | /* PLL_STAT Masks */ | ||
| 636 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
| 637 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
| 638 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
| 639 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
| 640 | 588 | ||
| 641 | /* CHIPID Masks */ | 589 | /* CHIPID Masks */ |
| 642 | #define CHIPID_VERSION 0xF0000000 | 590 | #define CHIPID_VERSION 0xF0000000 |