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authorCliff Cai <cliff.cai@analog.com>2009-03-28 13:03:20 -0400
committerBryan Wu <cooloney@kernel.org>2009-03-28 13:03:20 -0400
commitabd750a0fa731f9fd568526adb96d11322734167 (patch)
tree7432ff6dbc27de629a6f6304e722e27622da2546 /arch/blackfin/mach-bf518
parent4636b3019a76aacc5b01e14bd14cb468fb00940f (diff)
Blackfin arch: add RSI's definitions to bf514 and bf516
Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h67
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h67
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h135
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h135
4 files changed, 404 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index 9521e178fb28..dfe492dfe54e 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -45,4 +45,71 @@
45 45
46/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ 46/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
47 47
48/* Removable Storage Interface Registers */
49
50#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
51#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
52#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
53#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
54#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
55#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
56#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
57#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
58#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
59#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
60#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
61#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
62#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
63#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
64#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
65#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
66#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
67#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
68#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
69#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
70#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
71#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
72#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
73#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
74#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
75#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
76#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
77#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
78#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
79#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
80#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
81#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
82#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
83#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
84#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
85#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
86#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
87#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
88#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
89#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
90#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
91#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
92#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
93#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
94#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
95#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
96#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
97#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
98#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
99#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
100#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
101#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
102#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
103#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
104#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
105#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
106#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
107#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
108#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
109#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
110#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
111#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
112#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
113#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
114
48#endif /* _CDEF_BF514_H */ 115#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 4e26ccfcef97..14df43d4677a 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -210,4 +210,71 @@
210#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) 210#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
211#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) 211#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
212 212
213/* Removable Storage Interface Registers */
214
215#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
216#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
217#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
218#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
219#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
220#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
221#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
222#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
223#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
224#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
225#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
226#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
227#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
228#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
229#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
230#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
231#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
232#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
233#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
234#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
235#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
236#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
237#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
238#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
239#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
240#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
241#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
242#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
243#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
244#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
245#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
246#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
247#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
248#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
249#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
250#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
251#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
252#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
253#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
254#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
255#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
256#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
257#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
258#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
259#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
260#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
261#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
262#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
263#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
264#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
265#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
266#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
267#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
268#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
269#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
270#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
271#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
272#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
273#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
274#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
275#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
276#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
277#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
278#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
279
213#endif /* _CDEF_BF516_H */ 280#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index 543f2913b3f5..56ee5a7c2007 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -110,4 +110,139 @@
110#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 110#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
111#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 111#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
112 112
113/* ********************************************************** */
114/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
115/* and MULTI BIT READ MACROS */
116/* ********************************************************** */
117
118/* Bit masks for SDH_COMMAND */
119
120#define CMD_IDX 0x3f /* Command Index */
121#define CMD_RSP 0x40 /* Response */
122#define CMD_L_RSP 0x80 /* Long Response */
123#define CMD_INT_E 0x100 /* Command Interrupt */
124#define CMD_PEND_E 0x200 /* Command Pending */
125#define CMD_E 0x400 /* Command Enable */
126
127/* Bit masks for SDH_PWR_CTL */
128
129#define PWR_ON 0x3 /* Power On */
130#if 0
131#define TBD 0x3c /* TBD */
132#endif
133#define SD_CMD_OD 0x40 /* Open Drain Output */
134#define ROD_CTL 0x80 /* Rod Control */
135
136/* Bit masks for SDH_CLK_CTL */
137
138#define CLKDIV 0xff /* MC_CLK Divisor */
139#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
140#define PWR_SV_E 0x200 /* Power Save Enable */
141#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
142#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
143
144/* Bit masks for SDH_RESP_CMD */
145
146#define RESP_CMD 0x3f /* Response Command */
147
148/* Bit masks for SDH_DATA_CTL */
149
150#define DTX_E 0x1 /* Data Transfer Enable */
151#define DTX_DIR 0x2 /* Data Transfer Direction */
152#define DTX_MODE 0x4 /* Data Transfer Mode */
153#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
154#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
155
156/* Bit masks for SDH_STATUS */
157
158#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
159#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
160#define CMD_TIME_OUT 0x4 /* CMD Time Out */
161#define DAT_TIME_OUT 0x8 /* Data Time Out */
162#define TX_UNDERRUN 0x10 /* Transmit Underrun */
163#define RX_OVERRUN 0x20 /* Receive Overrun */
164#define CMD_RESP_END 0x40 /* CMD Response End */
165#define CMD_SENT 0x80 /* CMD Sent */
166#define DAT_END 0x100 /* Data End */
167#define START_BIT_ERR 0x200 /* Start Bit Error */
168#define DAT_BLK_END 0x400 /* Data Block End */
169#define CMD_ACT 0x800 /* CMD Active */
170#define TX_ACT 0x1000 /* Transmit Active */
171#define RX_ACT 0x2000 /* Receive Active */
172#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
173#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
174#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
175#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
176#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
177#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
178#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
179#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
180
181/* Bit masks for SDH_STATUS_CLR */
182
183#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
184#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
185#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
186#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
187#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
188#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
189#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
190#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
191#define DAT_END_STAT 0x100 /* Data End Status */
192#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
193#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
194
195/* Bit masks for SDH_MASK0 */
196
197#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
198#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
199#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
200#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
201#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
202#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
203#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
204#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
205#define DAT_END_MASK 0x100 /* Data End Mask */
206#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
207#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
208#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
209#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
210#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
211#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
212#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
213#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
214#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
215#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
216#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
217#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
218#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
219
220/* Bit masks for SDH_FIFO_CNT */
221
222#define FIFO_COUNT 0x7fff /* FIFO Count */
223
224/* Bit masks for SDH_E_STATUS */
225
226#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
227#define SD_CARD_DET 0x10 /* SD Card Detect */
228
229/* Bit masks for SDH_E_MASK */
230
231#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
232#define SCD_MSK 0x40 /* Mask Card Detect */
233
234/* Bit masks for SDH_CFG */
235
236#define CLKS_EN 0x1 /* Clocks Enable */
237#define SD4E 0x4 /* SDIO 4-Bit Enable */
238#define MWE 0x8 /* Moving Window Enable */
239#define SD_RST 0x10 /* SDMMC Reset */
240#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
241#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
242#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
243
244/* Bit masks for SDH_RD_WAIT_EN */
245
246#define RWR 0x1 /* Read Wait Request */
247
113#endif /* _DEF_BF514_H */ 248#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 149a269306c5..dfc93843517d 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -487,4 +487,139 @@
487#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 487#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
488#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 488#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
489 489
490/* ********************************************************** */
491/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
492/* and MULTI BIT READ MACROS */
493/* ********************************************************** */
494
495/* Bit masks for SDH_COMMAND */
496
497#define CMD_IDX 0x3f /* Command Index */
498#define CMD_RSP 0x40 /* Response */
499#define CMD_L_RSP 0x80 /* Long Response */
500#define CMD_INT_E 0x100 /* Command Interrupt */
501#define CMD_PEND_E 0x200 /* Command Pending */
502#define CMD_E 0x400 /* Command Enable */
503
504/* Bit masks for SDH_PWR_CTL */
505
506#define PWR_ON 0x3 /* Power On */
507#if 0
508#define TBD 0x3c /* TBD */
509#endif
510#define SD_CMD_OD 0x40 /* Open Drain Output */
511#define ROD_CTL 0x80 /* Rod Control */
512
513/* Bit masks for SDH_CLK_CTL */
514
515#define CLKDIV 0xff /* MC_CLK Divisor */
516#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
517#define PWR_SV_E 0x200 /* Power Save Enable */
518#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
519#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
520
521/* Bit masks for SDH_RESP_CMD */
522
523#define RESP_CMD 0x3f /* Response Command */
524
525/* Bit masks for SDH_DATA_CTL */
526
527#define DTX_E 0x1 /* Data Transfer Enable */
528#define DTX_DIR 0x2 /* Data Transfer Direction */
529#define DTX_MODE 0x4 /* Data Transfer Mode */
530#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
531#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
532
533/* Bit masks for SDH_STATUS */
534
535#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
536#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
537#define CMD_TIME_OUT 0x4 /* CMD Time Out */
538#define DAT_TIME_OUT 0x8 /* Data Time Out */
539#define TX_UNDERRUN 0x10 /* Transmit Underrun */
540#define RX_OVERRUN 0x20 /* Receive Overrun */
541#define CMD_RESP_END 0x40 /* CMD Response End */
542#define CMD_SENT 0x80 /* CMD Sent */
543#define DAT_END 0x100 /* Data End */
544#define START_BIT_ERR 0x200 /* Start Bit Error */
545#define DAT_BLK_END 0x400 /* Data Block End */
546#define CMD_ACT 0x800 /* CMD Active */
547#define TX_ACT 0x1000 /* Transmit Active */
548#define RX_ACT 0x2000 /* Receive Active */
549#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
550#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
551#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
552#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
553#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
554#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
555#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
556#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
557
558/* Bit masks for SDH_STATUS_CLR */
559
560#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
561#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
562#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
563#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
564#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
565#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
566#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
567#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
568#define DAT_END_STAT 0x100 /* Data End Status */
569#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
570#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
571
572/* Bit masks for SDH_MASK0 */
573
574#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
575#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
576#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
577#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
578#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
579#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
580#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
581#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
582#define DAT_END_MASK 0x100 /* Data End Mask */
583#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
584#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
585#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
586#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
587#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
588#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
589#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
590#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
591#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
592#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
593#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
594#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
595#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
596
597/* Bit masks for SDH_FIFO_CNT */
598
599#define FIFO_COUNT 0x7fff /* FIFO Count */
600
601/* Bit masks for SDH_E_STATUS */
602
603#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
604#define SD_CARD_DET 0x10 /* SD Card Detect */
605
606/* Bit masks for SDH_E_MASK */
607
608#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
609#define SCD_MSK 0x40 /* Mask Card Detect */
610
611/* Bit masks for SDH_CFG */
612
613#define CLKS_EN 0x1 /* Clocks Enable */
614#define SD4E 0x4 /* SDIO 4-Bit Enable */
615#define MWE 0x8 /* Moving Window Enable */
616#define SD_RST 0x10 /* SDMMC Reset */
617#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
618#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
619#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
620
621/* Bit masks for SDH_RD_WAIT_EN */
622
623#define RWR 0x1 /* Read Wait Request */
624
490#endif /* _DEF_BF516_H */ 625#endif /* _DEF_BF516_H */