diff options
| author | Jiri Kosina <jkosina@suse.cz> | 2009-12-07 12:36:35 -0500 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2009-12-07 12:36:35 -0500 |
| commit | d014d043869cdc591f3a33243d3481fa4479c2d0 (patch) | |
| tree | 63626829498e647ba058a1ce06419fe7e4d5f97d /arch/blackfin/mach-bf518 | |
| parent | 6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff) | |
| parent | 6070d81eb5f2d4943223c96e7609a53cdc984364 (diff) | |
Merge branch 'for-next' into for-linus
Conflicts:
kernel/irq/chip.c
Diffstat (limited to 'arch/blackfin/mach-bf518')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index e06f4112c695..f9fd2b2a2956 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -542,7 +542,7 @@ | |||
| 542 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | 542 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ |
| 543 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | 543 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ |
| 544 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | 544 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ |
| 545 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ | 545 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ |
| 546 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ | 546 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ |
| 547 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | 547 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ |
| 548 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | 548 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ |
| @@ -550,7 +550,7 @@ | |||
| 550 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | 550 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ |
| 551 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | 551 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ |
| 552 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | 552 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ |
| 553 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ | 553 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ |
| 554 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ | 554 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ |
| 555 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | 555 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ |
| 556 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | 556 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ |