diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-20 13:20:21 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:59 -0500 |
| commit | 00d2460454676344a55a03f03fa284ad69325592 (patch) | |
| tree | 7885d8dcdeb1ffc026bc4888e1074ce7b8133c7a /arch/blackfin/mach-bf518 | |
| parent | c6feb7682885f732a264ef589ee44edb1a3d45f2 (diff) | |
Blackfin: unify DMA masks
Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index a97a2bbf9f33..9241205fb992 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -1260,33 +1260,6 @@ | |||
| 1260 | 1260 | ||
| 1261 | 1261 | ||
| 1262 | /* ************************** DMA CONTROLLER MASKS ********************************/ | 1262 | /* ************************** DMA CONTROLLER MASKS ********************************/ |
| 1263 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | ||
| 1264 | #define DMAEN 0x0001 /* DMA Channel Enable */ | ||
| 1265 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | ||
| 1266 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ | ||
| 1267 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ | ||
| 1268 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ | ||
| 1269 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ | ||
| 1270 | #define RESTART 0x0020 /* DMA Buffer Clear */ | ||
| 1271 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ | ||
| 1272 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | ||
| 1273 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1274 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1275 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1276 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1277 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1278 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1279 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1280 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1281 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1282 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1283 | #define NDSIZE 0x0900 /* Next Descriptor Size */ | ||
| 1284 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
| 1285 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1286 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1287 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1288 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1289 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1290 | 1263 | ||
| 1291 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | 1264 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ |
| 1292 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | 1265 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ |
| @@ -1304,13 +1277,6 @@ | |||
| 1304 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | 1277 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ |
| 1305 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | 1278 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ |
| 1306 | 1279 | ||
| 1307 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | ||
| 1308 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ | ||
| 1309 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ | ||
| 1310 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | ||
| 1311 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | ||
| 1312 | |||
| 1313 | |||
| 1314 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | 1280 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ |
| 1315 | /* PPI_CONTROL Masks */ | 1281 | /* PPI_CONTROL Masks */ |
| 1316 | #define PORT_EN 0x0001 /* PPI Port Enable */ | 1282 | #define PORT_EN 0x0001 /* PPI Port Enable */ |