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authorMike Frysinger <vapier@gentoo.org>2010-10-25 04:04:44 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:05 -0500
commit9346dba55672a6f04b7bfd1faa081ff149995a3f (patch)
tree78720838d17b73ab0a535fa907df9b805f5a7442 /arch/blackfin/mach-bf518
parent6c8e75a06c8ee32c68ce90afa4a0fe093327b0e4 (diff)
Blackfin: standardize DMAC traffic control MMRs & MDMA MMRs
Use the same naming convention for DMA traffic MMRs (most were legacy anyways) so we can avoid useless ifdef trees. Same goes for MDMA names -- this actually allows us to undo a bunch of ifdef redirects that existed for this purpose alone. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h14
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h8
2 files changed, 6 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index e16969f24ffd..71eff1f13b5e 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -377,16 +377,10 @@
377 377
378 378
379/* DMA Traffic Control Registers */ 379/* DMA Traffic Control Registers */
380#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 380#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
381#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) 381#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
382#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 382#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
383#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) 383#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
384
385/* Alternate deprecated register names (below) provided for backwards code compatibility */
386#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
387#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
388#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
389#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
390 384
391/* DMA Controller */ 385/* DMA Controller */
392#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 386#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index e816c63a5a5f..1ac16e7f7b76 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -215,12 +215,8 @@
215#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 215#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
216 216
217/* DMA Traffic Control Registers */ 217/* DMA Traffic Control Registers */
218#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 218#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
219#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 219#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
220
221/* Alternate deprecated register names (below) provided for backwards code compatibility */
222#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
223#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
224 220
225/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 221/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 222#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */