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authorMike Frysinger <vapier@gentoo.org>2009-09-27 23:16:01 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:02 -0500
commitb1524e29e318e79b2d04bcbd651a7af8dff32bb3 (patch)
tree7e138995fa0f8727b61fdada567cbda3f95e1670 /arch/blackfin/mach-bf518
parent709465d6ea0466454ef547e7d1065db2b23033a9 (diff)
Blackfin: bfin_serial.h: unify heavily duplicated serial code
Each Blackfin port has been duplicating UART structures and defines when there really is no need for it. So start a new bfin_serial.h header to unify all these pieces and give ourselves a fresh start. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h45
4 files changed, 16 insertions, 131 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index 970d310021e7..f6d924ac0c44 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
146}; 75};
147 76
148#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 9053462be4b1..3ddc978bada2 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -43,19 +43,4 @@
43#endif 43#endif
44#endif 44#endif
45 45
46#define BFIN_UART_NR_PORTS 2
47
48#define OFFSET_THR 0x00 /* Transmit Holding register */
49#define OFFSET_RBR 0x00 /* Receive Buffer register */
50#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
51#define OFFSET_IER 0x04 /* Interrupt Enable Register */
52#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
53#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
54#define OFFSET_LCR 0x0C /* Line Control Register */
55#define OFFSET_MCR 0x10 /* Modem Control Register */
56#define OFFSET_LSR 0x14 /* Line Status Register */
57#define OFFSET_MSR 0x18 /* Modem Status Register */
58#define OFFSET_SCR 0x1C /* SCR Scratch Register */
59#define OFFSET_GCTL 0x24 /* Global Control Register */
60
61#endif 46#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 5f84913dcd91..e816c63a5a5f 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -703,51 +703,6 @@
703#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 703#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
705 705
706
707/* ************** UART CONTROLLER MASKS *************************/
708/* UARTx_LCR Masks */
709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
710#define STB 0x04 /* Stop Bits */
711#define PEN 0x08 /* Parity Enable */
712#define EPS 0x10 /* Even Parity Select */
713#define STP 0x20 /* Stick Parity */
714#define SB 0x40 /* Set Break */
715#define DLAB 0x80 /* Divisor Latch Access */
716
717/* UARTx_MCR Mask */
718#define LOOP_ENA 0x10 /* Loopback Mode Enable */
719#define LOOP_ENA_P 0x04
720
721/* UARTx_LSR Masks */
722#define DR 0x01 /* Data Ready */
723#define OE 0x02 /* Overrun Error */
724#define PE 0x04 /* Parity Error */
725#define FE 0x08 /* Framing Error */
726#define BI 0x10 /* Break Interrupt */
727#define THRE 0x20 /* THR Empty */
728#define TEMT 0x40 /* TSR and UART_THR Empty */
729
730/* UARTx_IER Masks */
731#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
732#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
733#define ELSI 0x04 /* Enable RX Status Interrupt */
734
735/* UARTx_IIR Masks */
736#define NINT 0x01 /* Pending Interrupt */
737#define IIR_TX_READY 0x02 /* UART_THR empty */
738#define IIR_RX_READY 0x04 /* Receive data ready */
739#define IIR_LINE_CHANGE 0x06 /* Receive line status */
740#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
741
742/* UARTx_GCTL Masks */
743#define UCEN 0x01 /* Enable UARTx Clocks */
744#define IREN 0x02 /* Enable IrDA Mode */
745#define TPOLC 0x04 /* IrDA TX Polarity Change */
746#define RPOLC 0x08 /* IrDA RX Polarity Change */
747#define FPE 0x10 /* Force Parity Error On Transmit */
748#define FFE 0x20 /* Force Framing Error On Transmit */
749
750
751/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 706/* **************** GENERAL PURPOSE TIMER MASKS **********************/
752/* TIMER_ENABLE Masks */ 707/* TIMER_ENABLE Masks */
753#define TIMEN0 0x0001 /* Enable Timer 0 */ 708#define TIMEN0 0x0001 /* Enable Timer 0 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 10:53:59 -0500