diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2011-11-24 04:40:07 -0500 |
|---|---|---|
| committer | Bob Liu <lliubbo@gmail.com> | 2012-05-21 02:54:21 -0400 |
| commit | c55c89e939f2a0a83d5c61462be554d5d2408178 (patch) | |
| tree | f3fe0781b6bf66acb3fb1a321ff446c240afeb73 /arch/blackfin/mach-bf518 | |
| parent | 2879bb30d788bb3841e2f1675ea7af5204eb171c (diff) | |
blackfin: twi: move twi bit mask macro to twi head file
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-bf518')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF512.h | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h index 729704078cd7..a818bb15cf0d 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h | |||
| @@ -1083,77 +1083,6 @@ | |||
| 1083 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | 1083 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ |
| 1084 | 1084 | ||
| 1085 | 1085 | ||
| 1086 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
| 1087 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 1088 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 1089 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 1090 | |||
| 1091 | /* TWI_PRESCALE Masks */ | ||
| 1092 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 1093 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 1094 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 1095 | |||
| 1096 | /* TWI_SLAVE_CTL Masks */ | ||
| 1097 | #define SEN 0x0001 /* Slave Enable */ | ||
| 1098 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 1099 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 1100 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 1101 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
| 1102 | |||
| 1103 | /* TWI_SLAVE_STAT Masks */ | ||
| 1104 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 1105 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 1106 | |||
| 1107 | /* TWI_MASTER_CTL Masks */ | ||
| 1108 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 1109 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 1110 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 1111 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 1112 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 1113 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 1114 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 1115 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 1116 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 1117 | |||
| 1118 | /* TWI_MASTER_STAT Masks */ | ||
| 1119 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 1120 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 1121 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 1122 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 1123 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 1124 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 1125 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 1126 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 1127 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 1128 | |||
| 1129 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
| 1130 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 1131 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 1132 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 1133 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 1134 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 1135 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 1136 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 1137 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 1138 | |||
| 1139 | /* TWI_FIFO_CTRL Masks */ | ||
| 1140 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 1141 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 1142 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 1143 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 1144 | |||
| 1145 | /* TWI_FIFO_STAT Masks */ | ||
| 1146 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 1147 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 1148 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 1149 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 1150 | |||
| 1151 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 1152 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 1153 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 1154 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 1155 | |||
| 1156 | |||
| 1157 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | 1086 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ |
| 1158 | /* PORT_MUX Masks */ | 1087 | /* PORT_MUX Masks */ |
| 1159 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | 1088 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ |