Blackfin: clean up style in irq defines

These files had a lot of whitespace damage, mostly due to copying and
pasting original files that had damage.

The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so
punt them all.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 109 insertions, 109 deletions

diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index daf1fa5bbb00..edf8efd457dc 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -9,7 +9,7 @@
 
 #include <mach-common/irq.h>
 
-#define NR_PERI_INTS    (2 * 32)
+#define NR_PERI_INTS            (2 * 32)
 
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -25,23 +25,23 @@
 #define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
 #define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
 #define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
+#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
 #define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
 #define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
 #define IRQ_RSI                 BFIN_IRQ(17)    /* DMA 4 Channel (RSI) */
 #define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX/SPI) */
 #define IRQ_SPI1                BFIN_IRQ(18)    /* DMA 5 Channel (SPI1) */
 #define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
+#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
+#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
+#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
+#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
+#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
 #define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
@@ -67,90 +67,90 @@
 #define IRQ_PWM_SYNC            BFIN_IRQ(54)    /* PWM Sync Interrupt */
 #define IRQ_PTP_STAT            BFIN_IRQ(55)    /* PTP Stat Interrupt */
 
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define IRQ_PG0         87
-#define IRQ_PG1         88
-#define IRQ_PG2         89
-#define IRQ_PG3         90
-#define IRQ_PG4         91
-#define IRQ_PG5         92
-#define IRQ_PG6         93
-#define IRQ_PG7         94
-#define IRQ_PG8         95
-#define IRQ_PG9         96
-#define IRQ_PG10        97
-#define IRQ_PG11        98
-#define IRQ_PG12        99
-#define IRQ_PG13        100
-#define IRQ_PG14        101
-#define IRQ_PG15        102
-
-#define IRQ_PH0         103
-#define IRQ_PH1         104
-#define IRQ_PH2         105
-#define IRQ_PH3         106
-#define IRQ_PH4         107
-#define IRQ_PH5         108
-#define IRQ_PH6         109
-#define IRQ_PH7         110
-#define IRQ_PH8         111
-#define IRQ_PH9         112
-#define IRQ_PH10        113
-#define IRQ_PH11        114
-#define IRQ_PH12        115
-#define IRQ_PH13        116
-#define IRQ_PH14        117
-#define IRQ_PH15        118
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define IRQ_MAC_PHYINT          119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT          120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT         121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT         122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET         123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR        124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR        125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE         126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS    (IRQ_MAC_STMDONE + 1)
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+
+#define IRQ_PF0                 71
+#define IRQ_PF1                 72
+#define IRQ_PF2                 73
+#define IRQ_PF3                 74
+#define IRQ_PF4                 75
+#define IRQ_PF5                 76
+#define IRQ_PF6                 77
+#define IRQ_PF7                 78
+#define IRQ_PF8                 79
+#define IRQ_PF9                 80
+#define IRQ_PF10                81
+#define IRQ_PF11                82
+#define IRQ_PF12                83
+#define IRQ_PF13                84
+#define IRQ_PF14                85
+#define IRQ_PF15                86
+
+#define IRQ_PG0                 87
+#define IRQ_PG1                 88
+#define IRQ_PG2                 89
+#define IRQ_PG3                 90
+#define IRQ_PG4                 91
+#define IRQ_PG5                 92
+#define IRQ_PG6                 93
+#define IRQ_PG7                 94
+#define IRQ_PG8                 95
+#define IRQ_PG9                 96
+#define IRQ_PG10                97
+#define IRQ_PG11                98
+#define IRQ_PG12                99
+#define IRQ_PG13                100
+#define IRQ_PG14                101
+#define IRQ_PG15                102
+
+#define IRQ_PH0                 103
+#define IRQ_PH1                 104
+#define IRQ_PH2                 105
+#define IRQ_PH3                 106
+#define IRQ_PH4                 107
+#define IRQ_PH5                 108
+#define IRQ_PH6                 109
+#define IRQ_PH7                 110
+#define IRQ_PH8                 111
+#define IRQ_PH9                 112
+#define IRQ_PH10                113
+#define IRQ_PH11                114
+#define IRQ_PH12                115
+#define IRQ_PH13                116
+#define IRQ_PH14                117
+#define IRQ_PH15                118
+
+#define GPIO_IRQ_BASE           IRQ_PF0
+
+#define IRQ_MAC_PHYINT          119     /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT          120     /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT         121     /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT         122     /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET         123     /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR        124     /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR        125     /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE         126     /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS            (IRQ_MAC_STMDONE + 1)
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
 #define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
+#define IRQ_DMAR0_BLK_POS       8
+#define IRQ_DMAR1_BLK_POS       12
+#define IRQ_DMAR0_OVR_POS       16
+#define IRQ_DMAR1_OVR_POS       20
+#define IRQ_PPI_ERROR_POS       24
+#define IRQ_MAC_ERROR_POS       28
 
 /* IAR1 BIT FIELDS */
 #define IRQ_SPORT0_ERROR_POS    0
 #define IRQ_SPORT1_ERROR_POS    4
 #define IRQ_PTP_ERROR_POS       8
-#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
+#define IRQ_UART0_ERROR_POS     16
+#define IRQ_UART1_ERROR_POS     20
+#define IRQ_RTC_POS             24
+#define IRQ_PPI_POS             28
 
 /* IAR2 BIT FIELDS */
 #define IRQ_SPORT0_RX_POS       0
@@ -159,19 +159,19 @@
 #define IRQ_SPORT1_RX_POS       8
 #define IRQ_SPI1_POS            8
 #define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
-#define IRQ_SPI0_POS            20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
+#define IRQ_TWI_POS             16
+#define IRQ_SPI0_POS            20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
 
 /* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
+#define IRQ_UART1_RX_POS        0
+#define IRQ_UART1_TX_POS        4
+#define IRQ_OPTSEC_POS          8
+#define IRQ_CNT_POS             12
+#define IRQ_MAC_RX_POS          16
 #define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
+#define IRQ_MAC_TX_POS          24
 #define IRQ_PORTH_INTB_POS      28
 
 /* IAR4 BIT FIELDS */
@@ -187,19 +187,19 @@
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0
 #define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
+#define IRQ_MEM_DMA0_POS        8
+#define IRQ_MEM_DMA1_POS        12
+#define IRQ_WATCH_POS           16
 #define IRQ_PORTF_INTA_POS      20
 #define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI0_ERROR_POS      28
+#define IRQ_SPI0_ERROR_POS      28
 
 /* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS      0
-#define IRQ_RSI_INT0_POS        12
-#define IRQ_RSI_INT1_POS        16
-#define IRQ_PWM_TRIP_POS        20
-#define IRQ_PWM_SYNC_POS        24
-#define IRQ_PTP_STAT_POS        28
-
-#endif                          /* _BF518_IRQ_H_ */
+#define IRQ_SPI1_ERROR_POS      0
+#define IRQ_RSI_INT0_POS        12
+#define IRQ_RSI_INT1_POS        16
+#define IRQ_PWM_TRIP_POS        20
+#define IRQ_PWM_SYNC_POS        24
+#define IRQ_PTP_STAT_POS        28
+
+#endif