Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
  Blackfin SPORTS UART Driver: converting BFIN->BLACKFIN
  Blackfin serial driver: add extra IRQ flag for 8250 serial driver
  8250 Serial Driver: Added support for 8250-class UARTs in HV Sistemas H8606 board
  Blackfin arch: Fix bug - USB fails to build for BF524/BF526
  Blackfin arch: update boards defconfig files
  Blackfin arch: IO Port functions to read/write unalligned memory
  Blackfin arch: enable a choice to provide 4M DMA memory
  Blackfin arch: cleanup the icplb/dcplb multiple hit checks
  Blackfin arch: Add workaround to read edge triggered GPIOs
  Blackfin arch: Sync channel defines with struct dma_register dma_io_base_addr.
  Blackfin arch: Check for Anomaly 05000182
  [Blackfin] arch: rename bf5xx-flash to bfin-async-flash
  [Blackfin] arch: Blackfin checksum annotations

1 files changed, 18 insertions, 3 deletions

diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index df7b8833a0c5..eba2343b1b59 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -7,7 +7,7 @@
  * Description:  Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
  *
  * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2004-2008 Analog Devices Inc.
  *               Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
  *
  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
@@ -63,6 +63,23 @@ ENTRY(_insw)
         RTS;
 ENDPROC(_insw)
 
+ENTRY(_insw_8)
+        P0 = R0;        /* P0 = port */
+        cli R3;
+        P1 = R1;        /* P1 = address */
+        P2 = R2;        /* P2 = count */
+        SSYNC;
+        LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
+.Lword8_loop_s:  R0 = W[P0];
+                B[P1++] = R0;
+                R0 = R0 >> 8;
+                B[P1++] = R0;
+                NOP;
+.Lword8_loop_e: NOP;
+        sti R3;
+        RTS;
+ENDPROC(_insw_8)
+
 ENTRY(_insb)
         P0 = R0;        /* P0 = port */
         cli R3;
@@ -78,8 +95,6 @@ ENTRY(_insb)
         RTS;
 ENDPROC(_insb)
 
-
-
 ENTRY(_insl_16)
         P0 = R0;        /* P0 = port */
         cli R3;