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authorMike Frysinger <michael.frysinger@analog.com>2007-06-11 03:31:30 -0400
committerBryan Wu <bryan.wu@analog.com>2007-06-11 03:31:30 -0400
commit51be24c351bc9ee4937121100adb098eeb1effdd (patch)
treeb766c400cab7c51bfc7672cfbc3402bc83be5fb3 /arch/blackfin/lib/divsi3.S
parent52a078120c33b06a9abb721357adaafc3b55b7c1 (diff)
Blackfin arch: add proper ENDPROC()
add proper ENDPROC() to close out assembly functions so size/type is set properly in the final ELF image Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/lib/divsi3.S')
-rw-r--r--arch/blackfin/lib/divsi3.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
index 3e29861852b2..2ac59c70dd94 100644
--- a/arch/blackfin/lib/divsi3.S
+++ b/arch/blackfin/lib/divsi3.S
@@ -44,6 +44,7 @@
44 */ 44 */
45 45
46.global ___divsi3; 46.global ___divsi3;
47.type ___divsi3, STT_FUNC;
47 48
48#ifdef CONFIG_ARITHMETIC_OPS_L1 49#ifdef CONFIG_ARITHMETIC_OPS_L1
49.section .l1.text 50.section .l1.text
@@ -214,3 +215,5 @@ ___divsi3 :
214.Lret_zero: 215.Lret_zero:
215 R0 = 0; 216 R0 = 0;
216 RTS; 217 RTS;
218
219.size ___divsi3, .-___divsi3