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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /arch/blackfin/kernel
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/kernel')
-rw-r--r--arch/blackfin/kernel/Makefile5
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c205
-rw-r--r--arch/blackfin/kernel/setup.c3
3 files changed, 6 insertions, 207 deletions
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f3b7d2f9d49c..93d21406cade 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -6,9 +6,10 @@ extra-y := init_task.o vmlinux.lds
6 6
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \ 9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o
10 flat.o
11 10
11obj-$(CONFIG_BF53x) += bfin_gpio.o
12obj-$(CONFIG_BF561) += bfin_gpio.o
12obj-$(CONFIG_MODULES) += module.o 13obj-$(CONFIG_MODULES) += module.o
13obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o 14obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
14obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o 15obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 069a896a8f26..8a16c2bbec04 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -34,6 +34,7 @@
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/param.h> 35#include <linux/param.h>
36 36
37#include <asm/blackfin.h>
37#include <asm/dma.h> 38#include <asm/dma.h>
38#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
39 40
@@ -45,67 +46,6 @@
45***************************************************************************/ 46***************************************************************************/
46 47
47static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; 48static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
48#if defined (CONFIG_BF561)
49static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
50 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
51 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
52 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
53 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
54 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
55 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
56 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
57 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
58 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
59 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
60 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
61 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
62 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
63 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
64 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
65 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
66 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
67 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
68 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
69 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
70 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
71 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
72 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
73 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
74 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
75 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
76 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
77 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
78 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
79 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
80 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
81 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
82 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
83 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
84 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
85 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
86};
87#else
88static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
89 (struct dma_register *) DMA0_NEXT_DESC_PTR,
90 (struct dma_register *) DMA1_NEXT_DESC_PTR,
91 (struct dma_register *) DMA2_NEXT_DESC_PTR,
92 (struct dma_register *) DMA3_NEXT_DESC_PTR,
93 (struct dma_register *) DMA4_NEXT_DESC_PTR,
94 (struct dma_register *) DMA5_NEXT_DESC_PTR,
95 (struct dma_register *) DMA6_NEXT_DESC_PTR,
96 (struct dma_register *) DMA7_NEXT_DESC_PTR,
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
98 (struct dma_register *) DMA8_NEXT_DESC_PTR,
99 (struct dma_register *) DMA9_NEXT_DESC_PTR,
100 (struct dma_register *) DMA10_NEXT_DESC_PTR,
101 (struct dma_register *) DMA11_NEXT_DESC_PTR,
102#endif
103 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
104 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
105 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
106 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
107};
108#endif
109 49
110/*------------------------------------------------------------------------------ 50/*------------------------------------------------------------------------------
111 * Set the Buffer Clear bit in the Configuration register of specific DMA 51 * Set the Buffer Clear bit in the Configuration register of specific DMA
@@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
138 78
139arch_initcall(blackfin_dma_init); 79arch_initcall(blackfin_dma_init);
140 80
141/*
142 * Form the channel find the irq number for that channel.
143 */
144#if !defined(CONFIG_BF561)
145
146static int bf533_channel2irq(unsigned int channel)
147{
148 int ret_irq = -1;
149
150 switch (channel) {
151 case CH_PPI:
152 ret_irq = IRQ_PPI;
153 break;
154
155#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
156 case CH_EMAC_RX:
157 ret_irq = IRQ_MAC_RX;
158 break;
159
160 case CH_EMAC_TX:
161 ret_irq = IRQ_MAC_TX;
162 break;
163
164 case CH_UART1_RX:
165 ret_irq = IRQ_UART1_RX;
166 break;
167
168 case CH_UART1_TX:
169 ret_irq = IRQ_UART1_TX;
170 break;
171#endif
172
173 case CH_SPORT0_RX:
174 ret_irq = IRQ_SPORT0_RX;
175 break;
176
177 case CH_SPORT0_TX:
178 ret_irq = IRQ_SPORT0_TX;
179 break;
180
181 case CH_SPORT1_RX:
182 ret_irq = IRQ_SPORT1_RX;
183 break;
184
185 case CH_SPORT1_TX:
186 ret_irq = IRQ_SPORT1_TX;
187 break;
188
189 case CH_SPI:
190 ret_irq = IRQ_SPI;
191 break;
192
193 case CH_UART_RX:
194 ret_irq = IRQ_UART_RX;
195 break;
196
197 case CH_UART_TX:
198 ret_irq = IRQ_UART_TX;
199 break;
200
201 case CH_MEM_STREAM0_SRC:
202 case CH_MEM_STREAM0_DEST:
203 ret_irq = IRQ_MEM_DMA0;
204 break;
205
206 case CH_MEM_STREAM1_SRC:
207 case CH_MEM_STREAM1_DEST:
208 ret_irq = IRQ_MEM_DMA1;
209 break;
210 }
211 return ret_irq;
212}
213
214# define channel2irq(channel) bf533_channel2irq(channel)
215
216#else
217
218static int bf561_channel2irq(unsigned int channel)
219{
220 int ret_irq = -1;
221
222 switch (channel) {
223 case CH_PPI0:
224 ret_irq = IRQ_PPI0;
225 break;
226 case CH_PPI1:
227 ret_irq = IRQ_PPI1;
228 break;
229 case CH_SPORT0_RX:
230 ret_irq = IRQ_SPORT0_RX;
231 break;
232 case CH_SPORT0_TX:
233 ret_irq = IRQ_SPORT0_TX;
234 break;
235 case CH_SPORT1_RX:
236 ret_irq = IRQ_SPORT1_RX;
237 break;
238 case CH_SPORT1_TX:
239 ret_irq = IRQ_SPORT1_TX;
240 break;
241 case CH_SPI:
242 ret_irq = IRQ_SPI;
243 break;
244 case CH_UART_RX:
245 ret_irq = IRQ_UART_RX;
246 break;
247 case CH_UART_TX:
248 ret_irq = IRQ_UART_TX;
249 break;
250
251 case CH_MEM_STREAM0_SRC:
252 case CH_MEM_STREAM0_DEST:
253 ret_irq = IRQ_MEM_DMA0;
254 break;
255 case CH_MEM_STREAM1_SRC:
256 case CH_MEM_STREAM1_DEST:
257 ret_irq = IRQ_MEM_DMA1;
258 break;
259 case CH_MEM_STREAM2_SRC:
260 case CH_MEM_STREAM2_DEST:
261 ret_irq = IRQ_MEM_DMA2;
262 break;
263 case CH_MEM_STREAM3_SRC:
264 case CH_MEM_STREAM3_DEST:
265 ret_irq = IRQ_MEM_DMA3;
266 break;
267
268 case CH_IMEM_STREAM0_SRC:
269 case CH_IMEM_STREAM0_DEST:
270 ret_irq = IRQ_IMEM_DMA0;
271 break;
272 case CH_IMEM_STREAM1_SRC:
273 case CH_IMEM_STREAM1_DEST:
274 ret_irq = IRQ_IMEM_DMA1;
275 break;
276 }
277 return ret_irq;
278}
279
280# define channel2irq(channel) bf561_channel2irq(channel)
281
282#endif
283
284/*------------------------------------------------------------------------------ 81/*------------------------------------------------------------------------------
285 * Request the specific DMA channel from the system. 82 * Request the specific DMA channel from the system.
286 *-----------------------------------------------------------------------------*/ 83 *-----------------------------------------------------------------------------*/
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 83060f98d15d..76bf2cea61d7 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -500,8 +500,9 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i,
500 cplb_data[i].end, 500 cplb_data[i].end,
501 SIZE_4M, 501 SIZE_4M,
502 cplb_data[i].i_conf); 502 cplb_data[i].i_conf);
503 } else { 503 } else
504#endif 504#endif
505 {
505 fill_cplbtab(t, 506 fill_cplbtab(t,
506 cplb_data[i].start, 507 cplb_data[i].start,
507 a_start, 508 a_start,