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authorMike Frysinger <vapier.adi@gmail.com>2008-08-13 04:16:11 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-13 04:16:11 -0400
commit07aa7be5708afb3d9afa68f6f853c98e51bc64b3 (patch)
tree808fe87c382fb0a1b9432c75989da81f7f9efdd1 /arch/blackfin/kernel
parent17e89bcfa12f71b840361da07fe6c2f9c48d0605 (diff)
Blackfin arch: convert L2 defines to be the same as the L1 defines
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel')
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c6
-rw-r--r--arch/blackfin/kernel/setup.c14
-rw-r--r--arch/blackfin/kernel/traps.c2
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S10
4 files changed, 13 insertions, 19 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 224e7cc30bc5..728f708d3981 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -164,17 +164,13 @@ static struct cplb_desc cplb_data[] = {
164 .name = "Asynchronous Memory Banks", 164 .name = "Asynchronous Memory Banks",
165 }, 165 },
166 { 166 {
167#ifdef L2_START
168 .start = L2_START, 167 .start = L2_START,
169 .end = L2_START + L2_LENGTH, 168 .end = L2_START + L2_LENGTH,
170 .psize = SIZE_1M, 169 .psize = SIZE_1M,
171 .attr = SWITCH_T | I_CPLB | D_CPLB, 170 .attr = SWITCH_T | I_CPLB | D_CPLB,
172 .i_conf = L2_MEMORY, 171 .i_conf = L2_MEMORY,
173 .d_conf = L2_MEMORY, 172 .d_conf = L2_MEMORY,
174 .valid = 1, 173 .valid = (L2_LENGTH > 0),
175#else
176 .valid = 0,
177#endif
178 .name = "L2 Memory", 174 .name = "L2 Memory",
179 }, 175 },
180 { 176 {
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 15967e7578cd..936c06d820de 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -131,14 +131,14 @@ void __init bf53x_relocate_l1_mem(void)
131 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + 131 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
132 l1_data_a_length, l1_data_b_length); 132 l1_data_a_length, l1_data_b_length);
133 133
134#ifdef L2_LENGTH 134 if (L2_LENGTH != 0) {
135 l2_length = _ebss_l2 - _stext_l2; 135 l2_length = _ebss_l2 - _stext_l2;
136 if (l2_length > L2_LENGTH) 136 if (l2_length > L2_LENGTH)
137 panic("L2 SRAM Overflow\n"); 137 panic("L2 SRAM Overflow\n");
138 138
139 /* Copy _stext_l2 to _edata_l2 to L2 SRAM */ 139 /* Copy _stext_l2 to _edata_l2 to L2 SRAM */
140 dma_memcpy(_stext_l2, _l2_lma_start, l2_length); 140 dma_memcpy(_stext_l2, _l2_lma_start, l2_length);
141#endif 141 }
142} 142}
143 143
144/* add_memory_region to memmap */ 144/* add_memory_region to memmap */
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index ad922ab91543..62a47d67d876 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -567,7 +567,7 @@ bool get_instruction(unsigned short *val, unsigned short *address)
567 * we don't read something in the async space that can hang forever 567 * we don't read something in the async space that can hang forever
568 */ 568 */
569 if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) || 569 if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) ||
570#ifdef L2_START 570#if L2_LENGTH != 0
571 (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) || 571 (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) ||
572#endif 572#endif
573 (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) || 573 (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) ||
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index d062597e6217..7d12c6692a65 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -102,7 +102,7 @@ SECTIONS
102#if !L1_DATA_B_LENGTH 102#if !L1_DATA_B_LENGTH
103 *(.l1.data.B) 103 *(.l1.data.B)
104#endif 104#endif
105#ifndef L2_LENGTH 105#if !L2_LENGTH
106 . = ALIGN(32); 106 . = ALIGN(32);
107 *(.data_l2.cacheline_aligned) 107 *(.data_l2.cacheline_aligned)
108 *(.l2.data) 108 *(.l2.data)
@@ -212,20 +212,19 @@ SECTIONS
212 __ebss_b_l1 = .; 212 __ebss_b_l1 = .;
213 } 213 }
214 214
215#ifdef L2_LENGTH
216 __l2_lma_start = .; 215 __l2_lma_start = .;
217 216
218 .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) 217 .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1))
219 { 218 {
220 . = ALIGN(4); 219 . = ALIGN(4);
221 __stext_l2 = .; 220 __stext_l2 = .;
222 *(.l1.text) 221 *(.l2.text)
223 . = ALIGN(4); 222 . = ALIGN(4);
224 __etext_l2 = .; 223 __etext_l2 = .;
225 224
226 . = ALIGN(4); 225 . = ALIGN(4);
227 __sdata_l2 = .; 226 __sdata_l2 = .;
228 *(.l1.data) 227 *(.l2.data)
229 __edata_l2 = .; 228 __edata_l2 = .;
230 229
231 . = ALIGN(32); 230 . = ALIGN(32);
@@ -233,11 +232,10 @@ SECTIONS
233 232
234 . = ALIGN(4); 233 . = ALIGN(4);
235 __sbss_l2 = .; 234 __sbss_l2 = .;
236 *(.l1.bss) 235 *(.l2.bss)
237 . = ALIGN(4); 236 . = ALIGN(4);
238 __ebss_l2 = .; 237 __ebss_l2 = .;
239 } 238 }
240#endif
241 239
242 /* Force trailing alignment of our init section so that when we 240 /* Force trailing alignment of our init section so that when we
243 * free our init memory, we don't leave behind a partial page. 241 * free our init memory, we don't leave behind a partial page.