Blackfin: use on-chip reset func with newer parts

Turns out the documentation is wrong and doing "RAISE 1" does not result
in a software reset, only a core reset.  So when the on-chip rom has a
functioning reset helper, use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 31 insertions, 34 deletions

diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 53d08dee8531..488bdc51aaa5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -23,6 +23,9 @@
 __attribute__ ((__l1_text__, __noreturn__))
 static void bfin_reset(void)
 {
+        if (!ANOMALY_05000353 && !ANOMALY_05000386)
+                bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
+
         /* Wait for completion of "system" events such as cache line
          * line fills so that we avoid infinite stalls later on as
          * much as possible.  This code is in L1, so it won't trigger
@@ -30,46 +33,40 @@ static void bfin_reset(void)
          */
         __builtin_bfin_ssync();
 
-        /* The bootrom checks to see how it was reset and will
-         * automatically perform a software reset for us when
-         * it starts executing after the core reset.
-         */
-        if (ANOMALY_05000353 || ANOMALY_05000386) {
-                /* Initiate System software reset. */
-                bfin_write_SWRST(0x7);
+        /* Initiate System software reset. */
+        bfin_write_SWRST(0x7);
 
-                /* Due to the way reset is handled in the hardware, we need
-                 * to delay for 10 SCLKS.  The only reliable way to do this is
-                 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-                 * we'll assume worse case which is a 1:15 ratio.
-                 */
-                asm(
-                        "LSETUP (1f, 1f) LC0 = %0\n"
-                        "1: nop;"
-                        :
-                        : "a" (15 * 10)
-                        : "LC0", "LB0", "LT0"
-                );
+        /* Due to the way reset is handled in the hardware, we need
+         * to delay for 10 SCLKS.  The only reliable way to do this is
+         * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+         * we'll assume worse case which is a 1:15 ratio.
+         */
+        asm(
+                "LSETUP (1f, 1f) LC0 = %0\n"
+                "1: nop;"
+                :
+                : "a" (15 * 10)
+                : "LC0", "LB0", "LT0"
+        );
 
-                /* Clear System software reset */
-                bfin_write_SWRST(0);
+        /* Clear System software reset */
+        bfin_write_SWRST(0);
 
-                /* The BF526 ROM will crash during reset */
+        /* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-                bfin_read_SWRST();
+        bfin_read_SWRST();
 #endif
 
-                /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-                 * though as the System state is all reset now.
-                 */
-                asm(
-                        "LSETUP (1f, 1f) LC1 = %0\n"
-                        "1: nop;"
-                        :
-                        : "a" (15 * 1)
-                        : "LC1", "LB1", "LT1"
-                );
-        }
+        /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+         * though as the System state is all reset now.
+         */
+        asm(
+                "LSETUP (1f, 1f) LC1 = %0\n"
+                "1: nop;"
+                :
+                : "a" (15 * 1)
+                : "LC1", "LB1", "LT1"
+        );
 
         while (1)
                 /* Issue core reset */