diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-10-09 05:32:28 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-10-09 05:32:28 -0400 |
commit | 0c0497c257c12c9ecb8825490a339bfce8a0532f (patch) | |
tree | 5ed9776845a63b56119b602237889e881a6dc856 /arch/blackfin/kernel/setup.c | |
parent | 664d0403f96ff5f4fb43a4b3a54b5642589c57d2 (diff) |
Blackfin arch: Move all the silicon rev handling to one place
Move all the silicon rev handling to one place (Kconfig) and
make sure we warn if you are running on silicon that has not been tested on
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/setup.c')
-rw-r--r-- | arch/blackfin/kernel/setup.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index e9054e0b4555..4267523912bd 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
@@ -821,9 +821,10 @@ void __init setup_arch(char **cmdline_p) | |||
821 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", | 821 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
822 | bfin_compiled_revid(), bfin_revid()); | 822 | bfin_compiled_revid(), bfin_revid()); |
823 | } | 823 | } |
824 | if (bfin_revid() < SUPPORTED_REVID) | 824 | if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
825 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", | 825 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
826 | CPU, bfin_revid()); | 826 | CPU, bfin_revid()); |
827 | |||
827 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); | 828 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
828 | 829 | ||
829 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", | 830 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |