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authorRobin Getz <robin.getz@analog.com>2010-03-28 08:50:53 -0400
committerMike Frysinger <vapier@gentoo.org>2010-05-22 14:19:05 -0400
commitdc89d97fc73176c883b32ff21ae6f1164ca20d05 (patch)
treebf96980105a75e89ebc0a61bf008e41434c2f819 /arch/blackfin/kernel/pseudodbg.c
parent6a4110c2b38da51b767e389a6fb477072cf5843c (diff)
Blackfin: add support for the DBG (debug output) pseudo insn
Another pseudo insn used by Blackfin simulators. Also factor some now common register lookup code out of the DBGA handlers. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/kernel/pseudodbg.c')
-rw-r--r--arch/blackfin/kernel/pseudodbg.c86
1 files changed, 68 insertions, 18 deletions
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
index 4474b8db3501..a5a4636124aa 100644
--- a/arch/blackfin/kernel/pseudodbg.c
+++ b/arch/blackfin/kernel/pseudodbg.c
@@ -9,6 +9,30 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/ptrace.h> 10#include <linux/ptrace.h>
11 11
12/*
13 * Unfortunately, the pt_regs structure is not laid out the same way as the
14 * hardware register file, so we need to do some fix ups.
15 */
16static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
17{
18 long *val = &fp->r0;
19
20 /* Only do Dregs and Pregs for now */
21 if (grp > 1)
22 return false;
23
24 if (grp == 0 || (grp == 1 && reg < 6))
25 val -= (reg + 8 * grp);
26 else if (grp == 1 && reg == 6)
27 val = &fp->usp;
28 else if (grp == 1 && reg == 7)
29 val = &fp->fp;
30
31 *value = *val;
32 return true;
33
34}
35
12#define PseudoDbg_Assert_opcode 0xf0000000 36#define PseudoDbg_Assert_opcode 0xf0000000
13#define PseudoDbg_Assert_expected_bits 0 37#define PseudoDbg_Assert_expected_bits 0
14#define PseudoDbg_Assert_expected_mask 0xffff 38#define PseudoDbg_Assert_expected_mask 0xffff
@@ -23,47 +47,38 @@
23#define PseudoDbg_Assert_code_bits 27 47#define PseudoDbg_Assert_code_bits 27
24#define PseudoDbg_Assert_code_mask 0x1f 48#define PseudoDbg_Assert_code_mask 0x1f
25 49
50/*
51 * DBGA - debug assert
52 */
26bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode) 53bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
27{ 54{
28 int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); 55 int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
29 int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask); 56 int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
30 int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask); 57 int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
31 int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask); 58 int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
32 long *value = &fp->r0; 59 long value;
33 60
34 if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode) 61 if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
35 return false; 62 return false;
36 63
37 /* Only do Dregs and Pregs for now */ 64 if (!fix_up_reg(fp, &value, grp, regtest))
38 if (grp > 1)
39 return false; 65 return false;
40 66
41 /*
42 * Unfortunately, the pt_regs structure is not laid out the same way as the
43 * hardware register file, so we need to do some fix ups.
44 */
45 if (grp == 0 || (grp == 1 && regtest < 6))
46 value -= (regtest + 8 * grp);
47 else if (grp == 1 && regtest == 6)
48 value = &fp->usp;
49 else if (grp == 1 && regtest == 7)
50 value = &fp->fp;
51
52 if (dbgop == 0 || dbgop == 2) { 67 if (dbgop == 0 || dbgop == 2) {
53 /* DBGA ( regs_lo , uimm16 ) */ 68 /* DBGA ( regs_lo , uimm16 ) */
54 /* DBGAL ( regs , uimm16 ) */ 69 /* DBGAL ( regs , uimm16 ) */
55 if (expected != (*value & 0xFFFF)) { 70 if (expected != (value & 0xFFFF)) {
56 pr_notice("DBGA (%s%i.L,0x%x) failure, got 0x%x\n", grp ? "P" : "R", 71 pr_notice("DBGA (%s%i.L,0x%x) failure, got 0x%x\n", grp ? "P" : "R",
57 regtest, expected, (unsigned int)(*value & 0xFFFF)); 72 regtest, expected, (unsigned int)(value & 0xFFFF));
58 return false; 73 return false;
59 } 74 }
60 75
61 } else if (dbgop == 1 || dbgop == 3) { 76 } else if (dbgop == 1 || dbgop == 3) {
62 /* DBGA ( regs_hi , uimm16 ) */ 77 /* DBGA ( regs_hi , uimm16 ) */
63 /* DBGAH ( regs , uimm16 ) */ 78 /* DBGAH ( regs , uimm16 ) */
64 if (expected != ((*value >> 16) & 0xFFFF)) { 79 if (expected != ((value >> 16) & 0xFFFF)) {
65 pr_notice("DBGA (%s%i.H,0x%x) failure, got 0x%x\n", grp ? "P" : "R", 80 pr_notice("DBGA (%s%i.H,0x%x) failure, got 0x%x\n", grp ? "P" : "R",
66 regtest, expected, (unsigned int)((*value >> 16) & 0xFFFF)); 81 regtest, expected, (unsigned int)((value >> 16) & 0xFFFF));
67 return false; 82 return false;
68 } 83 }
69 } 84 }
@@ -71,3 +86,38 @@ bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
71 fp->pc += 4; 86 fp->pc += 4;
72 return true; 87 return true;
73} 88}
89
90#define PseudoDbg_opcode 0xf8000000
91#define PseudoDbg_reg_bits 0
92#define PseudoDbg_reg_mask 0x7
93#define PseudoDbg_grp_bits 3
94#define PseudoDbg_grp_mask 0x7
95#define PseudoDbg_fn_bits 6
96#define PseudoDbg_fn_mask 0x3
97#define PseudoDbg_code_bits 8
98#define PseudoDbg_code_mask 0xff
99
100/*
101 * DBG - debug (dump a register value out)
102 */
103bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
104{
105 int grp, fn, reg;
106 long value;
107
108 if ((opcode & 0xFF000000) != PseudoDbg_opcode)
109 return false;
110
111 opcode >>= 16;
112 grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
113 fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
114 reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
115
116 if (!fix_up_reg(fp, &value, grp, reg))
117 return false;
118
119 pr_notice("DBG %s%d = %08lx\n", grp ? "P" : "R", reg, value);
120
121 fp->pc += 2;
122 return true;
123}