diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-11-18 04:48:22 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 04:48:22 -0500 |
commit | 09c1db922dd5b41e6421a5a7a94c1282ee881e81 (patch) | |
tree | 2bc6a4c29e5ee4874c21e1f9265cd7a3ee3c1abd /arch/blackfin/kernel/kgdb.c | |
parent | bda07aac9db0d5eb2d6fbe83b99e070b58820dcf (diff) |
Blackfin arch: delete unused vars and add parenthesis to fixup warnings
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/kgdb.c')
-rw-r--r-- | arch/blackfin/kernel/kgdb.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index 85d0ebcb4e1a..a895927fcc30 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c | |||
@@ -382,10 +382,8 @@ int kgdb_arch_handle_exception(int vector, int signo, | |||
382 | struct pt_regs *regs) | 382 | struct pt_regs *regs) |
383 | { | 383 | { |
384 | long addr; | 384 | long addr; |
385 | long breakno; | ||
386 | char *ptr; | 385 | char *ptr; |
387 | int newPC; | 386 | int newPC; |
388 | int wp_status; | ||
389 | int i; | 387 | int i; |
390 | 388 | ||
391 | switch (remcom_in_buffer[0]) { | 389 | switch (remcom_in_buffer[0]) { |
@@ -568,12 +566,12 @@ int kgdb_mem2hex(char *mem, char *buf, int count) | |||
568 | default: | 566 | default: |
569 | err = EFAULT; | 567 | err = EFAULT; |
570 | } | 568 | } |
571 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 569 | } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && |
572 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH | 570 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH) |
573 | #ifdef CONFIG_SMP | 571 | #ifdef CONFIG_SMP |
574 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 572 | || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && |
575 | (unsigned int)(mem + count) <= | 573 | (unsigned int)(mem + count) <= |
576 | COREB_L1_CODE_START + L1_CODE_LENGTH | 574 | COREB_L1_CODE_START + L1_CODE_LENGTH) |
577 | #endif | 575 | #endif |
578 | ) { | 576 | ) { |
579 | /* access L1 instruction SRAM*/ | 577 | /* access L1 instruction SRAM*/ |
@@ -644,12 +642,12 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) | |||
644 | default: | 642 | default: |
645 | return EFAULT; | 643 | return EFAULT; |
646 | } | 644 | } |
647 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 645 | } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && |
648 | (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH | 646 | (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH) |
649 | #ifdef CONFIG_SMP | 647 | #ifdef CONFIG_SMP |
650 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 648 | || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && |
651 | (unsigned int)(mem + count) <= | 649 | (unsigned int)(mem + count) <= |
652 | COREB_L1_CODE_START + L1_CODE_LENGTH | 650 | COREB_L1_CODE_START + L1_CODE_LENGTH) |
653 | #endif | 651 | #endif |
654 | ) { | 652 | ) { |
655 | /* access L1 instruction SRAM */ | 653 | /* access L1 instruction SRAM */ |
@@ -709,12 +707,12 @@ int kgdb_hex2mem(char *buf, char *mem, int count) | |||
709 | default: | 707 | default: |
710 | return EFAULT; | 708 | return EFAULT; |
711 | } | 709 | } |
712 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 710 | } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && |
713 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH | 711 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH) |
714 | #ifdef CONFIG_SMP | 712 | #ifdef CONFIG_SMP |
715 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 713 | || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && |
716 | (unsigned int)(mem + count) <= | 714 | (unsigned int)(mem + count) <= |
717 | COREB_L1_CODE_START + L1_CODE_LENGTH | 715 | COREB_L1_CODE_START + L1_CODE_LENGTH) |
718 | #endif | 716 | #endif |
719 | ) { | 717 | ) { |
720 | /* access L1 instruction SRAM */ | 718 | /* access L1 instruction SRAM */ |