Blackfin arch: Make L2 SRAM cacheable

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 2c45c16c3520..301252e84441 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -168,8 +168,8 @@ static struct cplb_desc cplb_data[] = {
                 .end = L2_START + L2_LENGTH,
                 .psize = SIZE_1M,
                 .attr = SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = L2_MEMORY,
-                .d_conf = L2_MEMORY,
+                .i_conf = L2_IMEMORY,
+                .d_conf = L2_DMEMORY,
                 .valid = (L2_LENGTH > 0),
                 .name = "L2 Memory",
         },