diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-09-07 02:19:51 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-09-07 02:19:51 -0400 |
commit | a1922ed661ab2c1637d0b10cde933bd9cd33d965 (patch) | |
tree | 0f1777542b385ebefd30b3586d830fd8ed6fda5b /arch/blackfin/kernel/cplb-nompu/cplbinit.c | |
parent | 75e33751ca8bbb72dd6f1a74d2810ddc8cbe4bdf (diff) | |
parent | d28daf923ac5e4a0d7cecebae56f3e339189366b (diff) |
Merge branch 'tracing/core' into tracing/hw-breakpoints
Conflicts:
arch/Kconfig
kernel/trace/trace.h
Merge reason: resolve the conflicts, plus adopt to the new
ring-buffer APIs.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu/cplbinit.c')
-rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index d6c067782e63..685f160a5a36 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c | |||
@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
72 | } | 72 | } |
73 | 73 | ||
74 | /* Cover L1 memory. One 4M area for code and data each is enough. */ | 74 | /* Cover L1 memory. One 4M area for code and data each is enough. */ |
75 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { | 75 | if (cpu == 0) { |
76 | d_tbl[i_d].addr = L1_DATA_A_START; | 76 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { |
77 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | 77 | d_tbl[i_d].addr = L1_DATA_A_START; |
78 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | ||
79 | } | ||
80 | i_tbl[i_i].addr = L1_CODE_START; | ||
81 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | ||
78 | } | 82 | } |
79 | i_tbl[i_i].addr = L1_CODE_START; | 83 | #ifdef CONFIG_SMP |
80 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | 84 | else { |
81 | 85 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { | |
86 | d_tbl[i_d].addr = COREB_L1_DATA_A_START; | ||
87 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | ||
88 | } | ||
89 | i_tbl[i_i].addr = COREB_L1_CODE_START; | ||
90 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | ||
91 | } | ||
92 | #endif | ||
82 | first_switched_dcplb = i_d; | 93 | first_switched_dcplb = i_d; |
83 | first_switched_icplb = i_i; | 94 | first_switched_icplb = i_i; |
84 | 95 | ||