diff options
author | Sonic Zhang <sonic.zhang@analog.com> | 2012-07-04 07:21:51 -0400 |
---|---|---|
committer | Bob Liu <lliubbo@gmail.com> | 2012-07-24 01:39:52 -0400 |
commit | 2a26a2055259862e771cb922aee3d1196040c205 (patch) | |
tree | 98cdc83acd9af80a25de1994fe3c254d26f57bc5 /arch/blackfin/include | |
parent | 00afdbbfaf07baf62a31920862128e55842f07dc (diff) |
bf60x: update anomaly id in serial and twi driver headers.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r-- | arch/blackfin/include/asm/bfin_serial.h | 2 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin_twi.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 8597158010b5..2d90d62edc97 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h | |||
@@ -282,7 +282,7 @@ struct bfin_uart_regs { | |||
282 | #define UART_GET_GCTL(p) UART_GET_CTL(p) | 282 | #define UART_GET_GCTL(p) UART_GET_CTL(p) |
283 | #define UART_GET_LCR(p) UART_GET_CTL(p) | 283 | #define UART_GET_LCR(p) UART_GET_CTL(p) |
284 | #define UART_GET_MCR(p) UART_GET_CTL(p) | 284 | #define UART_GET_MCR(p) UART_GET_CTL(p) |
285 | #if ANOMALY_05001001 | 285 | #if ANOMALY_16000030 |
286 | #define UART_GET_STAT(p) \ | 286 | #define UART_GET_STAT(p) \ |
287 | ({ \ | 287 | ({ \ |
288 | u32 __ret; \ | 288 | u32 __ret; \ |
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index e3b40e2856f2..c0fe66257773 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h | |||
@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) | |||
84 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) | 84 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) |
85 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) | 85 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) |
86 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) | 86 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) |
87 | #if !ANOMALY_05001001 | 87 | #if !ANOMALY_16000030 |
88 | DEFINE_TWI_REG(RCV_DATA8, rcv_data8) | 88 | DEFINE_TWI_REG(RCV_DATA8, rcv_data8) |
89 | DEFINE_TWI_REG(RCV_DATA16, rcv_data16) | 89 | DEFINE_TWI_REG(RCV_DATA16, rcv_data16) |
90 | #else | 90 | #else |