diff options
author | Graf Yang <graf.yang@analog.com> | 2009-06-18 00:32:04 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-22 21:16:12 -0400 |
commit | ee48efb5dc45aeb9786dea6469d3e1bea5105036 (patch) | |
tree | 0dfab212febc247f6670f89cd79f85ad754273cc /arch/blackfin/include | |
parent | 8f580f7c82ed9edeb3629568aabcde2caff3f236 (diff) |
Blackfin: bf526-ezbrd: handle different SDRAM chips
The BF526-EZBRD changed SDRAM chips between board revisions, so create a
timing table that can accommodate both.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r-- | arch/blackfin/include/asm/mem_init.h | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index fc164b35a9c5..4179e329b9c9 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h | |||
@@ -89,6 +89,85 @@ | |||
89 | #endif | 89 | #endif |
90 | #endif | 90 | #endif |
91 | 91 | ||
92 | /* | ||
93 | * The BF526-EZ-Board changed SDRAM chips between revisions, | ||
94 | * so we use below timings to accommodate both. | ||
95 | */ | ||
96 | #if defined(CONFIG_MEM_MT48H32M16LFCJ_75) | ||
97 | #if (CONFIG_SCLK_HZ > 119402985) | ||
98 | #define SDRAM_tRP TRP_2 | ||
99 | #define SDRAM_tRP_num 2 | ||
100 | #define SDRAM_tRAS TRAS_8 | ||
101 | #define SDRAM_tRAS_num 8 | ||
102 | #define SDRAM_tRCD TRCD_2 | ||
103 | #define SDRAM_tWR TWR_2 | ||
104 | #endif | ||
105 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
106 | #define SDRAM_tRP TRP_2 | ||
107 | #define SDRAM_tRP_num 2 | ||
108 | #define SDRAM_tRAS TRAS_7 | ||
109 | #define SDRAM_tRAS_num 7 | ||
110 | #define SDRAM_tRCD TRCD_2 | ||
111 | #define SDRAM_tWR TWR_2 | ||
112 | #endif | ||
113 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
114 | #define SDRAM_tRP TRP_2 | ||
115 | #define SDRAM_tRP_num 2 | ||
116 | #define SDRAM_tRAS TRAS_6 | ||
117 | #define SDRAM_tRAS_num 6 | ||
118 | #define SDRAM_tRCD TRCD_2 | ||
119 | #define SDRAM_tWR TWR_2 | ||
120 | #endif | ||
121 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
122 | #define SDRAM_tRP TRP_2 | ||
123 | #define SDRAM_tRP_num 2 | ||
124 | #define SDRAM_tRAS TRAS_5 | ||
125 | #define SDRAM_tRAS_num 5 | ||
126 | #define SDRAM_tRCD TRCD_2 | ||
127 | #define SDRAM_tWR TWR_2 | ||
128 | #endif | ||
129 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
130 | #define SDRAM_tRP TRP_2 | ||
131 | #define SDRAM_tRP_num 2 | ||
132 | #define SDRAM_tRAS TRAS_4 | ||
133 | #define SDRAM_tRAS_num 4 | ||
134 | #define SDRAM_tRCD TRCD_2 | ||
135 | #define SDRAM_tWR TWR_2 | ||
136 | #endif | ||
137 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
138 | #define SDRAM_tRP TRP_2 | ||
139 | #define SDRAM_tRP_num 2 | ||
140 | #define SDRAM_tRAS TRAS_4 | ||
141 | #define SDRAM_tRAS_num 4 | ||
142 | #define SDRAM_tRCD TRCD_1 | ||
143 | #define SDRAM_tWR TWR_2 | ||
144 | #endif | ||
145 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
146 | #define SDRAM_tRP TRP_2 | ||
147 | #define SDRAM_tRP_num 2 | ||
148 | #define SDRAM_tRAS TRAS_3 | ||
149 | #define SDRAM_tRAS_num 3 | ||
150 | #define SDRAM_tRCD TRCD_1 | ||
151 | #define SDRAM_tWR TWR_2 | ||
152 | #endif | ||
153 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
154 | #define SDRAM_tRP TRP_1 | ||
155 | #define SDRAM_tRP_num 1 | ||
156 | #define SDRAM_tRAS TRAS_3 | ||
157 | #define SDRAM_tRAS_num 3 | ||
158 | #define SDRAM_tRCD TRCD_1 | ||
159 | #define SDRAM_tWR TWR_2 | ||
160 | #endif | ||
161 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
162 | #define SDRAM_tRP TRP_1 | ||
163 | #define SDRAM_tRP_num 1 | ||
164 | #define SDRAM_tRAS TRAS_2 | ||
165 | #define SDRAM_tRAS_num 2 | ||
166 | #define SDRAM_tRCD TRCD_1 | ||
167 | #define SDRAM_tWR TWR_2 | ||
168 | #endif | ||
169 | #endif | ||
170 | |||
92 | #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ | 171 | #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ |
93 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) | 172 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) |
94 | /*SDRAM INFORMATION: */ | 173 | /*SDRAM INFORMATION: */ |
@@ -109,6 +188,13 @@ | |||
109 | #define SDRAM_CL CL_3 | 188 | #define SDRAM_CL CL_3 |
110 | #endif | 189 | #endif |
111 | 190 | ||
191 | #if defined(CONFIG_MEM_MT48H32M16LFCJ_75) | ||
192 | /*SDRAM INFORMATION: */ | ||
193 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
194 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
195 | #define SDRAM_CL CL_2 | ||
196 | #endif | ||
197 | |||
112 | 198 | ||
113 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC | 199 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC |
114 | /* Equation from section 17 (p17-46) of BF533 HRM */ | 200 | /* Equation from section 17 (p17-46) of BF533 HRM */ |