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authorBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
commit639f6571458948b5112be2cf00c0c2c04db2897d (patch)
treea4dd7af33d0e92c935ba1e904f6fb7e923ac825e /arch/blackfin/include
parent3d9b7a5ce534f3963afcf8f4777267e5899fe007 (diff)
Blackfin arch: move include/asm-blackfin header files to arch/blackfin
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r--arch/blackfin/include/asm/.gitignore1
-rw-r--r--arch/blackfin/include/asm/Kbuild3
-rw-r--r--arch/blackfin/include/asm/a.out.h19
-rw-r--r--arch/blackfin/include/asm/atomic.h144
-rw-r--r--arch/blackfin/include/asm/auxvec.h4
-rw-r--r--arch/blackfin/include/asm/bfin-global.h117
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h137
-rw-r--r--arch/blackfin/include/asm/bfin_simple_timer.h13
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h175
-rw-r--r--arch/blackfin/include/asm/bitops.h218
-rw-r--r--arch/blackfin/include/asm/blackfin.h92
-rw-r--r--arch/blackfin/include/asm/bug.h17
-rw-r--r--arch/blackfin/include/asm/bugs.h16
-rw-r--r--arch/blackfin/include/asm/byteorder.h48
-rw-r--r--arch/blackfin/include/asm/cache.h29
-rw-r--r--arch/blackfin/include/asm/cacheflush.h90
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h328
-rw-r--r--arch/blackfin/include/asm/checksum.h100
-rw-r--r--arch/blackfin/include/asm/clocks.h70
-rw-r--r--arch/blackfin/include/asm/context.S355
-rw-r--r--arch/blackfin/include/asm/cplb-mpu.h61
-rw-r--r--arch/blackfin/include/asm/cplb.h110
-rw-r--r--arch/blackfin/include/asm/cplbinit.h95
-rw-r--r--arch/blackfin/include/asm/cpumask.h6
-rw-r--r--arch/blackfin/include/asm/cputime.h6
-rw-r--r--arch/blackfin/include/asm/current.h23
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h712
-rw-r--r--arch/blackfin/include/asm/delay.h62
-rw-r--r--arch/blackfin/include/asm/device.h7
-rw-r--r--arch/blackfin/include/asm/div64.h1
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h83
-rw-r--r--arch/blackfin/include/asm/dma.h205
-rw-r--r--arch/blackfin/include/asm/dpmc.h57
-rw-r--r--arch/blackfin/include/asm/early_printk.h28
-rw-r--r--arch/blackfin/include/asm/elf.h127
-rw-r--r--arch/blackfin/include/asm/emergency-restart.h6
-rw-r--r--arch/blackfin/include/asm/entry.h61
-rw-r--r--arch/blackfin/include/asm/errno.h6
-rw-r--r--arch/blackfin/include/asm/fb.h12
-rw-r--r--arch/blackfin/include/asm/fcntl.h13
-rw-r--r--arch/blackfin/include/asm/fixed_code.h46
-rw-r--r--arch/blackfin/include/asm/flat.h58
-rw-r--r--arch/blackfin/include/asm/futex.h6
-rw-r--r--arch/blackfin/include/asm/gpio.h456
-rw-r--r--arch/blackfin/include/asm/gptimers.h191
-rw-r--r--arch/blackfin/include/asm/hardirq.h45
-rw-r--r--arch/blackfin/include/asm/hw_irq.h6
-rw-r--r--arch/blackfin/include/asm/io.h212
-rw-r--r--arch/blackfin/include/asm/ioctl.h1
-rw-r--r--arch/blackfin/include/asm/ioctls.h87
-rw-r--r--arch/blackfin/include/asm/ipcbuf.h30
-rw-r--r--arch/blackfin/include/asm/irq.h72
-rw-r--r--arch/blackfin/include/asm/irq_handler.h33
-rw-r--r--arch/blackfin/include/asm/irq_regs.h1
-rw-r--r--arch/blackfin/include/asm/kdebug.h1
-rw-r--r--arch/blackfin/include/asm/kgdb.h184
-rw-r--r--arch/blackfin/include/asm/kmap_types.h21
-rw-r--r--arch/blackfin/include/asm/l1layout.h31
-rw-r--r--arch/blackfin/include/asm/linkage.h7
-rw-r--r--arch/blackfin/include/asm/local.h6
-rw-r--r--arch/blackfin/include/asm/mem_map.h12
-rw-r--r--arch/blackfin/include/asm/mman.h43
-rw-r--r--arch/blackfin/include/asm/mmu.h32
-rw-r--r--arch/blackfin/include/asm/mmu_context.h183
-rw-r--r--arch/blackfin/include/asm/module.h20
-rw-r--r--arch/blackfin/include/asm/msgbuf.h31
-rw-r--r--arch/blackfin/include/asm/mutex.h9
-rw-r--r--arch/blackfin/include/asm/nand.h47
-rw-r--r--arch/blackfin/include/asm/page.h88
-rw-r--r--arch/blackfin/include/asm/page_offset.h6
-rw-r--r--arch/blackfin/include/asm/param.h22
-rw-r--r--arch/blackfin/include/asm/pci.h148
-rw-r--r--arch/blackfin/include/asm/percpu.h6
-rw-r--r--arch/blackfin/include/asm/pgalloc.h8
-rw-r--r--arch/blackfin/include/asm/pgtable.h96
-rw-r--r--arch/blackfin/include/asm/poll.h24
-rw-r--r--arch/blackfin/include/asm/portmux.h1188
-rw-r--r--arch/blackfin/include/asm/posix_types.h61
-rw-r--r--arch/blackfin/include/asm/processor.h158
-rw-r--r--arch/blackfin/include/asm/ptrace.h168
-rw-r--r--arch/blackfin/include/asm/reboot.h20
-rw-r--r--arch/blackfin/include/asm/resource.h6
-rw-r--r--arch/blackfin/include/asm/scatterlist.h28
-rw-r--r--arch/blackfin/include/asm/sections.h7
-rw-r--r--arch/blackfin/include/asm/segment.h7
-rw-r--r--arch/blackfin/include/asm/sembuf.h25
-rw-r--r--arch/blackfin/include/asm/serial.h5
-rw-r--r--arch/blackfin/include/asm/setup.h17
-rw-r--r--arch/blackfin/include/asm/shmbuf.h42
-rw-r--r--arch/blackfin/include/asm/shmparam.h6
-rw-r--r--arch/blackfin/include/asm/sigcontext.h55
-rw-r--r--arch/blackfin/include/asm/siginfo.h35
-rw-r--r--arch/blackfin/include/asm/signal.h160
-rw-r--r--arch/blackfin/include/asm/socket.h56
-rw-r--r--arch/blackfin/include/asm/sockios.h13
-rw-r--r--arch/blackfin/include/asm/spinlock.h6
-rw-r--r--arch/blackfin/include/asm/stat.h63
-rw-r--r--arch/blackfin/include/asm/statfs.h6
-rw-r--r--arch/blackfin/include/asm/string.h137
-rw-r--r--arch/blackfin/include/asm/system.h221
-rw-r--r--arch/blackfin/include/asm/termbits.h198
-rw-r--r--arch/blackfin/include/asm/termios.h94
-rw-r--r--arch/blackfin/include/asm/thread_info.h135
-rw-r--r--arch/blackfin/include/asm/time.h40
-rw-r--r--arch/blackfin/include/asm/timex.h23
-rw-r--r--arch/blackfin/include/asm/tlb.h16
-rw-r--r--arch/blackfin/include/asm/tlbflush.h56
-rw-r--r--arch/blackfin/include/asm/topology.h6
-rw-r--r--arch/blackfin/include/asm/trace.h94
-rw-r--r--arch/blackfin/include/asm/traps.h131
-rw-r--r--arch/blackfin/include/asm/types.h36
-rw-r--r--arch/blackfin/include/asm/uaccess.h271
-rw-r--r--arch/blackfin/include/asm/ucontext.h17
-rw-r--r--arch/blackfin/include/asm/unaligned.h11
-rw-r--r--arch/blackfin/include/asm/unistd.h438
-rw-r--r--arch/blackfin/include/asm/user.h89
116 files changed, 10071 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/.gitignore b/arch/blackfin/include/asm/.gitignore
new file mode 100644
index 000000000000..7858564a4466
--- /dev/null
+++ b/arch/blackfin/include/asm/.gitignore
@@ -0,0 +1 @@
+mach
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
new file mode 100644
index 000000000000..606ecfdcc962
--- /dev/null
+++ b/arch/blackfin/include/asm/Kbuild
@@ -0,0 +1,3 @@
1include include/asm-generic/Kbuild.asm
2
3unifdef-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/a.out.h b/arch/blackfin/include/asm/a.out.h
new file mode 100644
index 000000000000..6c3d652ebd33
--- /dev/null
+++ b/arch/blackfin/include/asm/a.out.h
@@ -0,0 +1,19 @@
1#ifndef __BFIN_A_OUT_H__
2#define __BFIN_A_OUT_H__
3
4struct exec {
5 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
6 unsigned a_text; /* length of text, in bytes */
7 unsigned a_data; /* length of data, in bytes */
8 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
9 unsigned a_syms; /* length of symbol table data in file, in bytes */
10 unsigned a_entry; /* start address */
11 unsigned a_trsize; /* length of relocation info for text, in bytes */
12 unsigned a_drsize; /* length of relocation info for data, in bytes */
13};
14
15#define N_TRSIZE(a) ((a).a_trsize)
16#define N_DRSIZE(a) ((a).a_drsize)
17#define N_SYMSIZE(a) ((a).a_syms)
18
19#endif /* __BFIN_A_OUT_H__ */
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
new file mode 100644
index 000000000000..7cf508718605
--- /dev/null
+++ b/arch/blackfin/include/asm/atomic.h
@@ -0,0 +1,144 @@
1#ifndef __ARCH_BLACKFIN_ATOMIC__
2#define __ARCH_BLACKFIN_ATOMIC__
3
4#include <asm/system.h> /* local_irq_XXX() */
5
6/*
7 * Atomic operations that C can't guarantee us. Useful for
8 * resource counting etc..
9 *
10 * Generally we do not concern about SMP BFIN systems, so we don't have
11 * to deal with that.
12 *
13 * Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001
14 */
15
16typedef struct {
17 int counter;
18} atomic_t;
19#define ATOMIC_INIT(i) { (i) }
20
21#define atomic_read(v) ((v)->counter)
22#define atomic_set(v, i) (((v)->counter) = i)
23
24static __inline__ void atomic_add(int i, atomic_t * v)
25{
26 long flags;
27
28 local_irq_save(flags);
29 v->counter += i;
30 local_irq_restore(flags);
31}
32
33static __inline__ void atomic_sub(int i, atomic_t * v)
34{
35 long flags;
36
37 local_irq_save(flags);
38 v->counter -= i;
39 local_irq_restore(flags);
40
41}
42
43static inline int atomic_add_return(int i, atomic_t * v)
44{
45 int __temp = 0;
46 long flags;
47
48 local_irq_save(flags);
49 v->counter += i;
50 __temp = v->counter;
51 local_irq_restore(flags);
52
53
54 return __temp;
55}
56
57#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
58static inline int atomic_sub_return(int i, atomic_t * v)
59{
60 int __temp = 0;
61 long flags;
62
63 local_irq_save(flags);
64 v->counter -= i;
65 __temp = v->counter;
66 local_irq_restore(flags);
67
68 return __temp;
69}
70
71static __inline__ void atomic_inc(volatile atomic_t * v)
72{
73 long flags;
74
75 local_irq_save(flags);
76 v->counter++;
77 local_irq_restore(flags);
78}
79
80#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
81#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
82
83#define atomic_add_unless(v, a, u) \
84({ \
85 int c, old; \
86 c = atomic_read(v); \
87 while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
88 c = old; \
89 c != (u); \
90})
91#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
92
93static __inline__ void atomic_dec(volatile atomic_t * v)
94{
95 long flags;
96
97 local_irq_save(flags);
98 v->counter--;
99 local_irq_restore(flags);
100}
101
102static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
103{
104 long flags;
105
106 local_irq_save(flags);
107 v->counter &= ~mask;
108 local_irq_restore(flags);
109}
110
111static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
112{
113 long flags;
114
115 local_irq_save(flags);
116 v->counter |= mask;
117 local_irq_restore(flags);
118}
119
120/* Atomic operations are already serializing */
121#define smp_mb__before_atomic_dec() barrier()
122#define smp_mb__after_atomic_dec() barrier()
123#define smp_mb__before_atomic_inc() barrier()
124#define smp_mb__after_atomic_inc() barrier()
125
126#define atomic_dec_return(v) atomic_sub_return(1,(v))
127#define atomic_inc_return(v) atomic_add_return(1,(v))
128
129/*
130 * atomic_inc_and_test - increment and test
131 * @v: pointer of type atomic_t
132 *
133 * Atomically increments @v by 1
134 * and returns true if the result is zero, or false for all
135 * other cases.
136 */
137#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
138
139#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
140#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
141
142#include <asm-generic/atomic.h>
143
144#endif /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h
new file mode 100644
index 000000000000..215506cd87b7
--- /dev/null
+++ b/arch/blackfin/include/asm/auxvec.h
@@ -0,0 +1,4 @@
1#ifndef __ASMBFIN_AUXVEC_H
2#define __ASMBFIN_AUXVEC_H
3
4#endif
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
new file mode 100644
index 000000000000..7ba70de66f2b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -0,0 +1,117 @@
1/*
2 * File: include/asm-blackfin/bfin-global.h
3 * Based on:
4 * Author: *
5 * Created:
6 * Description: Global extern defines for blackfin
7 *
8 * Modified:
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 */
28
29#ifndef _BFIN_GLOBAL_H_
30#define _BFIN_GLOBAL_H_
31
32#ifndef __ASSEMBLY__
33
34#include <asm-generic/sections.h>
35#include <asm/ptrace.h>
36#include <asm/user.h>
37#include <linux/linkage.h>
38#include <linux/types.h>
39
40#if defined(CONFIG_DMA_UNCACHED_4M)
41# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
42#elif defined(CONFIG_DMA_UNCACHED_2M)
43# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
44#elif defined(CONFIG_DMA_UNCACHED_1M)
45# define DMA_UNCACHED_REGION (1024 * 1024)
46#else
47# define DMA_UNCACHED_REGION (0)
48#endif
49
50extern unsigned long get_cclk(void);
51extern unsigned long get_sclk(void);
52extern unsigned long sclk_to_usecs(unsigned long sclk);
53extern unsigned long usecs_to_sclk(unsigned long usecs);
54
55extern void dump_bfin_process(struct pt_regs *regs);
56extern void dump_bfin_mem(struct pt_regs *regs);
57extern void dump_bfin_trace_buffer(void);
58
59/* init functions only */
60extern int init_arch_irq(void);
61extern void bfin_icache_init(void);
62extern void bfin_dcache_init(void);
63extern void init_exception_vectors(void);
64extern void program_IAR(void);
65
66extern void bfin_reset(void);
67extern asmlinkage void lower_to_irq14(void);
68extern asmlinkage void bfin_return_from_exception(void);
69extern asmlinkage void evt14_softirq(void);
70extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
71extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
72
73extern void *l1_data_A_sram_alloc(size_t);
74extern void *l1_data_B_sram_alloc(size_t);
75extern void *l1_inst_sram_alloc(size_t);
76extern void *l1_data_sram_alloc(size_t);
77extern void *l1_data_sram_zalloc(size_t);
78extern void *l2_sram_alloc(size_t);
79extern void *l2_sram_zalloc(size_t);
80extern int l1_data_A_sram_free(const void*);
81extern int l1_data_B_sram_free(const void*);
82extern int l1_inst_sram_free(const void*);
83extern int l1_data_sram_free(const void*);
84extern int l2_sram_free(const void *);
85extern int sram_free(const void*);
86
87#define L1_INST_SRAM 0x00000001
88#define L1_DATA_A_SRAM 0x00000002
89#define L1_DATA_B_SRAM 0x00000004
90#define L1_DATA_SRAM 0x00000006
91#define L2_SRAM 0x00000008
92extern void *sram_alloc_with_lsl(size_t, unsigned long);
93extern int sram_free_with_lsl(const void*);
94
95extern const char bfin_board_name[];
96
97extern unsigned long bfin_sic_iwr[];
98extern unsigned vr_wakeup;
99extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
100extern unsigned long _ramstart, _ramend, _rambase;
101extern unsigned long memory_start, memory_end, physical_mem_end;
102extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
103 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[],
104 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
105 _ebss_l2[], _l2_lma_start[];
106
107/* only used when CONFIG_MTD_UCLINUX */
108extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
109
110#ifdef CONFIG_BFIN_ICACHE_LOCK
111extern void cache_grab_lock(int way);
112extern void cache_lock(int way);
113#endif
114
115#endif
116
117#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
new file mode 100644
index 000000000000..9fa19158e38d
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -0,0 +1,137 @@
1/************************************************************
2
3* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
4*
5* FILE bfin5xx_spi.h
6* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
7*
8*
9* DATE OF CREATION: March. 10th 2006
10*
11* SYNOPSIS:
12*
13* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
14**************************************************************
15
16* MODIFICATION HISTORY:
17* March 10, 2006 bfin5xx_spi.h Created. (Luke Yang)
18
19************************************************************/
20
21#ifndef _SPI_CHANNEL_H_
22#define _SPI_CHANNEL_H_
23
24#define SPI_READ 0
25#define SPI_WRITE 1
26
27#define SPI_CTRL_OFF 0x0
28#define SPI_FLAG_OFF 0x4
29#define SPI_STAT_OFF 0x8
30#define SPI_TXBUFF_OFF 0xc
31#define SPI_RXBUFF_OFF 0x10
32#define SPI_BAUD_OFF 0x14
33#define SPI_SHAW_OFF 0x18
34
35
36#define BIT_CTL_ENABLE 0x4000
37#define BIT_CTL_OPENDRAIN 0x2000
38#define BIT_CTL_MASTER 0x1000
39#define BIT_CTL_POLAR 0x0800
40#define BIT_CTL_PHASE 0x0400
41#define BIT_CTL_BITORDER 0x0200
42#define BIT_CTL_WORDSIZE 0x0100
43#define BIT_CTL_MISOENABLE 0x0020
44#define BIT_CTL_RXMOD 0x0000
45#define BIT_CTL_TXMOD 0x0001
46#define BIT_CTL_TIMOD_DMA_TX 0x0003
47#define BIT_CTL_TIMOD_DMA_RX 0x0002
48#define BIT_CTL_SENDOPT 0x0004
49#define BIT_CTL_TIMOD 0x0003
50
51#define BIT_STAT_SPIF 0x0001
52#define BIT_STAT_MODF 0x0002
53#define BIT_STAT_TXE 0x0004
54#define BIT_STAT_TXS 0x0008
55#define BIT_STAT_RBSY 0x0010
56#define BIT_STAT_RXS 0x0020
57#define BIT_STAT_TXCOL 0x0040
58#define BIT_STAT_CLR 0xFFFF
59
60#define BIT_STU_SENDOVER 0x0001
61#define BIT_STU_RECVFULL 0x0020
62
63#define CFG_SPI_ENABLE 1
64#define CFG_SPI_DISABLE 0
65
66#define CFG_SPI_OUTENABLE 1
67#define CFG_SPI_OUTDISABLE 0
68
69#define CFG_SPI_ACTLOW 1
70#define CFG_SPI_ACTHIGH 0
71
72#define CFG_SPI_PHASESTART 1
73#define CFG_SPI_PHASEMID 0
74
75#define CFG_SPI_MASTER 1
76#define CFG_SPI_SLAVE 0
77
78#define CFG_SPI_SENELAST 0
79#define CFG_SPI_SENDZERO 1
80
81#define CFG_SPI_RCVFLUSH 1
82#define CFG_SPI_RCVDISCARD 0
83
84#define CFG_SPI_LSBFIRST 1
85#define CFG_SPI_MSBFIRST 0
86
87#define CFG_SPI_WORDSIZE16 1
88#define CFG_SPI_WORDSIZE8 0
89
90#define CFG_SPI_MISOENABLE 1
91#define CFG_SPI_MISODISABLE 0
92
93#define CFG_SPI_READ 0x00
94#define CFG_SPI_WRITE 0x01
95#define CFG_SPI_DMAREAD 0x02
96#define CFG_SPI_DMAWRITE 0x03
97
98#define CFG_SPI_CSCLEARALL 0
99#define CFG_SPI_CHIPSEL1 1
100#define CFG_SPI_CHIPSEL2 2
101#define CFG_SPI_CHIPSEL3 3
102#define CFG_SPI_CHIPSEL4 4
103#define CFG_SPI_CHIPSEL5 5
104#define CFG_SPI_CHIPSEL6 6
105#define CFG_SPI_CHIPSEL7 7
106
107#define CFG_SPI_CS1VALUE 1
108#define CFG_SPI_CS2VALUE 2
109#define CFG_SPI_CS3VALUE 3
110#define CFG_SPI_CS4VALUE 4
111#define CFG_SPI_CS5VALUE 5
112#define CFG_SPI_CS6VALUE 6
113#define CFG_SPI_CS7VALUE 7
114
115#define CMD_SPI_SET_BAUDRATE 2
116#define CMD_SPI_GET_SYSTEMCLOCK 25
117#define CMD_SPI_SET_WRITECONTINUOUS 26
118
119/* device.platform_data for SSP controller devices */
120struct bfin5xx_spi_master {
121 u16 num_chipselect;
122 u8 enable_dma;
123 u16 pin_req[4];
124};
125
126/* spi_board_info.controller_data for SPI slave devices,
127 * copied to spi_device.platform_data ... mostly for dma tuning
128 */
129struct bfin5xx_spi_chip {
130 u16 ctl_reg;
131 u8 enable_dma;
132 u8 bits_per_word;
133 u8 cs_change_per_word;
134 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
135};
136
137#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
new file mode 100644
index 000000000000..fccbb595464a
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_simple_timer.h
@@ -0,0 +1,13 @@
1#ifndef _bfin_simple_timer_h_
2#define _bfin_simple_timer_h_
3
4#include <linux/ioctl.h>
5
6#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
7
8#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
9#define BFIN_SIMPLE_TIMER_START _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
10#define BFIN_SIMPLE_TIMER_STOP _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
11#define BFIN_SIMPLE_TIMER_READ _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
12
13#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
new file mode 100644
index 000000000000..c76ed8def302
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -0,0 +1,175 @@
1/*
2 * File: include/asm-blackfin/bfin_sport.h
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 *
6 * Created: Thu Aug. 24 2006
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BFIN_SPORT_H__
31#define __BFIN_SPORT_H__
32
33#define SPORT_MAJOR 237
34#define SPORT_NR_DEVS 2
35
36/* Sport mode: it can be set to TDM, i2s or others */
37#define NORM_MODE 0x0
38#define TDM_MODE 0x1
39#define I2S_MODE 0x2
40
41/* Data format, normal, a-law or u-law */
42#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3
45struct sport_register;
46
47/* Function driver which use sport must initialize the structure */
48struct sport_config {
49 /*TDM (multichannels), I2S or other mode */
50 unsigned int mode:3;
51
52 /* if TDM mode is selected, channels must be set */
53 int channels; /* Must be in 8 units */
54 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
55
56 /* I2S mode */
57 unsigned int right_first:1; /* Right stereo channel first */
58
59 /* In mormal mode, the following item need to be set */
60 unsigned int lsb_first:1; /* order of transmit or receive data */
61 unsigned int fsync:1; /* Frame sync required */
62 unsigned int data_indep:1; /* data independent frame sync generated */
63 unsigned int act_low:1; /* Active low TFS */
64 unsigned int late_fsync:1; /* Late frame sync */
65 unsigned int tckfe:1;
66 unsigned int sec_en:1; /* Secondary side enabled */
67
68 /* Choose clock source */
69 unsigned int int_clk:1; /* Internal or external clock */
70
71 /* If external clock is used, the following fields are ignored */
72 int serial_clk;
73 int fsync_clk;
74
75 unsigned int data_format:2; /*Normal, u-law or a-law */
76
77 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled;
79};
80
81struct sport_register {
82 unsigned short tcr1;
83 unsigned short reserved0;
84 unsigned short tcr2;
85 unsigned short reserved1;
86 unsigned short tclkdiv;
87 unsigned short reserved2;
88 unsigned short tfsdiv;
89 unsigned short reserved3;
90 unsigned long tx;
91 unsigned long reserved_l0;
92 unsigned long rx;
93 unsigned long reserved_l1;
94 unsigned short rcr1;
95 unsigned short reserved4;
96 unsigned short rcr2;
97 unsigned short reserved5;
98 unsigned short rclkdiv;
99 unsigned short reserved6;
100 unsigned short rfsdiv;
101 unsigned short reserved7;
102 unsigned short stat;
103 unsigned short reserved8;
104 unsigned short chnl;
105 unsigned short reserved9;
106 unsigned short mcmc1;
107 unsigned short reserved10;
108 unsigned short mcmc2;
109 unsigned short reserved11;
110 unsigned long mtcs0;
111 unsigned long mtcs1;
112 unsigned long mtcs2;
113 unsigned long mtcs3;
114 unsigned long mrcs0;
115 unsigned long mrcs1;
116 unsigned long mrcs2;
117 unsigned long mrcs3;
118};
119
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123/* Test purpose */
124#define ENABLE_AD73311 _IOWR('P', 0x02, int)
125
126struct sport_dev {
127 struct cdev cdev; /* Char device structure */
128
129 int sport_num;
130
131 int dma_rx_chan;
132 int dma_tx_chan;
133
134 int rx_irq;
135 unsigned char *rx_buf; /* Buffer store the received data */
136 int rx_len; /* How many bytes will be received */
137 int rx_received; /* How many bytes has been received */
138
139 int tx_irq;
140 const unsigned char *tx_buf;
141 int tx_len;
142 int tx_sent;
143
144 int sport_err_irq;
145
146 struct mutex mutex; /* mutual exclusion semaphore */
147 struct task_struct *task;
148
149 wait_queue_head_t waitq;
150 int wait_con;
151 struct sport_register *regs;
152 struct sport_config config;
153};
154
155#define SPORT_TCR1 0
156#define SPORT_TCR2 1
157#define SPORT_TCLKDIV 2
158#define SPORT_TFSDIV 3
159#define SPORT_RCR1 8
160#define SPORT_RCR2 9
161#define SPORT_RCLKDIV 10
162#define SPORT_RFSDIV 11
163#define SPORT_CHANNEL 13
164#define SPORT_MCMC1 14
165#define SPORT_MCMC2 15
166#define SPORT_MTCS0 16
167#define SPORT_MTCS1 17
168#define SPORT_MTCS2 18
169#define SPORT_MTCS3 19
170#define SPORT_MRCS0 20
171#define SPORT_MRCS1 21
172#define SPORT_MRCS2 22
173#define SPORT_MRCS3 23
174
175#endif /*__BFIN_SPORT_H__*/
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
new file mode 100644
index 000000000000..b39a175c79c1
--- /dev/null
+++ b/arch/blackfin/include/asm/bitops.h
@@ -0,0 +1,218 @@
1#ifndef _BLACKFIN_BITOPS_H
2#define _BLACKFIN_BITOPS_H
3
4/*
5 * Copyright 1992, Linus Torvalds.
6 */
7
8#include <linux/compiler.h>
9#include <asm/byteorder.h> /* swab32 */
10#include <asm/system.h> /* save_flags */
11
12#ifdef __KERNEL__
13
14#ifndef _LINUX_BITOPS_H
15#error only <linux/bitops.h> can be included directly
16#endif
17
18#include <asm-generic/bitops/ffs.h>
19#include <asm-generic/bitops/__ffs.h>
20#include <asm-generic/bitops/sched.h>
21#include <asm-generic/bitops/ffz.h>
22
23static __inline__ void set_bit(int nr, volatile unsigned long *addr)
24{
25 int *a = (int *)addr;
26 int mask;
27 unsigned long flags;
28
29 a += nr >> 5;
30 mask = 1 << (nr & 0x1f);
31 local_irq_save(flags);
32 *a |= mask;
33 local_irq_restore(flags);
34}
35
36static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
37{
38 int *a = (int *)addr;
39 int mask;
40
41 a += nr >> 5;
42 mask = 1 << (nr & 0x1f);
43 *a |= mask;
44}
45
46/*
47 * clear_bit() doesn't provide any barrier for the compiler.
48 */
49#define smp_mb__before_clear_bit() barrier()
50#define smp_mb__after_clear_bit() barrier()
51
52static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
53{
54 int *a = (int *)addr;
55 int mask;
56 unsigned long flags;
57 a += nr >> 5;
58 mask = 1 << (nr & 0x1f);
59 local_irq_save(flags);
60 *a &= ~mask;
61 local_irq_restore(flags);
62}
63
64static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
65{
66 int *a = (int *)addr;
67 int mask;
68
69 a += nr >> 5;
70 mask = 1 << (nr & 0x1f);
71 *a &= ~mask;
72}
73
74static __inline__ void change_bit(int nr, volatile unsigned long *addr)
75{
76 int mask, flags;
77 unsigned long *ADDR = (unsigned long *)addr;
78
79 ADDR += nr >> 5;
80 mask = 1 << (nr & 31);
81 local_irq_save(flags);
82 *ADDR ^= mask;
83 local_irq_restore(flags);
84}
85
86static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
87{
88 int mask;
89 unsigned long *ADDR = (unsigned long *)addr;
90
91 ADDR += nr >> 5;
92 mask = 1 << (nr & 31);
93 *ADDR ^= mask;
94}
95
96static __inline__ int test_and_set_bit(int nr, void *addr)
97{
98 int mask, retval;
99 volatile unsigned int *a = (volatile unsigned int *)addr;
100 unsigned long flags;
101
102 a += nr >> 5;
103 mask = 1 << (nr & 0x1f);
104 local_irq_save(flags);
105 retval = (mask & *a) != 0;
106 *a |= mask;
107 local_irq_restore(flags);
108
109 return retval;
110}
111
112static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
113{
114 int mask, retval;
115 volatile unsigned int *a = (volatile unsigned int *)addr;
116
117 a += nr >> 5;
118 mask = 1 << (nr & 0x1f);
119 retval = (mask & *a) != 0;
120 *a |= mask;
121 return retval;
122}
123
124static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
125{
126 int mask, retval;
127 volatile unsigned int *a = (volatile unsigned int *)addr;
128 unsigned long flags;
129
130 a += nr >> 5;
131 mask = 1 << (nr & 0x1f);
132 local_irq_save(flags);
133 retval = (mask & *a) != 0;
134 *a &= ~mask;
135 local_irq_restore(flags);
136
137 return retval;
138}
139
140static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
141{
142 int mask, retval;
143 volatile unsigned int *a = (volatile unsigned int *)addr;
144
145 a += nr >> 5;
146 mask = 1 << (nr & 0x1f);
147 retval = (mask & *a) != 0;
148 *a &= ~mask;
149 return retval;
150}
151
152static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
153{
154 int mask, retval;
155 volatile unsigned int *a = (volatile unsigned int *)addr;
156 unsigned long flags;
157
158 a += nr >> 5;
159 mask = 1 << (nr & 0x1f);
160 local_irq_save(flags);
161 retval = (mask & *a) != 0;
162 *a ^= mask;
163 local_irq_restore(flags);
164 return retval;
165}
166
167static __inline__ int __test_and_change_bit(int nr,
168 volatile unsigned long *addr)
169{
170 int mask, retval;
171 volatile unsigned int *a = (volatile unsigned int *)addr;
172
173 a += nr >> 5;
174 mask = 1 << (nr & 0x1f);
175 retval = (mask & *a) != 0;
176 *a ^= mask;
177 return retval;
178}
179
180/*
181 * This routine doesn't need to be atomic.
182 */
183static __inline__ int __constant_test_bit(int nr, const void *addr)
184{
185 return ((1UL << (nr & 31)) &
186 (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
187}
188
189static __inline__ int __test_bit(int nr, const void *addr)
190{
191 int *a = (int *)addr;
192 int mask;
193
194 a += nr >> 5;
195 mask = 1 << (nr & 0x1f);
196 return ((mask & *a) != 0);
197}
198
199#define test_bit(nr,addr) \
200(__builtin_constant_p(nr) ? \
201 __constant_test_bit((nr),(addr)) : \
202 __test_bit((nr),(addr)))
203
204#include <asm-generic/bitops/find.h>
205#include <asm-generic/bitops/hweight.h>
206#include <asm-generic/bitops/lock.h>
207
208#include <asm-generic/bitops/ext2-atomic.h>
209#include <asm-generic/bitops/ext2-non-atomic.h>
210
211#include <asm-generic/bitops/minix.h>
212
213#endif /* __KERNEL__ */
214
215#include <asm-generic/bitops/fls.h>
216#include <asm-generic/bitops/fls64.h>
217
218#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
new file mode 100644
index 000000000000..8749b0e321ab
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -0,0 +1,92 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_H_
7#define _BLACKFIN_H_
8
9#define LO(con32) ((con32) & 0xFFFF)
10#define lo(con32) ((con32) & 0xFFFF)
11#define HI(con32) (((con32) >> 16) & 0xFFFF)
12#define hi(con32) (((con32) >> 16) & 0xFFFF)
13
14#include <mach/anomaly.h>
15
16#ifndef __ASSEMBLY__
17
18/* SSYNC implementation for C file */
19static inline void SSYNC(void)
20{
21 int _tmp;
22 if (ANOMALY_05000312)
23 __asm__ __volatile__(
24 "cli %0;"
25 "nop;"
26 "nop;"
27 "ssync;"
28 "sti %0;"
29 : "=d" (_tmp)
30 );
31 else if (ANOMALY_05000244)
32 __asm__ __volatile__(
33 "nop;"
34 "nop;"
35 "nop;"
36 "ssync;"
37 );
38 else
39 __asm__ __volatile__("ssync;");
40}
41
42/* CSYNC implementation for C file */
43static inline void CSYNC(void)
44{
45 int _tmp;
46 if (ANOMALY_05000312)
47 __asm__ __volatile__(
48 "cli %0;"
49 "nop;"
50 "nop;"
51 "csync;"
52 "sti %0;"
53 : "=d" (_tmp)
54 );
55 else if (ANOMALY_05000244)
56 __asm__ __volatile__(
57 "nop;"
58 "nop;"
59 "nop;"
60 "csync;"
61 );
62 else
63 __asm__ __volatile__("csync;");
64}
65
66#else /* __ASSEMBLY__ */
67
68/* SSYNC & CSYNC implementations for assembly files */
69
70#define ssync(x) SSYNC(x)
71#define csync(x) CSYNC(x)
72
73#if ANOMALY_05000312
74#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
75#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
76
77#elif ANOMALY_05000244
78#define SSYNC(scratch) nop; nop; nop; SSYNC;
79#define CSYNC(scratch) nop; nop; nop; CSYNC;
80
81#else
82#define SSYNC(scratch) SSYNC;
83#define CSYNC(scratch) CSYNC;
84
85#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
86
87#endif /* __ASSEMBLY__ */
88
89#include <mach/blackfin.h>
90#include <asm/bfin-global.h>
91
92#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
new file mode 100644
index 000000000000..6d3e11b1fc57
--- /dev/null
+++ b/arch/blackfin/include/asm/bug.h
@@ -0,0 +1,17 @@
1#ifndef _BLACKFIN_BUG_H
2#define _BLACKFIN_BUG_H
3
4#ifdef CONFIG_BUG
5#define HAVE_ARCH_BUG
6
7#define BUG() do { \
8 dump_bfin_trace_buffer(); \
9 printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
10 panic("BUG!"); \
11} while (0)
12
13#endif
14
15#include <asm-generic/bug.h>
16
17#endif
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h
new file mode 100644
index 000000000000..9093c9c1fb81
--- /dev/null
+++ b/arch/blackfin/include/asm/bugs.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-blackfin/bugs.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7/*
8 * This is included by init/main.c to check for architecture-dependent bugs.
9 *
10 * Needs:
11 * void check_bugs(void);
12 */
13
14static void check_bugs(void)
15{
16}
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
new file mode 100644
index 000000000000..6a673d42da18
--- /dev/null
+++ b/arch/blackfin/include/asm/byteorder.h
@@ -0,0 +1,48 @@
1#ifndef _BLACKFIN_BYTEORDER_H
2#define _BLACKFIN_BYTEORDER_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7#ifdef __GNUC__
8
9static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
10{
11 __u32 tmp;
12 __asm__("%1 = %0 >> 8 (V);\n\t"
13 "%0 = %0 << 8 (V);\n\t"
14 "%0 = %0 | %1;\n\t"
15 : "+d"(xx), "=&d"(tmp));
16 return xx;
17}
18
19static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
20{
21 __u32 rv;
22 __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
23 return rv;
24}
25
26#define __arch__swahb32(x) ___arch__swahb32(x)
27#define __arch__swahw32(x) ___arch__swahw32(x)
28#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
29
30static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
31{
32 __u32 xw = xx;
33 __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
34 return (__u16)xw;
35}
36
37#define __arch__swab16(x) ___arch__swab16(x)
38
39#endif
40
41#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
42# define __BYTEORDER_HAS_U64__
43# define __SWAB_64_THRU_32__
44#endif
45
46#include <linux/byteorder/little_endian.h>
47
48#endif /* _BLACKFIN_BYTEORDER_H */
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 000000000000..023d72133b5a
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-blackfin/cache.h
3 */
4#ifndef __ARCH_BLACKFIN_CACHE_H
5#define __ARCH_BLACKFIN_CACHE_H
6
7/*
8 * Bytes per L1 cache line
9 * Blackfin loads 32 bytes for cache
10 */
11#define L1_CACHE_SHIFT 5
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13#define SMP_CACHE_BYTES L1_CACHE_BYTES
14
15/*
16 * Put cacheline_aliged data to L1 data memory
17 */
18#ifdef CONFIG_CACHELINE_ALIGNED_L1
19#define __cacheline_aligned \
20 __attribute__((__aligned__(L1_CACHE_BYTES), \
21 __section__(".data_l1.cacheline_aligned")))
22#endif
23
24/*
25 * largest L1 which this arch supports
26 */
27#define L1_CACHE_SHIFT_MAX 5
28
29#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
new file mode 100644
index 000000000000..d81a77545a04
--- /dev/null
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -0,0 +1,90 @@
1/*
2 * File: include/asm-blackfin/cacheflush.h
3 * Based on: include/asm-m68knommu/cacheflush.h
4 * Author: LG Soft India
5 * Copyright (C) 2004 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level cache routines adapted from the i386
8 * and PPC versions by Greg Ungerer (gerg@snapgear.com)
9 *
10 * Modified:
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; see the file COPYING.
26 * If not, write to the Free Software Foundation,
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 */
29
30#ifndef _BLACKFIN_CACHEFLUSH_H
31#define _BLACKFIN_CACHEFLUSH_H
32
33#include <asm/cplb.h>
34
35extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
36extern void blackfin_icache_flush_range(unsigned int, unsigned int);
37extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
38extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
39extern void blackfin_dflush_page(void *);
40
41#define flush_dcache_mmap_lock(mapping) do { } while (0)
42#define flush_dcache_mmap_unlock(mapping) do { } while (0)
43#define flush_cache_mm(mm) do { } while (0)
44#define flush_cache_range(vma, start, end) do { } while (0)
45#define flush_cache_page(vma, vmaddr) do { } while (0)
46#define flush_cache_vmap(start, end) do { } while (0)
47#define flush_cache_vunmap(start, end) do { } while (0)
48
49static inline void flush_icache_range(unsigned start, unsigned end)
50{
51#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
52
53# if defined(CONFIG_BFIN_WT)
54 blackfin_icache_flush_range((start), (end));
55# else
56 blackfin_icache_dcache_flush_range((start), (end));
57# endif
58
59#else
60
61# if defined(CONFIG_BFIN_ICACHE)
62 blackfin_icache_flush_range((start), (end));
63# endif
64# if defined(CONFIG_BFIN_DCACHE)
65 blackfin_dcache_flush_range((start), (end));
66# endif
67
68#endif
69}
70
71#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
72do { memcpy(dst, src, len); \
73 flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
74} while (0)
75#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
76
77#if defined(CONFIG_BFIN_DCACHE)
78# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
79#else
80# define invalidate_dcache_range(start,end) do { } while (0)
81#endif
82#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
83# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
84# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
85#else
86# define flush_dcache_range(start,end) do { } while (0)
87# define flush_dcache_page(page) do { } while (0)
88#endif
89
90#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
new file mode 100644
index 000000000000..35f841bce57d
--- /dev/null
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -0,0 +1,328 @@
1 /*
2 * File: include/asm-blackfin/mach-common/cdef_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _CDEF_LPBLACKFIN_H
30#define _CDEF_LPBLACKFIN_H
31
32/*#if !defined(__ADSPLPBLACKFIN__)
33#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
34#endif
35*/
36#include <asm/def_LPBlackfin.h>
37
38/*Cache & SRAM Memory*/
39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
43#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
44#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
45#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
46#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
47/*
48#define MMR_TIMEOUT 0xFFE00010
49*/
50#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
51#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
52#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
53#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
54#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
55#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
56#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
57#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
58#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
59#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
60#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
61#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
62#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
63#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
64#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
65#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
66#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
67#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
68#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
69#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
70#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
71#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
72#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
73#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
74#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
75#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
76#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
77#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
78#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
79#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
80#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
81#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
82#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
83#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
84#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
85#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
86#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
87#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
88#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
89#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
90#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
91#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
92#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
93#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
94#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
95#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
96#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
97#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
98#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
99#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
100#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
101#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
102#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
103#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
104#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
105#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
106#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
107#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
108#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
109#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
110#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
111#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
112#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
113#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
114#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
115#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
116/*
117#define DTEST_INDEX 0xFFE00304
118*/
119#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
120#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
121#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
122#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
123/*
124#define DTEST_DATA2 0xFFE00408
125#define DTEST_DATA3 0xFFE0040C
126*/
127#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
128#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
129#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
130#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
131#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
132#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
133#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
134#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
135#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
136#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
137#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
138#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
139#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
140#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
141#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
142#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
143#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
144#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
145#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
146#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
147#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
148#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
149#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
150#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
151#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
152#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
153#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
154#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
155#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
156#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
157#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
158#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
159#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
160#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
161#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
162#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
163#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
164#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
165#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
166#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
167#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
168#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
169#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
170#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
171#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
172#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
173#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
174#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
175#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
176#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
177#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
178#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
179#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
180#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
181#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
182#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
183#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
184#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
185#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
186#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
187#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
188#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
189#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
190#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
191#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
192#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
193#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
194#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
195#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
196#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
197#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
198#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
199#if 0
200#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
201#endif
202#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
203#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
204#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
205#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
206
207/* Event/Interrupt Registers*/
208
209#define bfin_read_EVT0() bfin_read32(EVT0)
210#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
211#define bfin_read_EVT1() bfin_read32(EVT1)
212#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
213#define bfin_read_EVT2() bfin_read32(EVT2)
214#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
215#define bfin_read_EVT3() bfin_read32(EVT3)
216#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
217#define bfin_read_EVT4() bfin_read32(EVT4)
218#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
219#define bfin_read_EVT5() bfin_read32(EVT5)
220#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
221#define bfin_read_EVT6() bfin_read32(EVT6)
222#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
223#define bfin_read_EVT7() bfin_read32(EVT7)
224#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
225#define bfin_read_EVT8() bfin_read32(EVT8)
226#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
227#define bfin_read_EVT9() bfin_read32(EVT9)
228#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
229#define bfin_read_EVT10() bfin_read32(EVT10)
230#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
231#define bfin_read_EVT11() bfin_read32(EVT11)
232#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
233#define bfin_read_EVT12() bfin_read32(EVT12)
234#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
235#define bfin_read_EVT13() bfin_read32(EVT13)
236#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
237#define bfin_read_EVT14() bfin_read32(EVT14)
238#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
239#define bfin_read_EVT15() bfin_read32(EVT15)
240#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
241#define bfin_read_IMASK() bfin_read32(IMASK)
242#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
243#define bfin_read_IPEND() bfin_read32(IPEND)
244#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
245#define bfin_read_ILAT() bfin_read32(ILAT)
246#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
247
248/*Core Timer Registers*/
249#define bfin_read_TCNTL() bfin_read32(TCNTL)
250#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
251#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
252#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
253#define bfin_read_TSCALE() bfin_read32(TSCALE)
254#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
255#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
256#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
257
258/*Debug/MP/Emulation Registers*/
259#define bfin_read_DSPID() bfin_read32(DSPID)
260#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
261#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
262#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
263#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
264#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
265#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
266#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
267
268/*Trace Buffer Registers*/
269#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
270#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
271#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
272#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
273#define bfin_read_TBUF() bfin_read32(TBUF)
274#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
275
276/*Watch Point Control Registers*/
277#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
278#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
279#define bfin_read_WPIA0() bfin_read32(WPIA0)
280#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
281#define bfin_read_WPIA1() bfin_read32(WPIA1)
282#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
283#define bfin_read_WPIA2() bfin_read32(WPIA2)
284#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
285#define bfin_read_WPIA3() bfin_read32(WPIA3)
286#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
287#define bfin_read_WPIA4() bfin_read32(WPIA4)
288#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
289#define bfin_read_WPIA5() bfin_read32(WPIA5)
290#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
291#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
292#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
293#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
294#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
295#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
296#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
297#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
298#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
299#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
300#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
301#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
302#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
303#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
304#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
305#define bfin_read_WPDA0() bfin_read32(WPDA0)
306#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
307#define bfin_read_WPDA1() bfin_read32(WPDA1)
308#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
309#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
310#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
311#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
312#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
313#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
314#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
315
316/*Performance Monitor Registers*/
317#define bfin_read_PFCTL() bfin_read32(PFCTL)
318#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
319#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
320#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
321#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
322#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
323
324/*
325#define IPRIO 0xFFE02110
326*/
327
328#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
new file mode 100644
index 000000000000..6f6af2b8e9e0
--- /dev/null
+++ b/arch/blackfin/include/asm/checksum.h
@@ -0,0 +1,100 @@
1#ifndef _BFIN_CHECKSUM_H
2#define _BFIN_CHECKSUM_H
3
4/*
5 * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
6 *
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28__wsum csum_partial_copy(const void *src, void *dst,
29 int len, __wsum sum);
30
31/*
32 * the same as csum_partial_copy, but copies from user space.
33 *
34 * here even more important to align src and dst on a 32-bit (or even
35 * better 64-bit) boundary
36 */
37
38extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
39 int len, __wsum sum, int *csum_err);
40
41#define csum_partial_copy_nocheck(src, dst, len, sum) \
42 csum_partial_copy((src), (dst), (len), (sum))
43
44__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
45
46/*
47 * Fold a partial checksum
48 */
49
50static inline __sum16 csum_fold(__wsum sum)
51{
52 while (sum >> 16)
53 sum = (sum & 0xffff) + (sum >> 16);
54 return ((~(sum << 16)) >> 16);
55}
56
57/*
58 * computes the checksum of the TCP/UDP pseudo-header
59 * returns a 16-bit checksum, already complemented
60 */
61
62static inline __wsum
63csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
64 unsigned short proto, __wsum sum)
65{
66
67 __asm__ ("%0 = %0 + %1;\n\t"
68 "CC = AC0;\n\t"
69 "if !CC jump 4;\n\t"
70 "%0 = %0 + %4;\n\t"
71 "%0 = %0 + %2;\n\t"
72 "CC = AC0;\n\t"
73 "if !CC jump 4;\n\t"
74 "%0 = %0 + %4;\n\t"
75 "%0 = %0 + %3;\n\t"
76 "CC = AC0;\n\t"
77 "if !CC jump 4;\n\t"
78 "%0 = %0 + %4;\n\t"
79 "NOP;\n\t"
80 : "=d" (sum)
81 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
82
83 return (sum);
84}
85
86static inline __sum16
87csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
88 unsigned short proto, __wsum sum)
89{
90 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
91}
92
93/*
94 * this routine is used for miscellaneous IP-like checksums, mainly
95 * in icmp.c
96 */
97
98extern __sum16 ip_compute_csum(const void *buff, int len);
99
100#endif /* _BFIN_CHECKSUM_H */
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
new file mode 100644
index 000000000000..033bba92d61c
--- /dev/null
+++ b/arch/blackfin/include/asm/clocks.h
@@ -0,0 +1,70 @@
1/*
2 * File: include/asm-blackfin/mach-common/clocks.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Common Clock definitions for various kernel files
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef _BFIN_CLOCKS_H
31#define _BFIN_CLOCKS_H
32
33#ifdef CONFIG_CCLK_DIV_1
34# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
35# define CONFIG_CCLK_DIV 1
36#endif
37
38#ifdef CONFIG_CCLK_DIV_2
39# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
40# define CONFIG_CCLK_DIV 2
41#endif
42
43#ifdef CONFIG_CCLK_DIV_4
44# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
45# define CONFIG_CCLK_DIV 4
46#endif
47
48#ifdef CONFIG_CCLK_DIV_8
49# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
50# define CONFIG_CCLK_DIV 8
51#endif
52
53#ifndef CONFIG_PLL_BYPASS
54# ifndef CONFIG_CLKIN_HALF
55# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
56# else
57# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
58# endif
59
60# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
61# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
62
63#else
64# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
65# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
66# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
67# define CONFIG_VCO_MULT 0
68#endif
69
70#endif
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
new file mode 100644
index 000000000000..c0e630edfb9a
--- /dev/null
+++ b/arch/blackfin/include/asm/context.S
@@ -0,0 +1,355 @@
1/*
2 * File: arch/blackfin/kernel/context.S
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31 * NOTE! The single-stepping code assumes that all interrupt handlers
32 * start by saving SYSCFG on the stack with their first instruction.
33 */
34
35/*
36 * Code to save processor context.
37 * We even save the register which are preserved by a function call
38 * - r4, r5, r6, r7, p3, p4, p5
39 */
40.macro save_context_with_interrupts
41 [--sp] = SYSCFG;
42
43 [--sp] = P0; /*orig_p0*/
44 [--sp] = R0; /*orig_r0*/
45
46 [--sp] = ( R7:0, P5:0 );
47 [--sp] = fp;
48 [--sp] = usp;
49
50 [--sp] = i0;
51 [--sp] = i1;
52 [--sp] = i2;
53 [--sp] = i3;
54
55 [--sp] = m0;
56 [--sp] = m1;
57 [--sp] = m2;
58 [--sp] = m3;
59
60 [--sp] = l0;
61 [--sp] = l1;
62 [--sp] = l2;
63 [--sp] = l3;
64
65 [--sp] = b0;
66 [--sp] = b1;
67 [--sp] = b2;
68 [--sp] = b3;
69 [--sp] = a0.x;
70 [--sp] = a0.w;
71 [--sp] = a1.x;
72 [--sp] = a1.w;
73
74 [--sp] = LC0;
75 [--sp] = LC1;
76 [--sp] = LT0;
77 [--sp] = LT1;
78 [--sp] = LB0;
79 [--sp] = LB1;
80
81 [--sp] = ASTAT;
82
83 [--sp] = r0; /* Skip reserved */
84 [--sp] = RETS;
85 r0 = RETI;
86 [--sp] = r0;
87 [--sp] = RETX;
88 [--sp] = RETN;
89 [--sp] = RETE;
90 [--sp] = SEQSTAT;
91 [--sp] = r0; /* Skip IPEND as well. */
92 /* Switch to other method of keeping interrupts disabled. */
93#ifdef CONFIG_DEBUG_HWERR
94 r0 = 0x3f;
95 sti r0;
96#else
97 cli r0;
98#endif
99 [--sp] = RETI; /*orig_pc*/
100 /* Clear all L registers. */
101 r0 = 0 (x);
102 l0 = r0;
103 l1 = r0;
104 l2 = r0;
105 l3 = r0;
106.endm
107
108.macro save_context_syscall
109 [--sp] = SYSCFG;
110
111 [--sp] = P0; /*orig_p0*/
112 [--sp] = R0; /*orig_r0*/
113 [--sp] = ( R7:0, P5:0 );
114 [--sp] = fp;
115 [--sp] = usp;
116
117 [--sp] = i0;
118 [--sp] = i1;
119 [--sp] = i2;
120 [--sp] = i3;
121
122 [--sp] = m0;
123 [--sp] = m1;
124 [--sp] = m2;
125 [--sp] = m3;
126
127 [--sp] = l0;
128 [--sp] = l1;
129 [--sp] = l2;
130 [--sp] = l3;
131
132 [--sp] = b0;
133 [--sp] = b1;
134 [--sp] = b2;
135 [--sp] = b3;
136 [--sp] = a0.x;
137 [--sp] = a0.w;
138 [--sp] = a1.x;
139 [--sp] = a1.w;
140
141 [--sp] = LC0;
142 [--sp] = LC1;
143 [--sp] = LT0;
144 [--sp] = LT1;
145 [--sp] = LB0;
146 [--sp] = LB1;
147
148 [--sp] = ASTAT;
149
150 [--sp] = r0; /* Skip reserved */
151 [--sp] = RETS;
152 r0 = RETI;
153 [--sp] = r0;
154 [--sp] = RETX;
155 [--sp] = RETN;
156 [--sp] = RETE;
157 [--sp] = SEQSTAT;
158 [--sp] = r0; /* Skip IPEND as well. */
159 [--sp] = RETI; /*orig_pc*/
160 /* Clear all L registers. */
161 r0 = 0 (x);
162 l0 = r0;
163 l1 = r0;
164 l2 = r0;
165 l3 = r0;
166.endm
167
168.macro save_context_no_interrupts
169 [--sp] = SYSCFG;
170 [--sp] = P0; /* orig_p0 */
171 [--sp] = R0; /* orig_r0 */
172 [--sp] = ( R7:0, P5:0 );
173 [--sp] = fp;
174 [--sp] = usp;
175
176 [--sp] = i0;
177 [--sp] = i1;
178 [--sp] = i2;
179 [--sp] = i3;
180
181 [--sp] = m0;
182 [--sp] = m1;
183 [--sp] = m2;
184 [--sp] = m3;
185
186 [--sp] = l0;
187 [--sp] = l1;
188 [--sp] = l2;
189 [--sp] = l3;
190
191 [--sp] = b0;
192 [--sp] = b1;
193 [--sp] = b2;
194 [--sp] = b3;
195 [--sp] = a0.x;
196 [--sp] = a0.w;
197 [--sp] = a1.x;
198 [--sp] = a1.w;
199
200 [--sp] = LC0;
201 [--sp] = LC1;
202 [--sp] = LT0;
203 [--sp] = LT1;
204 [--sp] = LB0;
205 [--sp] = LB1;
206
207 [--sp] = ASTAT;
208
209#ifdef CONFIG_KGDB
210 fp = 0(Z);
211 r1 = sp;
212 r1 += 60;
213 r1 += 60;
214 r1 += 60;
215 [--sp] = r1;
216#else
217 [--sp] = r0; /* Skip reserved */
218#endif
219 [--sp] = RETS;
220 r0 = RETI;
221 [--sp] = r0;
222 [--sp] = RETX;
223 [--sp] = RETN;
224 [--sp] = RETE;
225 [--sp] = SEQSTAT;
226#ifdef CONFIG_KGDB
227 r1.l = lo(IPEND);
228 r1.h = hi(IPEND);
229 [--sp] = r1;
230#else
231 [--sp] = r0; /* Skip IPEND as well. */
232#endif
233 [--sp] = r0; /*orig_pc*/
234 /* Clear all L registers. */
235 r0 = 0 (x);
236 l0 = r0;
237 l1 = r0;
238 l2 = r0;
239 l3 = r0;
240.endm
241
242.macro restore_context_no_interrupts
243 sp += 4; /* Skip orig_pc */
244 sp += 4; /* Skip IPEND */
245 SEQSTAT = [sp++];
246 RETE = [sp++];
247 RETN = [sp++];
248 RETX = [sp++];
249 r0 = [sp++];
250 RETI = r0; /* Restore RETI indirectly when in exception */
251 RETS = [sp++];
252
253 sp += 4; /* Skip Reserved */
254
255 ASTAT = [sp++];
256
257 LB1 = [sp++];
258 LB0 = [sp++];
259 LT1 = [sp++];
260 LT0 = [sp++];
261 LC1 = [sp++];
262 LC0 = [sp++];
263
264 a1.w = [sp++];
265 a1.x = [sp++];
266 a0.w = [sp++];
267 a0.x = [sp++];
268 b3 = [sp++];
269 b2 = [sp++];
270 b1 = [sp++];
271 b0 = [sp++];
272
273 l3 = [sp++];
274 l2 = [sp++];
275 l1 = [sp++];
276 l0 = [sp++];
277
278 m3 = [sp++];
279 m2 = [sp++];
280 m1 = [sp++];
281 m0 = [sp++];
282
283 i3 = [sp++];
284 i2 = [sp++];
285 i1 = [sp++];
286 i0 = [sp++];
287
288 sp += 4;
289 fp = [sp++];
290
291 ( R7 : 0, P5 : 0) = [ SP ++ ];
292 sp += 8; /* Skip orig_r0/orig_p0 */
293 SYSCFG = [sp++];
294.endm
295
296.macro restore_context_with_interrupts
297 sp += 4; /* Skip orig_pc */
298 sp += 4; /* Skip IPEND */
299 SEQSTAT = [sp++];
300 RETE = [sp++];
301 RETN = [sp++];
302 RETX = [sp++];
303 RETI = [sp++];
304 RETS = [sp++];
305
306 p0.h = _irq_flags;
307 p0.l = _irq_flags;
308 r0 = [p0];
309 sti r0;
310
311 sp += 4; /* Skip Reserved */
312
313 ASTAT = [sp++];
314
315 LB1 = [sp++];
316 LB0 = [sp++];
317 LT1 = [sp++];
318 LT0 = [sp++];
319 LC1 = [sp++];
320 LC0 = [sp++];
321
322 a1.w = [sp++];
323 a1.x = [sp++];
324 a0.w = [sp++];
325 a0.x = [sp++];
326 b3 = [sp++];
327 b2 = [sp++];
328 b1 = [sp++];
329 b0 = [sp++];
330
331 l3 = [sp++];
332 l2 = [sp++];
333 l1 = [sp++];
334 l0 = [sp++];
335
336 m3 = [sp++];
337 m2 = [sp++];
338 m1 = [sp++];
339 m0 = [sp++];
340
341 i3 = [sp++];
342 i2 = [sp++];
343 i1 = [sp++];
344 i0 = [sp++];
345
346 sp += 4;
347 fp = [sp++];
348
349 ( R7 : 0, P5 : 0) = [ SP ++ ];
350 sp += 8; /* Skip orig_r0/orig_p0 */
351 csync;
352 SYSCFG = [sp++];
353 csync;
354.endm
355
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h
new file mode 100644
index 000000000000..75c67b99d607
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb-mpu.h
@@ -0,0 +1,61 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#ifndef __ASM_BFIN_CPLB_MPU_H
30#define __ASM_BFIN_CPLB_MPU_H
31
32struct cplb_entry {
33 unsigned long data, addr;
34};
35
36struct mem_region {
37 unsigned long start, end;
38 unsigned long dcplb_data;
39 unsigned long icplb_data;
40};
41
42extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
43extern struct cplb_entry icplb_tbl[MAX_CPLBS];
44extern int first_switched_icplb;
45extern int first_mask_dcplb;
46extern int first_switched_dcplb;
47
48extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
49extern int nr_cplb_flush;
50
51extern int page_mask_order;
52extern int page_mask_nelts;
53
54extern unsigned long *current_rwx_mask;
55
56extern void flush_switched_cplbs(void);
57extern void set_mask_dcplbs(unsigned long *);
58
59extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
60
61#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
new file mode 100644
index 000000000000..05d6f05fb748
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb.h
@@ -0,0 +1,110 @@
1/*
2 * File: include/asm-blackfin/cplb.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 2000
7 * Description: Common CPLB definitions for CPLB init
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef _CPLB_H
31#define _CPLB_H
32
33#include <asm/blackfin.h>
34#include <mach/anomaly.h>
35
36#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
37#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
38#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
39#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
40
41/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
42
43#if ANOMALY_05000158
44#define ANOMALY_05000158_WORKAROUND 0x200
45#else
46#define ANOMALY_05000158_WORKAROUND 0x0
47#endif
48
49#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
50
51#ifdef CONFIG_BFIN_WB /*Write Back Policy */
52#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
53#else /*Write Through */
54#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
55#endif
56
57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
58#define L2_MEMORY (CPLB_COMMON)
59#define SDRAM_DNON_CHBL (CPLB_COMMON)
60#define SDRAM_EBIU (CPLB_COMMON)
61#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
62
63#define SIZE_1K 0x00000400 /* 1K */
64#define SIZE_4K 0x00001000 /* 4K */
65#define SIZE_1M 0x00100000 /* 1M */
66#define SIZE_4M 0x00400000 /* 4M */
67
68#ifdef CONFIG_MPU
69#define MAX_CPLBS 16
70#else
71#define MAX_CPLBS (16 * 2)
72#endif
73
74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
76
77#define CPLB_ENABLE_ICACHE_P 0
78#define CPLB_ENABLE_DCACHE_P 1
79#define CPLB_ENABLE_DCACHE2_P 2
80#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
81#define CPLB_ENABLE_ICPLBS_P 4
82#define CPLB_ENABLE_DCPLBS_P 5
83
84#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
85#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
86#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
87#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
88#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
89#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
90#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
91 CPLB_ENABLE_ICPLBS | \
92 CPLB_ENABLE_DCPLBS
93
94#define CPLB_RELOADED 0x0000
95#define CPLB_NO_UNLOCKED 0x0001
96#define CPLB_NO_ADDR_MATCH 0x0002
97#define CPLB_PROT_VIOL 0x0003
98#define CPLB_UNKNOWN_ERR 0x0004
99
100#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
101#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
102
103#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
104#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
105#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
106#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
107#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
108#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
109
110#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
new file mode 100644
index 000000000000..0eb1c1b685a7
--- /dev/null
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -0,0 +1,95 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __ASM_CPLBINIT_H__
31#define __ASM_CPLBINIT_H__
32
33#include <asm/blackfin.h>
34#include <asm/cplb.h>
35
36#ifdef CONFIG_MPU
37
38#include <asm/cplb-mpu.h>
39
40#else
41
42#define INITIAL_T 0x1
43#define SWITCH_T 0x2
44#define I_CPLB 0x4
45#define D_CPLB 0x8
46
47#define IN_KERNEL 1
48
49enum
50{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
51
52struct cplb_desc {
53 u32 start; /* start address */
54 u32 end; /* end address */
55 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
56 u16 attr;/* attributes */
57 u16 i_conf;/* I-CPLB DATA */
58 u16 d_conf;/* D-CPLB DATA */
59 u16 valid;/* valid */
60 const s8 name[30];/* name */
61};
62
63struct cplb_tab {
64 u_long *tab;
65 u16 pos;
66 u16 size;
67};
68
69extern u_long icplb_table[];
70extern u_long dcplb_table[];
71
72/* Till here we are discussing about the static memory management model.
73 * However, the operating envoronments commonly define more CPLB
74 * descriptors to cover the entire addressable memory than will fit into
75 * the available on-chip 16 CPLB MMRs. When this happens, the below table
76 * will be used which will hold all the potentially required CPLB descriptors
77 *
78 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
79 */
80
81extern u_long ipdt_table[];
82extern u_long dpdt_table[];
83#ifdef CONFIG_CPLB_INFO
84extern u_long ipdt_swapcount_table[];
85extern u_long dpdt_swapcount_table[];
86#endif
87
88#endif /* CONFIG_MPU */
89
90extern unsigned long reserved_mem_dcache_on;
91extern unsigned long reserved_mem_icache_on;
92
93extern void generate_cpl_tables(void);
94
95#endif
diff --git a/arch/blackfin/include/asm/cpumask.h b/arch/blackfin/include/asm/cpumask.h
new file mode 100644
index 000000000000..b20a8e9012cb
--- /dev/null
+++ b/arch/blackfin/include/asm/cpumask.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_CPUMASK_H
2#define _ASM_BLACKFIN_CPUMASK_H
3
4#include <asm-generic/cpumask.h>
5
6#endif /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h
new file mode 100644
index 000000000000..2b19705f9885
--- /dev/null
+++ b/arch/blackfin/include/asm/cputime.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_CPUTIME_H
2#define __BLACKFIN_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __BLACKFIN_CPUTIME_H */
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
new file mode 100644
index 000000000000..31918d29122c
--- /dev/null
+++ b/arch/blackfin/include/asm/current.h
@@ -0,0 +1,23 @@
1#ifndef _BLACKFIN_CURRENT_H
2#define _BLACKFIN_CURRENT_H
3/*
4 * current.h
5 * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
6 *
7 * rather than dedicate a register (as the m68k source does), we
8 * just keep a global, we should probably just change it all to be
9 * current and lose _current_task.
10 */
11#include <linux/thread_info.h>
12
13struct task_struct;
14
15static inline struct task_struct *get_current(void) __attribute__ ((__const__));
16static inline struct task_struct *get_current(void)
17{
18 return (current_thread_info()->task);
19}
20
21#define current (get_current())
22
23#endif /* _BLACKFIN_CURRENT_H */
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
new file mode 100644
index 000000000000..6341eebff3dc
--- /dev/null
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -0,0 +1,712 @@
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31#ifndef _DEF_LPBLACKFIN_H
32#define _DEF_LPBLACKFIN_H
33
34#include <mach/anomaly.h>
35
36#define MK_BMSK_(x) (1<<x)
37
38#ifndef __ASSEMBLY__
39
40#include <linux/types.h>
41
42#if ANOMALY_05000198
43# define NOP_PAD_ANOMALY_05000198 "nop;"
44#else
45# define NOP_PAD_ANOMALY_05000198
46#endif
47
48#define bfin_read8(addr) ({ \
49 uint32_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58#define bfin_read16(addr) ({ \
59 uint32_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68#define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78#define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" ((uint8_t)(val)) \
84 : "memory" \
85 )
86
87#define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" ((uint16_t)(val)) \
93 : "memory" \
94 )
95
96#define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105#endif /* __ASSEMBLY__ */
106
107/**************************************************
108 * System Register Bits
109 **************************************************/
110
111/**************************************************
112 * ASTAT register
113 **************************************************/
114
115/* definitions of ASTAT bit positions*/
116
117/*Result of last ALU0 or shifter operation is zero*/
118#define ASTAT_AZ_P 0x00000000
119/*Result of last ALU0 or shifter operation is negative*/
120#define ASTAT_AN_P 0x00000001
121/*Condition Code, used for holding comparison results*/
122#define ASTAT_CC_P 0x00000005
123/*Quotient Bit*/
124#define ASTAT_AQ_P 0x00000006
125/*Rounding mode, set for biased, clear for unbiased*/
126#define ASTAT_RND_MOD_P 0x00000008
127/*Result of last ALU0 operation generated a carry*/
128#define ASTAT_AC0_P 0x0000000C
129/*Result of last ALU0 operation generated a carry*/
130#define ASTAT_AC0_COPY_P 0x00000002
131/*Result of last ALU1 operation generated a carry*/
132#define ASTAT_AC1_P 0x0000000D
133/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
134#define ASTAT_AV0_P 0x00000010
135/*Sticky version of ASTAT_AV0 */
136#define ASTAT_AV0S_P 0x00000011
137/*Result of last MAC1 operation overflowed, sticky for MAC*/
138#define ASTAT_AV1_P 0x00000012
139/*Sticky version of ASTAT_AV1 */
140#define ASTAT_AV1S_P 0x00000013
141/*Result of last ALU0 or MAC0 operation overflowed*/
142#define ASTAT_V_P 0x00000018
143/*Result of last ALU0 or MAC0 operation overflowed*/
144#define ASTAT_V_COPY_P 0x00000003
145/*Sticky version of ASTAT_V*/
146#define ASTAT_VS_P 0x00000019
147
148/* Masks */
149
150/*Result of last ALU0 or shifter operation is zero*/
151#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
152/*Result of last ALU0 or shifter operation is negative*/
153#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
154/*Result of last ALU0 operation generated a carry*/
155#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
156/*Result of last ALU0 operation generated a carry*/
157#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
158/*Result of last ALU0 operation generated a carry*/
159#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
160/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
161#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
162/*Result of last MAC1 operation overflowed, sticky for MAC*/
163#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
164/*Condition Code, used for holding comparison results*/
165#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
166/*Quotient Bit*/
167#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
168/*Rounding mode, set for biased, clear for unbiased*/
169#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
170/*Overflow Bit*/
171#define ASTAT_V MK_BMSK_(ASTAT_V_P)
172/*Overflow Bit*/
173#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
174
175/**************************************************
176 * SEQSTAT register
177 **************************************************/
178
179/* Bit Positions */
180#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
181#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
182#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
183#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
184#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
185#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
186#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
187 * set by IDLE instruction.
188 */
189#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
190 * reset was a software reset
191 * (=1)
192 */
193#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
194#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
195#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
196#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
197#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
198/* Masks */
199/* Exception cause */
200#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
201 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
202 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
203 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
204 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
205 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
206 0)
207
208/* Indicates whether the last reset was a software reset (=1) */
209#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
210
211/* Last hw error cause */
212#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
213 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
214 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
215 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
216 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
217 0)
218
219/* Translate bits to something useful */
220
221/* Last hw error cause */
222#define SEQSTAT_HWERRCAUSE_SHIFT (14)
223#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
224#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
225#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
226#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
227
228/**************************************************
229 * SYSCFG register
230 **************************************************/
231
232/* Bit Positions */
233#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
234 * set it forces an exception
235 * for each instruction executed
236 */
237#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
238#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
239
240/* Masks */
241
242/* Supervisor single step, when set it forces an exception for each
243 *instruction executed
244 */
245#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
246/* Enable cycle counter (=1) */
247#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
248/* Self Nesting Interrupt Enable */
249#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
250/* Backward-compatibility for typos in prior releases */
251#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
252#define SYSCFG_CCCEN SYSCFG_CCEN
253
254/****************************************************
255 * Core MMR Register Map
256 ****************************************************/
257
258/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
259
260#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
261#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
262#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
263 * Buffer Status
264 */
265#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
266#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
267 * Buffer Fault Address
268 */
269#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
270 * Buffer 0
271 */
272#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
273 * Buffer 1
274 */
275#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
276 * Buffer 2
277 */
278#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
279 * Lookaside Buffer 3
280 */
281#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
282 * Lookaside Buffer 4
283 */
284#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
285 * Lookaside Buffer 5
286 */
287#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
288 * Lookaside Buffer 6
289 */
290#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
291 * Lookaside Buffer 7
292 */
293#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
294 * Lookaside Buffer 8
295 */
296#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
297 * Lookaside Buffer 9
298 */
299#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
300 * Lookaside Buffer 10
301 */
302#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
303 * Lookaside Buffer 11
304 */
305#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
306 * Lookaside Buffer 12
307 */
308#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
309 * Lookaside Buffer 13
310 */
311#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
312 * Lookaside Buffer 14
313 */
314#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
315 * Lookaside Buffer 15
316 */
317#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
318#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
319#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
320#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
321#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
322#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
323#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
324#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
325#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
326#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
327#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
328#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
329#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
330#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
331#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
332#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
333#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
334
335#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
336#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
337#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
338
339/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
340
341#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
342#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
343#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
344#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
345#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
346#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
347 * Protection Lookaside Buffer 0
348 */
349#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
350 * Protection Lookaside Buffer 1
351 */
352#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
353 * Protection Lookaside Buffer 2
354 */
355#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
356 * Protection Lookaside Buffer 3
357 */
358#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
359 * Protection Lookaside Buffer 4
360 */
361#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
362 * Protection Lookaside Buffer 5
363 */
364#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
365 * Protection Lookaside Buffer 6
366 */
367#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
368 * Protection Lookaside Buffer 7
369 */
370#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
371 * Protection Lookaside Buffer 8
372 */
373#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
374 * Protection Lookaside Buffer 9
375 */
376#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
377 * Protection Lookaside Buffer 10
378 */
379#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
380 * Protection Lookaside Buffer 11
381 */
382#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
383 * Protection Lookaside Buffer 12
384 */
385#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
386 * Protection Lookaside Buffer 13
387 */
388#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
389 * Protection Lookaside Buffer 14
390 */
391#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
392 * Protection Lookaside Buffer 15
393 */
394#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
395#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
396#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
397#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
398#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
399#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
400#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
401#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
402#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
403#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
404#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
405#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
406#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
407#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
408#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
409#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
410#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
411#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
412#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
413
414/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
415
416#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
417#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
418#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
419#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
420#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
421#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
422#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
423#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
424#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
425#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
426#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
427#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
428#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
429#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
430#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
431#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
432#define IMASK 0xFFE02104 /* Interrupt Mask Register */
433#define IPEND 0xFFE02108 /* Interrupt Pending Register */
434#define ILAT 0xFFE0210C /* Interrupt Latch Register */
435#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
436
437/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
438
439#define TCNTL 0xFFE03000 /* Core Timer Control Register */
440#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
441#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
442#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
443
444/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
445#define DSPID 0xFFE05000 /* DSP Processor ID Register for
446 * MP implementations
447 */
448
449#define DBGSTAT 0xFFE05008 /* Debug Status Register */
450
451/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
452
453#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
454#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
455#define TBUF 0xFFE06100 /* Trace Buffer */
456
457/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
458
459/* Watchpoint Instruction Address Control Register */
460#define WPIACTL 0xFFE07000
461/* Watchpoint Instruction Address Register 0 */
462#define WPIA0 0xFFE07040
463/* Watchpoint Instruction Address Register 1 */
464#define WPIA1 0xFFE07044
465/* Watchpoint Instruction Address Register 2 */
466#define WPIA2 0xFFE07048
467/* Watchpoint Instruction Address Register 3 */
468#define WPIA3 0xFFE0704C
469/* Watchpoint Instruction Address Register 4 */
470#define WPIA4 0xFFE07050
471/* Watchpoint Instruction Address Register 5 */
472#define WPIA5 0xFFE07054
473/* Watchpoint Instruction Address Count Register 0 */
474#define WPIACNT0 0xFFE07080
475/* Watchpoint Instruction Address Count Register 1 */
476#define WPIACNT1 0xFFE07084
477/* Watchpoint Instruction Address Count Register 2 */
478#define WPIACNT2 0xFFE07088
479/* Watchpoint Instruction Address Count Register 3 */
480#define WPIACNT3 0xFFE0708C
481/* Watchpoint Instruction Address Count Register 4 */
482#define WPIACNT4 0xFFE07090
483/* Watchpoint Instruction Address Count Register 5 */
484#define WPIACNT5 0xFFE07094
485/* Watchpoint Data Address Control Register */
486#define WPDACTL 0xFFE07100
487/* Watchpoint Data Address Register 0 */
488#define WPDA0 0xFFE07140
489/* Watchpoint Data Address Register 1 */
490#define WPDA1 0xFFE07144
491/* Watchpoint Data Address Count Value Register 0 */
492#define WPDACNT0 0xFFE07180
493/* Watchpoint Data Address Count Value Register 1 */
494#define WPDACNT1 0xFFE07184
495/* Watchpoint Status Register */
496#define WPSTAT 0xFFE07200
497
498/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
499
500/* Performance Monitor Control Register */
501#define PFCTL 0xFFE08000
502/* Performance Monitor Counter Register 0 */
503#define PFCNTR0 0xFFE08100
504/* Performance Monitor Counter Register 1 */
505#define PFCNTR1 0xFFE08104
506
507/****************************************************
508 * Core MMR Register Bits
509 ****************************************************/
510
511/**************************************************
512 * EVT registers (ILAT, IMASK, and IPEND).
513 **************************************************/
514
515/* Bit Positions */
516#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
517#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
518#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
519#define EVT_EVX_P 0x00000003 /* Exception bit position */
520#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
521#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
522#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
523#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
524#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
525#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
526#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
527#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
528#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
529#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
530#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
531#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
532
533/* Masks */
534#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
535#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
536#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
537#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
538#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
539#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
540#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
541#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
542#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
543#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
544#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
545#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
546#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
547#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
548#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
549#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
550
551/**************************************************
552 * DMEM_CONTROL Register
553 **************************************************/
554/* Bit Positions */
555#define ENDM_P 0x00 /* (doesn't really exist) Enable
556 *Data Memory L1
557 */
558#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
559
560#define ENDCPLB_P 0x01 /* Enable DCPLBS */
561#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
562#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
563#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
564#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
565#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
566#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
567#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
568#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
569
570/* Masks */
571#define ENDM 0x00000001 /* (doesn't really exist) Enable
572 * Data Memory L1
573 */
574#define ENDCPLB 0x00000002 /* Enable DCPLB */
575#define ASRAM_BSRAM 0x00000000
576#define ACACHE_BSRAM 0x00000008
577#define ACACHE_BCACHE 0x0000000C
578#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
579#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
580#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
581
582/* IMEM_CONTROL Register */
583/* Bit Positions */
584#define ENIM_P 0x00 /* Enable L1 Code Memory */
585#define IMCTL_ENIM_P 0x00 /* "" (older define) */
586#define ENICPLB_P 0x01 /* Enable ICPLB */
587#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
588#define IMC_P 0x02 /* Enable */
589#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
590 * cache (0=SRAM)
591 */
592#define ILOC0_P 0x03 /* Lock Way 0 */
593#define ILOC1_P 0x04 /* Lock Way 1 */
594#define ILOC2_P 0x05 /* Lock Way 2 */
595#define ILOC3_P 0x06 /* Lock Way 3 */
596#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
597 * Priority
598 */
599/* Masks */
600#define ENIM 0x00000001 /* Enable L1 Code Memory */
601#define ENICPLB 0x00000002 /* Enable ICPLB */
602#define IMC 0x00000004 /* Configure L1 code memory as
603 * cache (0=SRAM)
604 */
605#define ILOC0 0x00000008 /* Lock Way 0 */
606#define ILOC1 0x00000010 /* Lock Way 1 */
607#define ILOC2 0x00000020 /* Lock Way 2 */
608#define ILOC3 0x00000040 /* Lock Way 3 */
609#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
610 * Priority
611 */
612
613/* TCNTL Masks */
614#define TMPWR 0x00000001 /* Timer Low Power Control,
615 * 0=low power mode, 1=active state
616 */
617#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
618#define TAUTORLD 0x00000004 /* Timer auto reload */
619#define TINT 0x00000008 /* Timer generated interrupt 0=no
620 * interrupt has been generated,
621 * 1=interrupt has been generated
622 * (sticky)
623 */
624
625/* DCPLB_DATA and ICPLB_DATA Registers */
626/* Bit Positions */
627#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
628#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
629 * locked
630 */
631#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
632 * allowed (user mode)
633 */
634/* Masks */
635#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
636#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
637 * locked
638 */
639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
640 * allowed (user mode)
641 */
642
643#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
644#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
645#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
646#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
647#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
648 * mapped to L1
649 */
650#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
651 * priority port
652 */
653#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
654 * in L1
655 */
656/* ICPLB_DATA only */
657#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
658 * 1=priority for non-replacement
659 */
660/* DCPLB_DATA only */
661#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
662 * access allowed (user mode)
663 */
664#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
665 * access allowed (supervisor mode)
666 */
667#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
668#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
669 * write-through writes,
670 * 1= allocate cache lines on
671 * write-through writes.
672 */
673#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
674
675#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
677/* TBUFCTL Masks */
678#define TBUFPWR 0x0001
679#define TBUFEN 0x0002
680#define TBUFOVF 0x0004
681#define TBUFCMPLP_SINGLE 0x0008
682#define TBUFCMPLP_DOUBLE 0x0010
683#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
684
685/* TBUFSTAT Masks */
686#define TBUFCNT 0x001F
687
688/* ITEST_COMMAND and DTEST_COMMAND Registers */
689/* Masks */
690#define TEST_READ 0x00000000 /* Read Access */
691#define TEST_WRITE 0x00000002 /* Write Access */
692#define TEST_TAG 0x00000000 /* Access TAG */
693#define TEST_DATA 0x00000004 /* Access DATA */
694#define TEST_DW0 0x00000000 /* Select Double Word 0 */
695#define TEST_DW1 0x00000008 /* Select Double Word 1 */
696#define TEST_DW2 0x00000010 /* Select Double Word 2 */
697#define TEST_DW3 0x00000018 /* Select Double Word 3 */
698#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
699#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
700#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
701#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
702#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
703#define TEST_WAY0 0x00000000 /* Access Way0 */
704#define TEST_WAY1 0x04000000 /* Access Way1 */
705/* ITEST_COMMAND only */
706#define TEST_WAY2 0x08000000 /* Access Way2 */
707#define TEST_WAY3 0x0C000000 /* Access Way3 */
708/* DTEST_COMMAND only */
709#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
710#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
711
712#endif /* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
new file mode 100644
index 000000000000..0889c3abb593
--- /dev/null
+++ b/arch/blackfin/include/asm/delay.h
@@ -0,0 +1,62 @@
1/*
2 * delay.h - delay functions
3 *
4 * Copyright (c) 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_DELAY_H__
10#define __ASM_DELAY_H__
11
12#include <mach/anomaly.h>
13
14static inline void __delay(unsigned long loops)
15{
16 if (ANOMALY_05000312) {
17 /* Interrupted loads to loop registers -> bad */
18 unsigned long tmp;
19 __asm__ __volatile__(
20 "[--SP] = LC0;"
21 "[--SP] = LT0;"
22 "[--SP] = LB0;"
23 "LSETUP (1f,1f) LC0 = %1;"
24 "1: NOP;"
25 /* We take advantage of the fact that LC0 is 0 at
26 * the end of the loop. Otherwise we'd need some
27 * NOPs after the CLI here.
28 */
29 "CLI %0;"
30 "LB0 = [SP++];"
31 "LT0 = [SP++];"
32 "LC0 = [SP++];"
33 "STI %0;"
34 : "=d" (tmp)
35 : "a" (loops)
36 );
37 } else
38 __asm__ __volatile__ (
39 "LSETUP(1f, 1f) LC0 = %0;"
40 "1: NOP;"
41 :
42 : "a" (loops)
43 : "LT0", "LB0", "LC0"
44 );
45}
46
47#include <linux/param.h> /* needed for HZ */
48
49/*
50 * Use only for very small delays ( < 1 msec). Should probably use a
51 * lookup table, really, as the multiplications take much too long with
52 * short delays. This is a "reasonable" implementation, though (and the
53 * first constant multiplications gets optimized away if the delay is
54 * a constant)
55 */
56static inline void udelay(unsigned long usecs)
57{
58 extern unsigned long loops_per_jiffy;
59 __delay(usecs * loops_per_jiffy / (1000000 / HZ));
60}
61
62#endif
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/arch/blackfin/include/asm/device.h
@@ -0,0 +1,7 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/arch/blackfin/include/asm/div64.h b/arch/blackfin/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/blackfin/include/asm/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..1a13c2fc3667
--- /dev/null
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -0,0 +1,83 @@
1#ifndef _BLACKFIN_DMA_MAPPING_H
2#define _BLACKFIN_DMA_MAPPING_H
3
4#include <asm/scatterlist.h>
5
6void dma_alloc_init(unsigned long start, unsigned long end);
7void *dma_alloc_coherent(struct device *dev, size_t size,
8 dma_addr_t *dma_handle, gfp_t gfp);
9void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
10 dma_addr_t dma_handle);
11
12/*
13 * Now for the API extensions over the pci_ one
14 */
15#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
16#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
17
18#define dma_mapping_error
19
20/*
21 * Map a single buffer of the indicated size for DMA in streaming mode.
22 * The 32-bit bus address to use is returned.
23 *
24 * Once the device is given the dma address, the device owns this memory
25 * until either pci_unmap_single or pci_dma_sync_single is performed.
26 */
27extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
28 enum dma_data_direction direction);
29
30static inline dma_addr_t
31dma_map_page(struct device *dev, struct page *page,
32 unsigned long offset, size_t size,
33 enum dma_data_direction dir)
34{
35 return dma_map_single(dev, page_address(page) + offset, size, dir);
36}
37
38/*
39 * Unmap a single streaming mode DMA translation. The dma_addr and size
40 * must match what was provided for in a previous pci_map_single call. All
41 * other usages are undefined.
42 *
43 * After this call, reads by the cpu to the buffer are guarenteed to see
44 * whatever the device wrote there.
45 */
46extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
47 enum dma_data_direction direction);
48
49static inline void
50dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
51 enum dma_data_direction dir)
52{
53 dma_unmap_single(dev, dma_addr, size, dir);
54}
55
56/*
57 * Map a set of buffers described by scatterlist in streaming
58 * mode for DMA. This is the scather-gather version of the
59 * above pci_map_single interface. Here the scatter gather list
60 * elements are each tagged with the appropriate dma address
61 * and length. They are obtained via sg_dma_{address,length}(SG).
62 *
63 * NOTE: An implementation may be able to use a smaller number of
64 * DMA address/length pairs than there are SG table elements.
65 * (for example via virtual mapping capabilities)
66 * The routine returns the number of addr/length pairs actually
67 * used, at most nents.
68 *
69 * Device ownership issues as mentioned above for pci_map_single are
70 * the same here.
71 */
72extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
73 enum dma_data_direction direction);
74
75/*
76 * Unmap a set of streaming mode DMA translations.
77 * Again, cpu read rules concerning calls here are the same as for
78 * pci_unmap_single() above.
79 */
80extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
81 int nhwentries, enum dma_data_direction direction);
82
83#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
new file mode 100644
index 000000000000..6509733bb0f6
--- /dev/null
+++ b/arch/blackfin/include/asm/dma.h
@@ -0,0 +1,205 @@
1/*
2 * File: include/asm-blackfin/simple_bf533_dma.h
3 * Based on: none - original work
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: This file contains the major Data structures and constants
8 * used for DMA Implementation in BF533
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _BLACKFIN_DMA_H_
30#define _BLACKFIN_DMA_H_
31
32#include <asm/io.h>
33#include <linux/slab.h>
34#include <asm/irq.h>
35#include <asm/signal.h>
36
37#include <linux/kernel.h>
38#include <mach/dma.h>
39#include <linux/mm.h>
40#include <linux/interrupt.h>
41#include <asm/blackfin.h>
42
43#define MAX_DMA_ADDRESS PAGE_OFFSET
44
45/*****************************************************************************
46* Generic DMA Declarations
47*
48****************************************************************************/
49enum dma_chan_status {
50 DMA_CHANNEL_FREE,
51 DMA_CHANNEL_REQUESTED,
52 DMA_CHANNEL_ENABLED,
53};
54
55/*-------------------------
56 * config reg bits value
57 *-------------------------*/
58#define DATA_SIZE_8 0
59#define DATA_SIZE_16 1
60#define DATA_SIZE_32 2
61
62#define DMA_FLOW_STOP 0
63#define DMA_FLOW_AUTO 1
64#define DMA_FLOW_ARRAY 4
65#define DMA_FLOW_SMALL 6
66#define DMA_FLOW_LARGE 7
67
68#define DIMENSION_LINEAR 0
69#define DIMENSION_2D 1
70
71#define DIR_READ 0
72#define DIR_WRITE 1
73
74#define INTR_DISABLE 0
75#define INTR_ON_BUF 2
76#define INTR_ON_ROW 3
77
78#define DMA_NOSYNC_KEEP_DMA_BUF 0
79#define DMA_SYNC_RESTART 1
80
81struct dmasg {
82 unsigned long next_desc_addr;
83 unsigned long start_addr;
84 unsigned short cfg;
85 unsigned short x_count;
86 short x_modify;
87 unsigned short y_count;
88 short y_modify;
89} __attribute__((packed));
90
91struct dma_register {
92 unsigned long next_desc_ptr; /* DMA Next Descriptor Pointer register */
93 unsigned long start_addr; /* DMA Start address register */
94
95 unsigned short cfg; /* DMA Configuration register */
96 unsigned short dummy1; /* DMA Configuration register */
97
98 unsigned long reserved;
99
100 unsigned short x_count; /* DMA x_count register */
101 unsigned short dummy2;
102
103 short x_modify; /* DMA x_modify register */
104 unsigned short dummy3;
105
106 unsigned short y_count; /* DMA y_count register */
107 unsigned short dummy4;
108
109 short y_modify; /* DMA y_modify register */
110 unsigned short dummy5;
111
112 unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer
113 register */
114 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
115 register */
116 unsigned short irq_status; /* DMA irq status register */
117 unsigned short dummy6;
118
119 unsigned short peripheral_map; /* DMA peripheral map register */
120 unsigned short dummy7;
121
122 unsigned short curr_x_count; /* DMA Current x-count register */
123 unsigned short dummy8;
124
125 unsigned long reserved2;
126
127 unsigned short curr_y_count; /* DMA Current y-count register */
128 unsigned short dummy9;
129
130 unsigned long reserved3;
131
132};
133
134typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
135
136struct dma_channel {
137 struct mutex dmalock;
138 char *device_id;
139 enum dma_chan_status chan_status;
140 struct dma_register *regs;
141 struct dmasg *sg; /* large mode descriptor */
142 unsigned int ctrl_num; /* controller number */
143 dma_interrupt_t irq_callback;
144 void *data;
145 unsigned int dma_enable_flag;
146 unsigned int loopback_flag;
147#ifdef CONFIG_PM
148 unsigned short saved_peripheral_map;
149#endif
150};
151
152#ifdef CONFIG_PM
153int blackfin_dma_suspend(void);
154void blackfin_dma_resume(void);
155#endif
156
157/*******************************************************************************
158* DMA API's
159*******************************************************************************/
160/* functions to set register mode */
161void set_dma_start_addr(unsigned int channel, unsigned long addr);
162void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
163void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
164void set_dma_x_count(unsigned int channel, unsigned short x_count);
165void set_dma_x_modify(unsigned int channel, short x_modify);
166void set_dma_y_count(unsigned int channel, unsigned short y_count);
167void set_dma_y_modify(unsigned int channel, short y_modify);
168void set_dma_config(unsigned int channel, unsigned short config);
169unsigned short set_bfin_dma_config(char direction, char flow_mode,
170 char intr_mode, char dma_mode, char width,
171 char syncmode);
172void set_dma_curr_addr(unsigned int channel, unsigned long addr);
173
174/* get curr status for polling */
175unsigned short get_dma_curr_irqstat(unsigned int channel);
176unsigned short get_dma_curr_xcount(unsigned int channel);
177unsigned short get_dma_curr_ycount(unsigned int channel);
178unsigned long get_dma_next_desc_ptr(unsigned int channel);
179unsigned long get_dma_curr_desc_ptr(unsigned int channel);
180unsigned long get_dma_curr_addr(unsigned int channel);
181
182/* set large DMA mode descriptor */
183void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
184
185/* check if current channel is in use */
186int dma_channel_active(unsigned int channel);
187
188/* common functions must be called in any mode */
189void free_dma(unsigned int channel);
190int dma_channel_active(unsigned int channel); /* check if a channel is in use */
191void disable_dma(unsigned int channel);
192void enable_dma(unsigned int channel);
193int request_dma(unsigned int channel, char *device_id);
194int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
195 void *data);
196void dma_disable_irq(unsigned int channel);
197void dma_enable_irq(unsigned int channel);
198void clear_dma_irqstat(unsigned int channel);
199void *dma_memcpy(void *dest, const void *src, size_t count);
200void *safe_dma_memcpy(void *dest, const void *src, size_t count);
201
202extern int channel2irq(unsigned int channel);
203extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
204
205#endif
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
new file mode 100644
index 000000000000..96e8208f929a
--- /dev/null
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -0,0 +1,57 @@
1/*
2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
3 * Management Controller Driver.
4 * Copyright (C) 2004-2008 Analog Device Inc.
5 *
6 */
7#ifndef _BLACKFIN_DPMC_H_
8#define _BLACKFIN_DPMC_H_
9
10#ifdef __KERNEL__
11#ifndef __ASSEMBLY__
12
13void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
14void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
15void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
16void do_hibernate(int wakeup);
17void set_dram_srfs(void);
18void unset_dram_srfs(void);
19
20#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
21
22struct bfin_dpmc_platform_data {
23 const unsigned int *tuple_tab;
24 unsigned short tabsize;
25 unsigned short vr_settling_time; /* in us */
26};
27
28#else
29
30#define PM_PUSH(x) \
31 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
32 [--SP] = R0;\
33
34#define PM_POP(x) \
35 R0 = [SP++];\
36 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
37
38#define PM_SYS_PUSH(x) \
39 R0 = [P0 + (x - PLL_CTL)];\
40 [--SP] = R0;\
41
42#define PM_SYS_POP(x) \
43 R0 = [SP++];\
44 [P0 + (x - PLL_CTL)] = R0;\
45
46#define PM_SYS_PUSH16(x) \
47 R0 = w[P0 + (x - PLL_CTL)];\
48 [--SP] = R0;\
49
50#define PM_SYS_POP16(x) \
51 R0 = [SP++];\
52 w[P0 + (x - PLL_CTL)] = R0;\
53
54#endif
55#endif /* __KERNEL__ */
56
57#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h
new file mode 100644
index 000000000000..110f1c1f845c
--- /dev/null
+++ b/arch/blackfin/include/asm/early_printk.h
@@ -0,0 +1,28 @@
1/*
2 * File: include/asm-blackfin/early_printk.h
3 * Author: Robin Getz <rgetz@blackfin.uclinux.org
4 *
5 * Created: 14Aug2007
6 * Description: function prototpyes for early printk
7 *
8 * Modified:
9 * Copyright 2004-2007 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#ifdef CONFIG_EARLY_PRINTK
25extern int setup_early_printk(char *);
26#else
27#define setup_early_printk(fmt) do { } while (0)
28#endif /* CONFIG_EARLY_PRINTK */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
new file mode 100644
index 000000000000..67a03a8a353e
--- /dev/null
+++ b/arch/blackfin/include/asm/elf.h
@@ -0,0 +1,127 @@
1/* Changes made by LG Soft Oct 2004*/
2
3#ifndef __ASMBFIN_ELF_H
4#define __ASMBFIN_ELF_H
5
6/*
7 * ELF register definitions..
8 */
9
10#include <asm/ptrace.h>
11#include <asm/user.h>
12
13/* Processor specific flags for the ELF header e_flags field. */
14#define EF_BFIN_PIC 0x00000001 /* -fpic */
15#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
16#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
17#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
18#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
19#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
20
21typedef unsigned long elf_greg_t;
22
23#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
24typedef elf_greg_t elf_gregset_t[ELF_NGREG];
25
26typedef struct user_bfinfp_struct elf_fpregset_t;
27/*
28 * This is used to ensure we don't load something for the wrong architecture.
29 */
30#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
31
32#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
33#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
34
35/* EM_BLACKFIN defined in linux/elf.h */
36
37/*
38 * These are used to set parameters in the core dumps.
39 */
40#define ELF_CLASS ELFCLASS32
41#define ELF_DATA ELFDATA2LSB
42#define ELF_ARCH EM_BLACKFIN
43
44#define ELF_PLAT_INIT(_r) _r->p1 = 0
45
46#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
47do { \
48 _regs->r7 = 0; \
49 _regs->p0 = _exec_map_addr; \
50 _regs->p1 = _interp_map_addr; \
51 _regs->p2 = _dynamic_addr; \
52} while(0)
53
54#define USE_ELF_CORE_DUMP
55#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
56#define ELF_EXEC_PAGESIZE 4096
57
58#define R_unused0 0 /* relocation type 0 is not defined */
59#define R_pcrel5m2 1 /*LSETUP part a */
60#define R_unused1 2 /* relocation type 2 is not defined */
61#define R_pcrel10 3 /* type 3, if cc jump <target> */
62#define R_pcrel12_jump 4 /* type 4, jump <target> */
63#define R_rimm16 5 /* type 0x5, rN = <target> */
64#define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
65#define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
66#define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */
67#define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */
68#define R_pcrel24 10 /* # 0xa call <target> , not expandable */
69#define R_unusedb 11 /* # 0xb not generated */
70#define R_unusedc 12 /* # 0xc not used */
71#define R_pcrel24_jump_l 13 /*0xd jump.l <target> */
72#define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
73#define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */
74#define R_byte_data 16 /* 0x10, .byte var = symbol */
75#define R_byte2_data 17 /* 0x11, .byte2 var = symbol */
76#define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
77#define R_pcrel11 19 /* 0x13, lsetup part b */
78#define R_unused14 20 /* 0x14, undefined */
79#define R_unused15 21 /* not generated by VDSP 3.5 */
80
81/* arithmetic relocations */
82#define R_push 0xE0
83#define R_const 0xE1
84#define R_add 0xE2
85#define R_sub 0xE3
86#define R_mult 0xE4
87#define R_div 0xE5
88#define R_mod 0xE6
89#define R_lshift 0xE7
90#define R_rshift 0xE8
91#define R_and 0xE9
92#define R_or 0xEA
93#define R_xor 0xEB
94#define R_land 0xEC
95#define R_lor 0xED
96#define R_len 0xEE
97#define R_neg 0xEF
98#define R_comp 0xF0
99#define R_page 0xF1
100#define R_hwpage 0xF2
101#define R_addr 0xF3
102
103/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
104 use of this is to invoke "./ld.so someprog" to test out a new version of
105 the loader. We need to make sure that it is out of the way of the program
106 that it will "exec", and that there is sufficient room for the brk. */
107
108#define ELF_ET_DYN_BASE 0xD0000000UL
109
110#define ELF_CORE_COPY_REGS(pr_reg, regs) \
111 memcpy((char *) &pr_reg, (char *)regs, \
112 sizeof(struct pt_regs));
113
114/* This yields a mask that user programs can use to figure out what
115 instruction set this cpu supports. */
116
117#define ELF_HWCAP (0)
118
119/* This yields a string that ld.so will use to load implementation
120 specific libraries for optimization. This is more specific in
121 intent than poking at uname or /proc/cpuinfo. */
122
123#define ELF_PLATFORM (NULL)
124
125#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
126
127#endif
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..27f6c785d103
--- /dev/null
+++ b/arch/blackfin/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
new file mode 100644
index 000000000000..c4f721e0d00d
--- /dev/null
+++ b/arch/blackfin/include/asm/entry.h
@@ -0,0 +1,61 @@
1#ifndef __BFIN_ENTRY_H
2#define __BFIN_ENTRY_H
3
4#include <asm/setup.h>
5#include <asm/page.h>
6
7#ifdef __ASSEMBLY__
8
9#define LFLUSH_I_AND_D 0x00000808
10#define LSIGTRAP 5
11
12/* process bits for task_struct.flags */
13#define PF_TRACESYS_OFF 3
14#define PF_TRACESYS_BIT 5
15#define PF_PTRACED_OFF 3
16#define PF_PTRACED_BIT 4
17#define PF_DTRACE_OFF 1
18#define PF_DTRACE_BIT 5
19
20/*
21 * NOTE! The single-stepping code assumes that all interrupt handlers
22 * start by saving SYSCFG on the stack with their first instruction.
23 */
24
25/* This one is used for exceptions, emulation, and NMI. It doesn't push
26 RETI and doesn't do cli. */
27#define SAVE_ALL_SYS save_context_no_interrupts
28/* This is used for all normal interrupts. It saves a minimum of registers
29 to the stack, loads the IRQ number, and jumps to common code. */
30#define INTERRUPT_ENTRY(N) \
31 [--sp] = SYSCFG; \
32 \
33 [--sp] = P0; /*orig_p0*/ \
34 [--sp] = R0; /*orig_r0*/ \
35 [--sp] = (R7:0,P5:0); \
36 R0 = (N); \
37 jump __common_int_entry;
38
39/* For timer interrupts, we need to save IPEND, since the user_mode
40 macro accesses it to determine where to account time. */
41#define TIMER_INTERRUPT_ENTRY(N) \
42 [--sp] = SYSCFG; \
43 \
44 [--sp] = P0; /*orig_p0*/ \
45 [--sp] = R0; /*orig_r0*/ \
46 [--sp] = (R7:0,P5:0); \
47 p0.l = lo(IPEND); \
48 p0.h = hi(IPEND); \
49 r1 = [p0]; \
50 R0 = (N); \
51 jump __common_int_entry;
52
53/* This one pushes RETI without using CLI. Interrupts are enabled. */
54#define SAVE_CONTEXT_SYSCALL save_context_syscall
55#define SAVE_CONTEXT save_context_with_interrupts
56
57#define RESTORE_ALL_SYS restore_context_no_interrupts
58#define RESTORE_CONTEXT restore_context_with_interrupts
59
60#endif /* __ASSEMBLY__ */
61#endif /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
new file mode 100644
index 000000000000..164e4f39bb57
--- /dev/null
+++ b/arch/blackfin/include/asm/errno.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_ERRNO_H
2#define _BFIN_ERRNO_H
3
4#include<asm-generic/errno.h>
5
6#endif /* _BFIN_ERRNO_H */
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h
new file mode 100644
index 000000000000..c7df38030992
--- /dev/null
+++ b/arch/blackfin/include/asm/fb.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3#include <linux/fb.h>
4
5#define fb_pgprotect(...) do {} while (0)
6
7static inline int fb_is_primary_device(struct fb_info *info)
8{
9 return 0;
10}
11
12#endif /* _ASM_FB_H_ */
diff --git a/arch/blackfin/include/asm/fcntl.h b/arch/blackfin/include/asm/fcntl.h
new file mode 100644
index 000000000000..9c4037127857
--- /dev/null
+++ b/arch/blackfin/include/asm/fcntl.h
@@ -0,0 +1,13 @@
1#ifndef _BFIN_FCNTL_H
2#define _BFIN_FCNTL_H
3
4/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
5 located on an ext2 file system */
6#define O_DIRECTORY 040000 /* must be a directory */
7#define O_NOFOLLOW 0100000 /* don't follow links */
8#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
9#define O_LARGEFILE 0400000
10
11#include <asm-generic/fcntl.h>
12
13#endif
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
new file mode 100644
index 000000000000..32c4d495d847
--- /dev/null
+++ b/arch/blackfin/include/asm/fixed_code.h
@@ -0,0 +1,46 @@
1/* This file defines the fixed addresses where userspace programs can find
2 atomic code sequences. */
3
4#ifndef __BFIN_ASM_FIXED_CODE_H__
5#define __BFIN_ASM_FIXED_CODE_H__
6
7#ifdef __KERNEL__
8#ifndef __ASSEMBLY__
9#include <linux/linkage.h>
10#include <linux/ptrace.h>
11extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
12extern char fixed_code_start;
13extern char fixed_code_end;
14extern int atomic_xchg32(void);
15extern int atomic_cas32(void);
16extern int atomic_add32(void);
17extern int atomic_sub32(void);
18extern int atomic_ior32(void);
19extern int atomic_and32(void);
20extern int atomic_xor32(void);
21extern void safe_user_instruction(void);
22extern void sigreturn_stub(void);
23#endif
24#endif
25
26#define FIXED_CODE_START 0x400
27
28#define SIGRETURN_STUB 0x400
29
30#define ATOMIC_SEQS_START 0x410
31
32#define ATOMIC_XCHG32 0x410
33#define ATOMIC_CAS32 0x420
34#define ATOMIC_ADD32 0x430
35#define ATOMIC_SUB32 0x440
36#define ATOMIC_IOR32 0x450
37#define ATOMIC_AND32 0x460
38#define ATOMIC_XOR32 0x470
39
40#define ATOMIC_SEQS_END 0x480
41
42#define SAFE_USER_INSTRUCTION 0x480
43
44#define FIXED_CODE_END 0x490
45
46#endif
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h
new file mode 100644
index 000000000000..e70074e05f4e
--- /dev/null
+++ b/arch/blackfin/include/asm/flat.h
@@ -0,0 +1,58 @@
1/*
2 * include/asm-blackfin/flat.h -- uClinux flat-format executables
3 *
4 * Copyright (C) 2003,
5 *
6 */
7
8#ifndef __BLACKFIN_FLAT_H__
9#define __BLACKFIN_FLAT_H__
10
11#include <asm/unaligned.h>
12
13#define flat_stack_align(sp) /* nothing needed */
14#define flat_argvp_envp_on_stack() 0
15#define flat_old_ram_flag(flags) (flags)
16
17extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
18 unsigned long relval,
19 unsigned long flags,
20 unsigned long *persistent);
21
22extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
23 unsigned long relval);
24
25/* The amount by which a relocation can exceed the program image limits
26 without being regarded as an error. */
27
28#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
29
30#define flat_get_addr_from_rp(rp, relval, flags, persistent) \
31 bfin_get_addr_from_rp(rp, relval, flags, persistent)
32#define flat_put_addr_at_rp(rp, val, relval) \
33 bfin_put_addr_at_rp(rp, val, relval)
34
35/* Convert a relocation entry into an address. */
36static inline unsigned long
37flat_get_relocate_addr (unsigned long relval)
38{
39 return relval & 0x03ffffff; /* Mask out top 6 bits */
40}
41
42static inline int flat_set_persistent(unsigned long relval,
43 unsigned long *persistent)
44{
45 int type = (relval >> 26) & 7;
46 if (type == 3) {
47 *persistent = relval << 16;
48 return 1;
49 }
50 return 0;
51}
52
53static inline int flat_addr_absolute(unsigned long relval)
54{
55 return (relval & (1 << 29)) != 0;
56}
57
58#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/arch/blackfin/include/asm/futex.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <asm-generic/futex.h>
5
6#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
new file mode 100644
index 000000000000..ad33ac271fd9
--- /dev/null
+++ b/arch/blackfin/include/asm/gpio.h
@@ -0,0 +1,456 @@
1/*
2 * File: arch/blackfin/kernel/bfin_gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2008 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31* Number BF537/6/4 BF561 BF533/2/1
32* BF527/5/2
33*
34* GPIO_0 PF0 PF0 PF0
35* GPIO_1 PF1 PF1 PF1
36* GPIO_2 PF2 PF2 PF2
37* GPIO_3 PF3 PF3 PF3
38* GPIO_4 PF4 PF4 PF4
39* GPIO_5 PF5 PF5 PF5
40* GPIO_6 PF6 PF6 PF6
41* GPIO_7 PF7 PF7 PF7
42* GPIO_8 PF8 PF8 PF8
43* GPIO_9 PF9 PF9 PF9
44* GPIO_10 PF10 PF10 PF10
45* GPIO_11 PF11 PF11 PF11
46* GPIO_12 PF12 PF12 PF12
47* GPIO_13 PF13 PF13 PF13
48* GPIO_14 PF14 PF14 PF14
49* GPIO_15 PF15 PF15 PF15
50* GPIO_16 PG0 PF16
51* GPIO_17 PG1 PF17
52* GPIO_18 PG2 PF18
53* GPIO_19 PG3 PF19
54* GPIO_20 PG4 PF20
55* GPIO_21 PG5 PF21
56* GPIO_22 PG6 PF22
57* GPIO_23 PG7 PF23
58* GPIO_24 PG8 PF24
59* GPIO_25 PG9 PF25
60* GPIO_26 PG10 PF26
61* GPIO_27 PG11 PF27
62* GPIO_28 PG12 PF28
63* GPIO_29 PG13 PF29
64* GPIO_30 PG14 PF30
65* GPIO_31 PG15 PF31
66* GPIO_32 PH0 PF32
67* GPIO_33 PH1 PF33
68* GPIO_34 PH2 PF34
69* GPIO_35 PH3 PF35
70* GPIO_36 PH4 PF36
71* GPIO_37 PH5 PF37
72* GPIO_38 PH6 PF38
73* GPIO_39 PH7 PF39
74* GPIO_40 PH8 PF40
75* GPIO_41 PH9 PF41
76* GPIO_42 PH10 PF42
77* GPIO_43 PH11 PF43
78* GPIO_44 PH12 PF44
79* GPIO_45 PH13 PF45
80* GPIO_46 PH14 PF46
81* GPIO_47 PH15 PF47
82*/
83
84#ifndef __ARCH_BLACKFIN_GPIO_H__
85#define __ARCH_BLACKFIN_GPIO_H__
86
87#define gpio_bank(x) ((x) >> 4)
88#define gpio_bit(x) (1<<((x) & 0xF))
89#define gpio_sub_n(x) ((x) & 0xF)
90
91#define GPIO_BANKSIZE 16
92
93#define GPIO_0 0
94#define GPIO_1 1
95#define GPIO_2 2
96#define GPIO_3 3
97#define GPIO_4 4
98#define GPIO_5 5
99#define GPIO_6 6
100#define GPIO_7 7
101#define GPIO_8 8
102#define GPIO_9 9
103#define GPIO_10 10
104#define GPIO_11 11
105#define GPIO_12 12
106#define GPIO_13 13
107#define GPIO_14 14
108#define GPIO_15 15
109#define GPIO_16 16
110#define GPIO_17 17
111#define GPIO_18 18
112#define GPIO_19 19
113#define GPIO_20 20
114#define GPIO_21 21
115#define GPIO_22 22
116#define GPIO_23 23
117#define GPIO_24 24
118#define GPIO_25 25
119#define GPIO_26 26
120#define GPIO_27 27
121#define GPIO_28 28
122#define GPIO_29 29
123#define GPIO_30 30
124#define GPIO_31 31
125#define GPIO_32 32
126#define GPIO_33 33
127#define GPIO_34 34
128#define GPIO_35 35
129#define GPIO_36 36
130#define GPIO_37 37
131#define GPIO_38 38
132#define GPIO_39 39
133#define GPIO_40 40
134#define GPIO_41 41
135#define GPIO_42 42
136#define GPIO_43 43
137#define GPIO_44 44
138#define GPIO_45 45
139#define GPIO_46 46
140#define GPIO_47 47
141
142
143#define PERIPHERAL_USAGE 1
144#define GPIO_USAGE 0
145
146#ifdef BF533_FAMILY
147#define MAX_BLACKFIN_GPIOS 16
148
149#define GPIO_PF0 0
150#define GPIO_PF1 1
151#define GPIO_PF2 2
152#define GPIO_PF3 3
153#define GPIO_PF4 4
154#define GPIO_PF5 5
155#define GPIO_PF6 6
156#define GPIO_PF7 7
157#define GPIO_PF8 8
158#define GPIO_PF9 9
159#define GPIO_PF10 10
160#define GPIO_PF11 11
161#define GPIO_PF12 12
162#define GPIO_PF13 13
163#define GPIO_PF14 14
164#define GPIO_PF15 15
165
166#endif
167
168#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
169#define MAX_BLACKFIN_GPIOS 48
170
171#define GPIO_PF0 0
172#define GPIO_PF1 1
173#define GPIO_PF2 2
174#define GPIO_PF3 3
175#define GPIO_PF4 4
176#define GPIO_PF5 5
177#define GPIO_PF6 6
178#define GPIO_PF7 7
179#define GPIO_PF8 8
180#define GPIO_PF9 9
181#define GPIO_PF10 10
182#define GPIO_PF11 11
183#define GPIO_PF12 12
184#define GPIO_PF13 13
185#define GPIO_PF14 14
186#define GPIO_PF15 15
187#define GPIO_PG0 16
188#define GPIO_PG1 17
189#define GPIO_PG2 18
190#define GPIO_PG3 19
191#define GPIO_PG4 20
192#define GPIO_PG5 21
193#define GPIO_PG6 22
194#define GPIO_PG7 23
195#define GPIO_PG8 24
196#define GPIO_PG9 25
197#define GPIO_PG10 26
198#define GPIO_PG11 27
199#define GPIO_PG12 28
200#define GPIO_PG13 29
201#define GPIO_PG14 30
202#define GPIO_PG15 31
203#define GPIO_PH0 32
204#define GPIO_PH1 33
205#define GPIO_PH2 34
206#define GPIO_PH3 35
207#define GPIO_PH4 36
208#define GPIO_PH5 37
209#define GPIO_PH6 38
210#define GPIO_PH7 39
211#define GPIO_PH8 40
212#define GPIO_PH9 41
213#define GPIO_PH10 42
214#define GPIO_PH11 43
215#define GPIO_PH12 44
216#define GPIO_PH13 45
217#define GPIO_PH14 46
218#define GPIO_PH15 47
219
220#define PORT_F GPIO_PF0
221#define PORT_G GPIO_PG0
222#define PORT_H GPIO_PH0
223
224#endif
225
226#ifdef BF548_FAMILY
227#include <mach/gpio.h>
228#endif
229
230#ifdef BF561_FAMILY
231#define MAX_BLACKFIN_GPIOS 48
232
233#define GPIO_PF0 0
234#define GPIO_PF1 1
235#define GPIO_PF2 2
236#define GPIO_PF3 3
237#define GPIO_PF4 4
238#define GPIO_PF5 5
239#define GPIO_PF6 6
240#define GPIO_PF7 7
241#define GPIO_PF8 8
242#define GPIO_PF9 9
243#define GPIO_PF10 10
244#define GPIO_PF11 11
245#define GPIO_PF12 12
246#define GPIO_PF13 13
247#define GPIO_PF14 14
248#define GPIO_PF15 15
249#define GPIO_PF16 16
250#define GPIO_PF17 17
251#define GPIO_PF18 18
252#define GPIO_PF19 19
253#define GPIO_PF20 20
254#define GPIO_PF21 21
255#define GPIO_PF22 22
256#define GPIO_PF23 23
257#define GPIO_PF24 24
258#define GPIO_PF25 25
259#define GPIO_PF26 26
260#define GPIO_PF27 27
261#define GPIO_PF28 28
262#define GPIO_PF29 29
263#define GPIO_PF30 30
264#define GPIO_PF31 31
265#define GPIO_PF32 32
266#define GPIO_PF33 33
267#define GPIO_PF34 34
268#define GPIO_PF35 35
269#define GPIO_PF36 36
270#define GPIO_PF37 37
271#define GPIO_PF38 38
272#define GPIO_PF39 39
273#define GPIO_PF40 40
274#define GPIO_PF41 41
275#define GPIO_PF42 42
276#define GPIO_PF43 43
277#define GPIO_PF44 44
278#define GPIO_PF45 45
279#define GPIO_PF46 46
280#define GPIO_PF47 47
281
282#define PORT_FIO0 GPIO_0
283#define PORT_FIO1 GPIO_16
284#define PORT_FIO2 GPIO_32
285#endif
286
287#ifndef __ASSEMBLY__
288
289/***********************************************************
290*
291* FUNCTIONS: Blackfin General Purpose Ports Access Functions
292*
293* INPUTS/OUTPUTS:
294* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
295*
296*
297* DESCRIPTION: These functions abstract direct register access
298* to Blackfin processor General Purpose
299* Ports Regsiters
300*
301* CAUTION: These functions do not belong to the GPIO Driver API
302*************************************************************
303* MODIFICATION HISTORY :
304**************************************************************/
305
306#ifndef BF548_FAMILY
307void set_gpio_dir(unsigned, unsigned short);
308void set_gpio_inen(unsigned, unsigned short);
309void set_gpio_polar(unsigned, unsigned short);
310void set_gpio_edge(unsigned, unsigned short);
311void set_gpio_both(unsigned, unsigned short);
312void set_gpio_data(unsigned, unsigned short);
313void set_gpio_maska(unsigned, unsigned short);
314void set_gpio_maskb(unsigned, unsigned short);
315void set_gpio_toggle(unsigned);
316void set_gpiop_dir(unsigned, unsigned short);
317void set_gpiop_inen(unsigned, unsigned short);
318void set_gpiop_polar(unsigned, unsigned short);
319void set_gpiop_edge(unsigned, unsigned short);
320void set_gpiop_both(unsigned, unsigned short);
321void set_gpiop_data(unsigned, unsigned short);
322void set_gpiop_maska(unsigned, unsigned short);
323void set_gpiop_maskb(unsigned, unsigned short);
324unsigned short get_gpio_dir(unsigned);
325unsigned short get_gpio_inen(unsigned);
326unsigned short get_gpio_polar(unsigned);
327unsigned short get_gpio_edge(unsigned);
328unsigned short get_gpio_both(unsigned);
329unsigned short get_gpio_maska(unsigned);
330unsigned short get_gpio_maskb(unsigned);
331unsigned short get_gpio_data(unsigned);
332unsigned short get_gpiop_dir(unsigned);
333unsigned short get_gpiop_inen(unsigned);
334unsigned short get_gpiop_polar(unsigned);
335unsigned short get_gpiop_edge(unsigned);
336unsigned short get_gpiop_both(unsigned);
337unsigned short get_gpiop_maska(unsigned);
338unsigned short get_gpiop_maskb(unsigned);
339unsigned short get_gpiop_data(unsigned);
340
341struct gpio_port_t {
342 unsigned short data;
343 unsigned short dummy1;
344 unsigned short data_clear;
345 unsigned short dummy2;
346 unsigned short data_set;
347 unsigned short dummy3;
348 unsigned short toggle;
349 unsigned short dummy4;
350 unsigned short maska;
351 unsigned short dummy5;
352 unsigned short maska_clear;
353 unsigned short dummy6;
354 unsigned short maska_set;
355 unsigned short dummy7;
356 unsigned short maska_toggle;
357 unsigned short dummy8;
358 unsigned short maskb;
359 unsigned short dummy9;
360 unsigned short maskb_clear;
361 unsigned short dummy10;
362 unsigned short maskb_set;
363 unsigned short dummy11;
364 unsigned short maskb_toggle;
365 unsigned short dummy12;
366 unsigned short dir;
367 unsigned short dummy13;
368 unsigned short polar;
369 unsigned short dummy14;
370 unsigned short edge;
371 unsigned short dummy15;
372 unsigned short both;
373 unsigned short dummy16;
374 unsigned short inen;
375};
376#endif
377
378#ifdef CONFIG_PM
379
380unsigned int bfin_pm_standby_setup(void);
381void bfin_pm_standby_restore(void);
382
383void bfin_gpio_pm_hibernate_restore(void);
384void bfin_gpio_pm_hibernate_suspend(void);
385
386#ifndef CONFIG_BF54x
387#define PM_WAKE_RISING 0x1
388#define PM_WAKE_FALLING 0x2
389#define PM_WAKE_HIGH 0x4
390#define PM_WAKE_LOW 0x8
391#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
392#define PM_WAKE_IGNORE 0xF0
393
394int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
395void gpio_pm_wakeup_free(unsigned gpio);
396
397struct gpio_port_s {
398 unsigned short data;
399 unsigned short maska;
400 unsigned short maskb;
401 unsigned short dir;
402 unsigned short polar;
403 unsigned short edge;
404 unsigned short both;
405 unsigned short inen;
406
407 unsigned short fer;
408 unsigned short reserved;
409 unsigned short mux;
410};
411#endif /*CONFIG_BF54x*/
412#endif /*CONFIG_PM*/
413/***********************************************************
414*
415* FUNCTIONS: Blackfin GPIO Driver
416*
417* INPUTS/OUTPUTS:
418* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
419*
420*
421* DESCRIPTION: Blackfin GPIO Driver API
422*
423* CAUTION:
424*************************************************************
425* MODIFICATION HISTORY :
426**************************************************************/
427
428int gpio_request(unsigned, const char *);
429void gpio_free(unsigned);
430
431void gpio_set_value(unsigned gpio, int arg);
432int gpio_get_value(unsigned gpio);
433
434#ifndef BF548_FAMILY
435#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
436#endif
437
438int gpio_direction_input(unsigned gpio);
439int gpio_direction_output(unsigned gpio, int value);
440
441#include <asm-generic/gpio.h> /* cansleep wrappers */
442#include <asm/irq.h>
443
444static inline int gpio_to_irq(unsigned gpio)
445{
446 return (gpio + GPIO_IRQ_BASE);
447}
448
449static inline int irq_to_gpio(unsigned irq)
450{
451 return (irq - GPIO_IRQ_BASE);
452}
453
454#endif /* __ASSEMBLY__ */
455
456#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
new file mode 100644
index 000000000000..0520d2aac8f3
--- /dev/null
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -0,0 +1,191 @@
1/*
2 * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
5 * Copyright (C) 2005 John DeHority
6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
7 *
8 * Licensed under the GPL-2.
9 */
10
11#ifndef _BLACKFIN_TIMERS_H_
12#define _BLACKFIN_TIMERS_H_
13
14#include <linux/types.h>
15#include <asm/blackfin.h>
16
17/*
18 * BF537/BF527: 8 timers:
19 */
20#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
21# define MAX_BLACKFIN_GPTIMERS 8
22# define TIMER0_GROUP_REG TIMER_ENABLE
23#endif
24/*
25 * BF54x: 11 timers (BF542: 8 timers):
26 */
27#if defined(BF548_FAMILY)
28# ifdef CONFIG_BF542
29# define MAX_BLACKFIN_GPTIMERS 8
30# else
31# define MAX_BLACKFIN_GPTIMERS 11
32# define TIMER8_GROUP_REG TIMER_ENABLE1
33# endif
34# define TIMER0_GROUP_REG TIMER_ENABLE0
35#endif
36/*
37 * BF561: 12 timers:
38 */
39#if defined(CONFIG_BF561)
40# define MAX_BLACKFIN_GPTIMERS 12
41# define TIMER0_GROUP_REG TMRS8_ENABLE
42# define TIMER8_GROUP_REG TMRS4_ENABLE
43#endif
44/*
45 * All others: 3 timers:
46 */
47#if !defined(MAX_BLACKFIN_GPTIMERS)
48# define MAX_BLACKFIN_GPTIMERS 3
49# define TIMER0_GROUP_REG TIMER_ENABLE
50#endif
51
52#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
53#define BFIN_TIMER_OCTET(x) ((x) >> 3)
54
55/* used in masks for timer_enable() and timer_disable() */
56#define TIMER0bit 0x0001 /* 0001b */
57#define TIMER1bit 0x0002 /* 0010b */
58#define TIMER2bit 0x0004 /* 0100b */
59#define TIMER3bit 0x0008
60#define TIMER4bit 0x0010
61#define TIMER5bit 0x0020
62#define TIMER6bit 0x0040
63#define TIMER7bit 0x0080
64#define TIMER8bit 0x0100
65#define TIMER9bit 0x0200
66#define TIMER10bit 0x0400
67#define TIMER11bit 0x0800
68
69#define TIMER0_id 0
70#define TIMER1_id 1
71#define TIMER2_id 2
72#define TIMER3_id 3
73#define TIMER4_id 4
74#define TIMER5_id 5
75#define TIMER6_id 6
76#define TIMER7_id 7
77#define TIMER8_id 8
78#define TIMER9_id 9
79#define TIMER10_id 10
80#define TIMER11_id 11
81
82/* associated timers for ppi framesync: */
83
84#if defined(CONFIG_BF561)
85# define FS0_1_TIMER_ID TIMER8_id
86# define FS0_2_TIMER_ID TIMER9_id
87# define FS1_1_TIMER_ID TIMER10_id
88# define FS1_2_TIMER_ID TIMER11_id
89# define FS0_1_TIMER_BIT TIMER8bit
90# define FS0_2_TIMER_BIT TIMER9bit
91# define FS1_1_TIMER_BIT TIMER10bit
92# define FS1_2_TIMER_BIT TIMER11bit
93# undef FS1_TIMER_ID
94# undef FS2_TIMER_ID
95# undef FS1_TIMER_BIT
96# undef FS2_TIMER_BIT
97#else
98# define FS1_TIMER_ID TIMER0_id
99# define FS2_TIMER_ID TIMER1_id
100# define FS1_TIMER_BIT TIMER0bit
101# define FS2_TIMER_BIT TIMER1bit
102#endif
103
104/*
105 * Timer Configuration Register Bits
106 */
107#define TIMER_ERR 0xC000
108#define TIMER_ERR_OVFL 0x4000
109#define TIMER_ERR_PROG_PER 0x8000
110#define TIMER_ERR_PROG_PW 0xC000
111#define TIMER_EMU_RUN 0x0200
112#define TIMER_TOGGLE_HI 0x0100
113#define TIMER_CLK_SEL 0x0080
114#define TIMER_OUT_DIS 0x0040
115#define TIMER_TIN_SEL 0x0020
116#define TIMER_IRQ_ENA 0x0010
117#define TIMER_PERIOD_CNT 0x0008
118#define TIMER_PULSE_HI 0x0004
119#define TIMER_MODE 0x0003
120#define TIMER_MODE_PWM 0x0001
121#define TIMER_MODE_WDTH 0x0002
122#define TIMER_MODE_EXT_CLK 0x0003
123
124/*
125 * Timer Status Register Bits
126 */
127#define TIMER_STATUS_TIMIL0 0x0001
128#define TIMER_STATUS_TIMIL1 0x0002
129#define TIMER_STATUS_TIMIL2 0x0004
130#define TIMER_STATUS_TIMIL3 0x00000008
131#define TIMER_STATUS_TIMIL4 0x00010000
132#define TIMER_STATUS_TIMIL5 0x00020000
133#define TIMER_STATUS_TIMIL6 0x00040000
134#define TIMER_STATUS_TIMIL7 0x00080000
135#define TIMER_STATUS_TIMIL8 0x0001
136#define TIMER_STATUS_TIMIL9 0x0002
137#define TIMER_STATUS_TIMIL10 0x0004
138#define TIMER_STATUS_TIMIL11 0x0008
139
140#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
141#define TIMER_STATUS_TOVF1 0x0020
142#define TIMER_STATUS_TOVF2 0x0040
143#define TIMER_STATUS_TOVF3 0x00000080
144#define TIMER_STATUS_TOVF4 0x00100000
145#define TIMER_STATUS_TOVF5 0x00200000
146#define TIMER_STATUS_TOVF6 0x00400000
147#define TIMER_STATUS_TOVF7 0x00800000
148#define TIMER_STATUS_TOVF8 0x0010
149#define TIMER_STATUS_TOVF9 0x0020
150#define TIMER_STATUS_TOVF10 0x0040
151#define TIMER_STATUS_TOVF11 0x0080
152
153/*
154 * Timer Slave Enable Status : write 1 to clear
155 */
156#define TIMER_STATUS_TRUN0 0x1000
157#define TIMER_STATUS_TRUN1 0x2000
158#define TIMER_STATUS_TRUN2 0x4000
159#define TIMER_STATUS_TRUN3 0x00008000
160#define TIMER_STATUS_TRUN4 0x10000000
161#define TIMER_STATUS_TRUN5 0x20000000
162#define TIMER_STATUS_TRUN6 0x40000000
163#define TIMER_STATUS_TRUN7 0x80000000
164#define TIMER_STATUS_TRUN 0xF000F000
165#define TIMER_STATUS_TRUN8 0x1000
166#define TIMER_STATUS_TRUN9 0x2000
167#define TIMER_STATUS_TRUN10 0x4000
168#define TIMER_STATUS_TRUN11 0x8000
169
170/* The actual gptimer API */
171
172void set_gptimer_pwidth (int timer_id, uint32_t width);
173uint32_t get_gptimer_pwidth (int timer_id);
174void set_gptimer_period (int timer_id, uint32_t period);
175uint32_t get_gptimer_period (int timer_id);
176uint32_t get_gptimer_count (int timer_id);
177uint16_t get_gptimer_intr (int timer_id);
178void clear_gptimer_intr (int timer_id);
179uint16_t get_gptimer_over (int timer_id);
180void clear_gptimer_over (int timer_id);
181void set_gptimer_config (int timer_id, uint16_t config);
182uint16_t get_gptimer_config (int timer_id);
183void set_gptimer_pulse_hi (int timer_id);
184void clear_gptimer_pulse_hi(int timer_id);
185void enable_gptimers (uint16_t mask);
186void disable_gptimers (uint16_t mask);
187uint16_t get_enabled_gptimers (void);
188uint32_t get_gptimer_status (int group);
189void set_gptimer_status (int group, uint32_t value);
190
191#endif
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
new file mode 100644
index 000000000000..b6b19f1b9dab
--- /dev/null
+++ b/arch/blackfin/include/asm/hardirq.h
@@ -0,0 +1,45 @@
1#ifndef __BFIN_HARDIRQ_H
2#define __BFIN_HARDIRQ_H
3
4#include <linux/cache.h>
5#include <linux/threads.h>
6#include <asm/irq.h>
7
8typedef struct {
9 unsigned int __softirq_pending;
10 unsigned int __syscall_count;
11 struct task_struct *__ksoftirqd_task;
12} ____cacheline_aligned irq_cpustat_t;
13
14#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
15
16/*
17 * We put the hardirq and softirq counter into the preemption
18 * counter. The bitmask has the following meaning:
19 *
20 * - bits 0-7 are the preemption count (max preemption depth: 256)
21 * - bits 8-15 are the softirq count (max # of softirqs: 256)
22 * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
23 *
24 * - ( bit 26 is the PREEMPT_ACTIVE flag. )
25 *
26 * PREEMPT_MASK: 0x000000ff
27 * HARDIRQ_MASK: 0x0000ff00
28 * SOFTIRQ_MASK: 0x00ff0000
29 */
30
31#if NR_IRQS > 256
32#define HARDIRQ_BITS 9
33#else
34#define HARDIRQ_BITS 8
35#endif
36
37#ifdef NR_IRQS
38# if (1 << HARDIRQ_BITS) < NR_IRQS
39# error HARDIRQ_BITS is too low!
40# endif
41#endif
42
43#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
44
45#endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
new file mode 100644
index 000000000000..5b51eaec012c
--- /dev/null
+++ b/arch/blackfin/include/asm/hw_irq.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_BFIN_HW_IRQ_H
2#define __ASM_BFIN_HW_IRQ_H
3
4/* Dummy include. */
5
6#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
new file mode 100644
index 000000000000..cbbf7ffdbbff
--- /dev/null
+++ b/arch/blackfin/include/asm/io.h
@@ -0,0 +1,212 @@
1#ifndef _BFIN_IO_H
2#define _BFIN_IO_H
3
4#ifdef __KERNEL__
5
6#ifndef __ASSEMBLY__
7#include <linux/types.h>
8#endif
9#include <linux/compiler.h>
10
11/*
12 * These are for ISA/PCI shared memory _only_ and should never be used
13 * on any other type of memory, including Zorro memory. They are meant to
14 * access the bus in the bus byte order which is little-endian!.
15 *
16 * readX/writeX() are used to access memory mapped devices. On some
17 * architectures the memory mapped IO stuff needs to be accessed
18 * differently. On the bfin architecture, we just read/write the
19 * memory location directly.
20 */
21#ifndef __ASSEMBLY__
22
23static inline unsigned char readb(const volatile void __iomem *addr)
24{
25 unsigned int val;
26 int tmp;
27
28 __asm__ __volatile__ ("cli %1;\n\t"
29 "NOP; NOP; SSYNC;\n\t"
30 "%0 = b [%2] (z);\n\t"
31 "sti %1;\n\t"
32 : "=d"(val), "=d"(tmp): "a"(addr)
33 );
34
35 return (unsigned char) val;
36}
37
38static inline unsigned short readw(const volatile void __iomem *addr)
39{
40 unsigned int val;
41 int tmp;
42
43 __asm__ __volatile__ ("cli %1;\n\t"
44 "NOP; NOP; SSYNC;\n\t"
45 "%0 = w [%2] (z);\n\t"
46 "sti %1;\n\t"
47 : "=d"(val), "=d"(tmp): "a"(addr)
48 );
49
50 return (unsigned short) val;
51}
52
53static inline unsigned int readl(const volatile void __iomem *addr)
54{
55 unsigned int val;
56 int tmp;
57
58 __asm__ __volatile__ ("cli %1;\n\t"
59 "NOP; NOP; SSYNC;\n\t"
60 "%0 = [%2];\n\t"
61 "sti %1;\n\t"
62 : "=d"(val), "=d"(tmp): "a"(addr)
63 );
64 return val;
65}
66
67#endif /* __ASSEMBLY__ */
68
69#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
70#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
71#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
72
73#define __raw_readb readb
74#define __raw_readw readw
75#define __raw_readl readl
76#define __raw_writeb writeb
77#define __raw_writew writew
78#define __raw_writel writel
79#define memset_io(a,b,c) memset((void *)(a),(b),(c))
80#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
81#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
82
83#define inb(addr) readb(addr)
84#define inw(addr) readw(addr)
85#define inl(addr) readl(addr)
86#define outb(x,addr) ((void) writeb(x,addr))
87#define outw(x,addr) ((void) writew(x,addr))
88#define outl(x,addr) ((void) writel(x,addr))
89
90#define inb_p(addr) inb(addr)
91#define inw_p(addr) inw(addr)
92#define inl_p(addr) inl(addr)
93#define outb_p(x,addr) outb(x,addr)
94#define outw_p(x,addr) outw(x,addr)
95#define outl_p(x,addr) outl(x,addr)
96
97#define ioread8_rep(a,d,c) insb(a,d,c)
98#define ioread16_rep(a,d,c) insw(a,d,c)
99#define ioread32_rep(a,d,c) insl(a,d,c)
100#define iowrite8_rep(a,s,c) outsb(a,s,c)
101#define iowrite16_rep(a,s,c) outsw(a,s,c)
102#define iowrite32_rep(a,s,c) outsl(a,s,c)
103
104#define ioread8(X) readb(X)
105#define ioread16(X) readw(X)
106#define ioread32(X) readl(X)
107#define iowrite8(val,X) writeb(val,X)
108#define iowrite16(val,X) writew(val,X)
109#define iowrite32(val,X) writel(val,X)
110
111#define IO_SPACE_LIMIT 0xffffffff
112
113/* Values for nocacheflag and cmode */
114#define IOMAP_NOCACHE_SER 1
115
116#ifndef __ASSEMBLY__
117
118extern void outsb(unsigned long port, const void *addr, unsigned long count);
119extern void outsw(unsigned long port, const void *addr, unsigned long count);
120extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
121extern void outsl(unsigned long port, const void *addr, unsigned long count);
122
123extern void insb(unsigned long port, void *addr, unsigned long count);
124extern void insw(unsigned long port, void *addr, unsigned long count);
125extern void insw_8(unsigned long port, void *addr, unsigned long count);
126extern void insl(unsigned long port, void *addr, unsigned long count);
127extern void insl_16(unsigned long port, void *addr, unsigned long count);
128
129extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
130extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
131extern void dma_outsl(unsigned long port, const void *addr, unsigned short count);
132
133extern void dma_insb(unsigned long port, void *addr, unsigned short count);
134extern void dma_insw(unsigned long port, void *addr, unsigned short count);
135extern void dma_insl(unsigned long port, void *addr, unsigned short count);
136
137/*
138 * Map some physical address range into the kernel address space.
139 */
140static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
141 int cacheflag)
142{
143 return (void __iomem *)physaddr;
144}
145
146/*
147 * Unmap a ioremap()ed region again
148 */
149static inline void iounmap(void *addr)
150{
151}
152
153/*
154 * __iounmap unmaps nearly everything, so be careful
155 * it doesn't free currently pointer/page tables anymore but it
156 * wans't used anyway and might be added later.
157 */
158static inline void __iounmap(void *addr, unsigned long size)
159{
160}
161
162/*
163 * Set new cache mode for some kernel address space.
164 * The caller must push data for that range itself, if such data may already
165 * be in the cache.
166 */
167static inline void kernel_set_cachemode(void *addr, unsigned long size,
168 int cmode)
169{
170}
171
172static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
173{
174 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
175}
176static inline void __iomem *ioremap_nocache(unsigned long physaddr,
177 unsigned long size)
178{
179 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
180}
181
182extern void blkfin_inv_cache_all(void);
183
184#endif
185
186#define ioport_map(port, nr) ((void __iomem*)(port))
187#define ioport_unmap(addr)
188
189/* Pages to physical address... */
190#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
191#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
192
193#define phys_to_virt(vaddr) ((void *) (vaddr))
194#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
195
196#define virt_to_bus virt_to_phys
197#define bus_to_virt phys_to_virt
198
199/*
200 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
201 * access
202 */
203#define xlate_dev_mem_ptr(p) __va(p)
204
205/*
206 * Convert a virtual cached pointer to an uncached pointer
207 */
208#define xlate_dev_kmem_ptr(p) p
209
210#endif /* __KERNEL__ */
211
212#endif /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/ioctl.h b/arch/blackfin/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/blackfin/include/asm/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/arch/blackfin/include/asm/ioctls.h b/arch/blackfin/include/asm/ioctls.h
new file mode 100644
index 000000000000..895e3173165d
--- /dev/null
+++ b/arch/blackfin/include/asm/ioctls.h
@@ -0,0 +1,87 @@
1#ifndef __ARCH_BFIN_IOCTLS_H__
2#define __ARCH_BFIN_IOCTLS_H__
3
4#include <asm/ioctl.h>
5
6/* 0x54 is just a magic number to make these relatively unique ('T') */
7
8#define TCGETS 0x5401
9#define TCSETS 0x5402
10#define TCSETSW 0x5403
11#define TCSETSF 0x5404
12#define TCGETA 0x5405
13#define TCSETA 0x5406
14#define TCSETAW 0x5407
15#define TCSETAF 0x5408
16#define TCSBRK 0x5409
17#define TCXONC 0x540A
18#define TCFLSH 0x540B
19#define TIOCEXCL 0x540C
20#define TIOCNXCL 0x540D
21#define TIOCSCTTY 0x540E
22#define TIOCGPGRP 0x540F
23#define TIOCSPGRP 0x5410
24#define TIOCOUTQ 0x5411
25#define TIOCSTI 0x5412
26#define TIOCGWINSZ 0x5413
27#define TIOCSWINSZ 0x5414
28#define TIOCMGET 0x5415
29#define TIOCMBIS 0x5416
30#define TIOCMBIC 0x5417
31#define TIOCMSET 0x5418
32#define TIOCGSOFTCAR 0x5419
33#define TIOCSSOFTCAR 0x541A
34#define FIONREAD 0x541B
35#define TIOCINQ FIONREAD
36#define TIOCLINUX 0x541C
37#define TIOCCONS 0x541D
38#define TIOCGSERIAL 0x541E
39#define TIOCSSERIAL 0x541F
40#define TIOCPKT 0x5420
41#define FIONBIO 0x5421
42#define TIOCNOTTY 0x5422
43#define TIOCSETD 0x5423
44#define TIOCGETD 0x5424
45#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
46#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
47#define TIOCSBRK 0x5427 /* BSD compatibility */
48#define TIOCCBRK 0x5428 /* BSD compatibility */
49#define TIOCGSID 0x5429 /* Return the session ID of FD */
50#define TCGETS2 _IOR('T', 0x2A, struct termios2)
51#define TCSETS2 _IOW('T', 0x2B, struct termios2)
52#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
53#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
54/* Get Pty Number (of pty-mux device) */
55#define TIOCGPTN _IOR('T', 0x30, unsigned int)
56#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
57
58#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
59#define FIOCLEX 0x5451
60#define FIOASYNC 0x5452
61#define TIOCSERCONFIG 0x5453
62#define TIOCSERGWILD 0x5454
63#define TIOCSERSWILD 0x5455
64#define TIOCGLCKTRMIOS 0x5456
65#define TIOCSLCKTRMIOS 0x5457
66#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
67#define TIOCSERGETLSR 0x5459 /* Get line status register */
68#define TIOCSERGETMULTI 0x545A /* Get multiport config */
69#define TIOCSERSETMULTI 0x545B /* Set multiport config */
70
71#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
72#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
73
74#define FIOQSIZE 0x545E
75
76/* Used for packet mode */
77#define TIOCPKT_DATA 0
78#define TIOCPKT_FLUSHREAD 1
79#define TIOCPKT_FLUSHWRITE 2
80#define TIOCPKT_STOP 4
81#define TIOCPKT_START 8
82#define TIOCPKT_NOSTOP 16
83#define TIOCPKT_DOSTOP 32
84
85#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
86
87#endif /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..8f0899cdf4d2
--- /dev/null
+++ b/arch/blackfin/include/asm/ipcbuf.h
@@ -0,0 +1,30 @@
1/* Changes origined from m68k version. Lineo Inc. May 2001 */
2
3#ifndef __BFIN_IPCBUF_H__
4#define __BFIN_IPCBUF_H__
5
6/*
7 * The user_ipc_perm structure for m68k architecture.
8 * Note extra padding because this structure is passed back and forth
9 * between kernel and user space.
10 *
11 * Pad space is left for:
12 * - 32-bit mode_t and seq
13 * - 2 miscellaneous 32-bit values
14 */
15
16struct ipc64_perm {
17 __kernel_key_t key;
18 __kernel_uid32_t uid;
19 __kernel_gid32_t gid;
20 __kernel_uid32_t cuid;
21 __kernel_gid32_t cgid;
22 __kernel_mode_t mode;
23 unsigned short __pad1;
24 unsigned short seq;
25 unsigned short __pad2;
26 unsigned long __unused1;
27 unsigned long __unused2;
28};
29
30#endif /* __BFIN_IPCBUF_H__ */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
new file mode 100644
index 000000000000..89f59e18af93
--- /dev/null
+++ b/arch/blackfin/include/asm/irq.h
@@ -0,0 +1,72 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file COPYING in the main directory of this archive
4 * for more details.
5 *
6 * Changed by HuTao Apr18, 2003
7 *
8 * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
9 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
10 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
11 *
12 * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
13 * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
14 * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
15 */
16
17#ifndef _BFIN_IRQ_H_
18#define _BFIN_IRQ_H_
19
20#include <mach/irq.h>
21#include <asm/ptrace.h>
22
23/*******************************************************************************
24 ***** INTRODUCTION ***********
25 * On the Blackfin, the interrupt structure allows remmapping of the hardware
26 * levels.
27 * - I'm going to assume that the H/W level is going to stay at the default
28 * settings. If someone wants to go through and abstart this out, feel free
29 * to mod the interrupt numbering scheme.
30 * - I'm abstracting the interrupts so that uClinux does not know anything
31 * about the H/W levels. If you want to change the H/W AND keep the abstracted
32 * levels that uClinux sees, you should be able to do most of it here.
33 * - I've left the "abstract" numbering sparce in case someone wants to pull the
34 * interrupts apart (just the TX/RX for the various devices)
35 *******************************************************************************/
36
37/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
38
39/*
40 * Machine specific interrupt sources.
41 *
42 * Adding an interrupt service routine for a source with this bit
43 * set indicates a special machine specific interrupt source.
44 * The machine specific files define these sources.
45 *
46 * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
47 * introduce unnecessary overhead.
48 *
49 * All interrupt handling is actually machine specific so it is better
50 * to use function pointers, as used by the Sparc port, and select the
51 * interrupt handling functions when initializing the kernel. This way
52 * we save some unnecessary overhead at run-time.
53 * 01/11/97 - Jes
54 */
55
56extern void ack_bad_irq(unsigned int irq);
57
58static __inline__ int irq_canonicalize(int irq)
59{
60 return irq;
61}
62
63/* count of spurious interrupts */
64/* extern volatile unsigned int num_spurious; */
65
66#ifndef NO_IRQ
67#define NO_IRQ ((unsigned int)(-1))
68#endif
69
70#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
71
72#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
new file mode 100644
index 000000000000..139b5208f9d8
--- /dev/null
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -0,0 +1,33 @@
1#ifndef _IRQ_HANDLER_H
2#define _IRQ_HANDLER_H
3
4#include <linux/types.h>
5#include <linux/linkage.h>
6
7/* BASE LEVEL interrupt handler routines */
8asmlinkage void evt_exception(void);
9asmlinkage void trap(void);
10asmlinkage void evt_ivhw(void);
11asmlinkage void evt_timer(void);
12asmlinkage void evt_nmi(void);
13asmlinkage void evt_evt7(void);
14asmlinkage void evt_evt8(void);
15asmlinkage void evt_evt9(void);
16asmlinkage void evt_evt10(void);
17asmlinkage void evt_evt11(void);
18asmlinkage void evt_evt12(void);
19asmlinkage void evt_evt13(void);
20asmlinkage void evt_soft_int1(void);
21asmlinkage void evt_system_call(void);
22asmlinkage void init_exception_buff(void);
23asmlinkage void trap_c(struct pt_regs *fp);
24asmlinkage void ex_replaceable(void);
25asmlinkage void early_trap(void);
26
27extern void *ex_table[];
28extern void return_from_exception(void);
29
30extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
31extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
32
33#endif
diff --git a/arch/blackfin/include/asm/irq_regs.h b/arch/blackfin/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/blackfin/include/asm/irq_regs.h
@@ -0,0 +1 @@
#include <asm-generic/irq_regs.h>
diff --git a/arch/blackfin/include/asm/kdebug.h b/arch/blackfin/include/asm/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/arch/blackfin/include/asm/kdebug.h
@@ -0,0 +1 @@
#include <asm-generic/kdebug.h>
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
new file mode 100644
index 000000000000..0f73847fd6bc
--- /dev/null
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -0,0 +1,184 @@
1/*
2 * File: include/asm-blackfin/kgdb.h
3 * Based on:
4 * Author: Sonic Zhang
5 *
6 * Created:
7 * Description:
8 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#ifndef __ASM_BLACKFIN_KGDB_H__
33#define __ASM_BLACKFIN_KGDB_H__
34
35#include <linux/ptrace.h>
36
37/* gdb locks */
38#define KGDB_MAX_NO_CPUS 8
39
40/************************************************************************/
41/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
42/* at least NUMREGBYTES*2 are needed for register packets */
43/* Longer buffer is needed to list all threads */
44#define BUFMAX 2048
45
46/*
47 * Note that this register image is different from
48 * the register image that Linux produces at interrupt time.
49 *
50 * Linux's register image is defined by struct pt_regs in ptrace.h.
51 */
52enum regnames {
53 /* Core Registers */
54 BFIN_R0 = 0,
55 BFIN_R1,
56 BFIN_R2,
57 BFIN_R3,
58 BFIN_R4,
59 BFIN_R5,
60 BFIN_R6,
61 BFIN_R7,
62 BFIN_P0,
63 BFIN_P1,
64 BFIN_P2,
65 BFIN_P3,
66 BFIN_P4,
67 BFIN_P5,
68 BFIN_SP,
69 BFIN_FP,
70 BFIN_I0,
71 BFIN_I1,
72 BFIN_I2,
73 BFIN_I3,
74 BFIN_M0,
75 BFIN_M1,
76 BFIN_M2,
77 BFIN_M3,
78 BFIN_B0,
79 BFIN_B1,
80 BFIN_B2,
81 BFIN_B3,
82 BFIN_L0,
83 BFIN_L1,
84 BFIN_L2,
85 BFIN_L3,
86 BFIN_A0_DOT_X,
87 BFIN_A0_DOT_W,
88 BFIN_A1_DOT_X,
89 BFIN_A1_DOT_W,
90 BFIN_ASTAT,
91 BFIN_RETS,
92 BFIN_LC0,
93 BFIN_LT0,
94 BFIN_LB0,
95 BFIN_LC1,
96 BFIN_LT1,
97 BFIN_LB1,
98 BFIN_CYCLES,
99 BFIN_CYCLES2,
100 BFIN_USP,
101 BFIN_SEQSTAT,
102 BFIN_SYSCFG,
103 BFIN_RETI,
104 BFIN_RETX,
105 BFIN_RETN,
106 BFIN_RETE,
107
108 /* Pseudo Registers */
109 BFIN_PC,
110 BFIN_CC,
111 BFIN_EXTRA1, /* Address of .text section. */
112 BFIN_EXTRA2, /* Address of .data section. */
113 BFIN_EXTRA3, /* Address of .bss section. */
114 BFIN_FDPIC_EXEC,
115 BFIN_FDPIC_INTERP,
116
117 /* MMRs */
118 BFIN_IPEND,
119
120 /* LAST ENTRY SHOULD NOT BE CHANGED. */
121 BFIN_NUM_REGS /* The number of all registers. */
122};
123
124/* Number of bytes of registers. */
125#define NUMREGBYTES BFIN_NUM_REGS*4
126
127#define BREAKPOINT() asm(" EXCPT 2;");
128#define BREAK_INSTR_SIZE 2
129#define HW_BREAKPOINT_NUM 6
130
131/* Instruction watchpoint address control register bits mask */
132#define WPPWR 0x1
133#define WPIREN01 0x2
134#define WPIRINV01 0x4
135#define WPIAEN0 0x8
136#define WPIAEN1 0x10
137#define WPICNTEN0 0x20
138#define WPICNTEN1 0x40
139#define EMUSW0 0x80
140#define EMUSW1 0x100
141#define WPIREN23 0x200
142#define WPIRINV23 0x400
143#define WPIAEN2 0x800
144#define WPIAEN3 0x1000
145#define WPICNTEN2 0x2000
146#define WPICNTEN3 0x4000
147#define EMUSW2 0x8000
148#define EMUSW3 0x10000
149#define WPIREN45 0x20000
150#define WPIRINV45 0x40000
151#define WPIAEN4 0x80000
152#define WPIAEN5 0x100000
153#define WPICNTEN4 0x200000
154#define WPICNTEN5 0x400000
155#define EMUSW4 0x800000
156#define EMUSW5 0x1000000
157#define WPAND 0x2000000
158
159/* Data watchpoint address control register bits mask */
160#define WPDREN01 0x1
161#define WPDRINV01 0x2
162#define WPDAEN0 0x4
163#define WPDAEN1 0x8
164#define WPDCNTEN0 0x10
165#define WPDCNTEN1 0x20
166#define WPDSRC0 0xc0
167#define WPDACC0 0x300
168#define WPDSRC1 0xc00
169#define WPDACC1 0x3000
170
171/* Watchpoint status register bits mask */
172#define STATIA0 0x1
173#define STATIA1 0x2
174#define STATIA2 0x4
175#define STATIA3 0x8
176#define STATIA4 0x10
177#define STATIA5 0x20
178#define STATDA0 0x40
179#define STATDA1 0x80
180
181extern void kgdb_print(const char *fmt, ...);
182extern void init_kgdb_uart(void);
183
184#endif
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
new file mode 100644
index 000000000000..e215f7104974
--- /dev/null
+++ b/arch/blackfin/include/asm/kmap_types.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H
3
4enum km_type {
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20
21#endif
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
new file mode 100644
index 000000000000..c13ded777828
--- /dev/null
+++ b/arch/blackfin/include/asm/l1layout.h
@@ -0,0 +1,31 @@
1/*
2 * l1layout.h
3 * Defines a layout of L1 scratchpad memory that userspace can rely on.
4 */
5
6#ifndef _L1LAYOUT_H_
7#define _L1LAYOUT_H_
8
9#include <asm/blackfin.h>
10
11#ifndef __ASSEMBLY__
12
13/* Data that is "mapped" into the process VM at the start of the L1 scratch
14 memory, so that each process can access it at a fixed address. Used for
15 stack checking. */
16struct l1_scratch_task_info
17{
18 /* Points to the start of the stack. */
19 void *stack_start;
20 /* Not updated by the kernel; a user process can modify this to
21 keep track of the lowest address of the stack pointer during its
22 runtime. */
23 void *lowest_sp;
24};
25
26/* A pointer to the structure in memory. */
27#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
28
29#endif
30
31#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
new file mode 100644
index 000000000000..5a822bb790f7
--- /dev/null
+++ b/arch/blackfin/include/asm/linkage.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#define __ALIGN .align 4
5#define __ALIGN_STR ".align 4"
6
7#endif
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h
new file mode 100644
index 000000000000..75afffbc6421
--- /dev/null
+++ b/arch/blackfin/include/asm/local.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_LOCAL_H
2#define __BLACKFIN_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __BLACKFIN_LOCAL_H */
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
new file mode 100644
index 000000000000..88d04a707708
--- /dev/null
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -0,0 +1,12 @@
1/*
2 * mem_map.h
3 * Common header file for blackfin family of processors.
4 *
5 */
6
7#ifndef _MEM_MAP_H_
8#define _MEM_MAP_H_
9
10#include <mach/mem_map.h>
11
12#endif /* _MEM_MAP_H_ */
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h
new file mode 100644
index 000000000000..b58f5ad3f024
--- /dev/null
+++ b/arch/blackfin/include/asm/mman.h
@@ -0,0 +1,43 @@
1#ifndef __BFIN_MMAN_H__
2#define __BFIN_MMAN_H__
3
4#define PROT_READ 0x1 /* page can be read */
5#define PROT_WRITE 0x2 /* page can be written */
6#define PROT_EXEC 0x4 /* page can be executed */
7#define PROT_SEM 0x8 /* page may be used for atomic ops */
8#define PROT_NONE 0x0 /* page can not be accessed */
9#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
10#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
11
12#define MAP_SHARED 0x01 /* Share changes */
13#define MAP_PRIVATE 0x02 /* Changes are private */
14#define MAP_TYPE 0x0f /* Mask for type of mapping */
15#define MAP_FIXED 0x10 /* Interpret addr exactly */
16#define MAP_ANONYMOUS 0x20 /* don't use a file */
17
18#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
19#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
20#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
21#define MAP_LOCKED 0x2000 /* pages are locked */
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25
26#define MS_ASYNC 1 /* sync memory asynchronously */
27#define MS_INVALIDATE 2 /* invalidate the caches */
28#define MS_SYNC 4 /* synchronous memory sync */
29
30#define MCL_CURRENT 1 /* lock all current mappings */
31#define MCL_FUTURE 2 /* lock all future mappings */
32
33#define MADV_NORMAL 0x0 /* default page-in behavior */
34#define MADV_RANDOM 0x1 /* page-in minimum required */
35#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
36#define MADV_WILLNEED 0x3 /* pre-fault pages */
37#define MADV_DONTNEED 0x4 /* discard these pages */
38
39/* compatibility flags */
40#define MAP_ANON MAP_ANONYMOUS
41#define MAP_FILE 0
42
43#endif /* __BFIN_MMAN_H__ */
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
new file mode 100644
index 000000000000..757e43906ed4
--- /dev/null
+++ b/arch/blackfin/include/asm/mmu.h
@@ -0,0 +1,32 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5
6struct sram_list_struct {
7 struct sram_list_struct *next;
8 void *addr;
9 size_t length;
10};
11
12typedef struct {
13 struct vm_list_struct *vmlist;
14 unsigned long end_brk;
15 unsigned long stack_start;
16
17 /* Points to the location in SDRAM where the L1 stack is normally
18 saved, or NULL if the stack is always in SDRAM. */
19 void *l1_stack_save;
20
21 struct sram_list_struct *sram_list;
22
23#ifdef CONFIG_BINFMT_ELF_FDPIC
24 unsigned long exec_fdpic_loadmap;
25 unsigned long interp_fdpic_loadmap;
26#endif
27#ifdef CONFIG_MPU
28 unsigned long *page_rwx_mask;
29#endif
30} mm_context_t;
31
32#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
new file mode 100644
index 000000000000..8529552a981f
--- /dev/null
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -0,0 +1,183 @@
1/*
2 * File: include/asm-blackfin/mmu_context.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BLACKFIN_MMU_CONTEXT_H__
31#define __BLACKFIN_MMU_CONTEXT_H__
32
33#include <linux/gfp.h>
34#include <linux/sched.h>
35#include <asm/setup.h>
36#include <asm/page.h>
37#include <asm/pgalloc.h>
38#include <asm/cplbinit.h>
39
40extern void *current_l1_stack_save;
41extern int nr_l1stack_tasks;
42extern void *l1_stack_base;
43extern unsigned long l1_stack_len;
44
45extern int l1sram_free(const void*);
46extern void *l1sram_alloc_max(void*);
47
48static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
49{
50}
51
52/* Called when creating a new context during fork() or execve(). */
53static inline int
54init_new_context(struct task_struct *tsk, struct mm_struct *mm)
55{
56#ifdef CONFIG_MPU
57 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
58 mm->context.page_rwx_mask = (unsigned long *)p;
59 memset(mm->context.page_rwx_mask, 0,
60 page_mask_nelts * 3 * sizeof(long));
61#endif
62 return 0;
63}
64
65static inline void free_l1stack(void)
66{
67 nr_l1stack_tasks--;
68 if (nr_l1stack_tasks == 0)
69 l1sram_free(l1_stack_base);
70}
71static inline void destroy_context(struct mm_struct *mm)
72{
73 struct sram_list_struct *tmp;
74
75 if (current_l1_stack_save == mm->context.l1_stack_save)
76 current_l1_stack_save = NULL;
77 if (mm->context.l1_stack_save)
78 free_l1stack();
79
80 while ((tmp = mm->context.sram_list)) {
81 mm->context.sram_list = tmp->next;
82 sram_free(tmp->addr);
83 kfree(tmp);
84 }
85#ifdef CONFIG_MPU
86 if (current_rwx_mask == mm->context.page_rwx_mask)
87 current_rwx_mask = NULL;
88 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
89#endif
90}
91
92static inline unsigned long
93alloc_l1stack(unsigned long length, unsigned long *stack_base)
94{
95 if (nr_l1stack_tasks == 0) {
96 l1_stack_base = l1sram_alloc_max(&l1_stack_len);
97 if (!l1_stack_base)
98 return 0;
99 }
100
101 if (l1_stack_len < length) {
102 if (nr_l1stack_tasks == 0)
103 l1sram_free(l1_stack_base);
104 return 0;
105 }
106 *stack_base = (unsigned long)l1_stack_base;
107 nr_l1stack_tasks++;
108 return l1_stack_len;
109}
110
111static inline int
112activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
113{
114 if (current_l1_stack_save)
115 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
116 mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
117 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
118 return 1;
119}
120
121#define deactivate_mm(tsk,mm) do { } while (0)
122
123#define activate_mm(prev, next) switch_mm(prev, next, NULL)
124
125static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
126 struct task_struct *tsk)
127{
128 if (prev_mm == next_mm)
129 return;
130#ifdef CONFIG_MPU
131 if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
132 flush_switched_cplbs();
133 set_mask_dcplbs(next_mm->context.page_rwx_mask);
134 }
135#endif
136
137 /* L1 stack switching. */
138 if (!next_mm->context.l1_stack_save)
139 return;
140 if (next_mm->context.l1_stack_save == current_l1_stack_save)
141 return;
142 if (current_l1_stack_save) {
143 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
144 }
145 current_l1_stack_save = next_mm->context.l1_stack_save;
146 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
147}
148
149#ifdef CONFIG_MPU
150static inline void protect_page(struct mm_struct *mm, unsigned long addr,
151 unsigned long flags)
152{
153 unsigned long *mask = mm->context.page_rwx_mask;
154 unsigned long page = addr >> 12;
155 unsigned long idx = page >> 5;
156 unsigned long bit = 1 << (page & 31);
157
158 if (flags & VM_MAYREAD)
159 mask[idx] |= bit;
160 else
161 mask[idx] &= ~bit;
162 mask += page_mask_nelts;
163 if (flags & VM_MAYWRITE)
164 mask[idx] |= bit;
165 else
166 mask[idx] &= ~bit;
167 mask += page_mask_nelts;
168 if (flags & VM_MAYEXEC)
169 mask[idx] |= bit;
170 else
171 mask[idx] &= ~bit;
172}
173
174static inline void update_protections(struct mm_struct *mm)
175{
176 if (mm->context.page_rwx_mask == current_rwx_mask) {
177 flush_switched_cplbs();
178 set_mask_dcplbs(mm->context.page_rwx_mask);
179 }
180}
181#endif
182
183#endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
new file mode 100644
index 000000000000..e3128df139d6
--- /dev/null
+++ b/arch/blackfin/include/asm/module.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_BFIN_MODULE_H
2#define _ASM_BFIN_MODULE_H
3
4#define MODULE_SYMBOL_PREFIX "_"
5
6#define Elf_Shdr Elf32_Shdr
7#define Elf_Sym Elf32_Sym
8#define Elf_Ehdr Elf32_Ehdr
9
10struct mod_arch_specific {
11 Elf_Shdr *text_l1;
12 Elf_Shdr *data_a_l1;
13 Elf_Shdr *bss_a_l1;
14 Elf_Shdr *data_b_l1;
15 Elf_Shdr *bss_b_l1;
16 Elf_Shdr *text_l2;
17 Elf_Shdr *data_l2;
18 Elf_Shdr *bss_l2;
19};
20#endif /* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h
new file mode 100644
index 000000000000..6fcbe8cd801d
--- /dev/null
+++ b/arch/blackfin/include/asm/msgbuf.h
@@ -0,0 +1,31 @@
1#ifndef _BFIN_MSGBUF_H
2#define _BFIN_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17 unsigned long __unused1;
18 __kernel_time_t msg_rtime; /* last msgrcv time */
19 unsigned long __unused2;
20 __kernel_time_t msg_ctime; /* last change time */
21 unsigned long __unused3;
22 unsigned long msg_cbytes; /* current number of bytes on queue */
23 unsigned long msg_qnum; /* number of messages in queue */
24 unsigned long msg_qbytes; /* max number of bytes on queue */
25 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
26 __kernel_pid_t msg_lrpid; /* last receive pid */
27 unsigned long __unused4;
28 unsigned long __unused5;
29};
30
31#endif /* _BFIN_MSGBUF_H */
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/blackfin/include/asm/mutex.h
@@ -0,0 +1,9 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
new file mode 100644
index 000000000000..afbaafa793f1
--- /dev/null
+++ b/arch/blackfin/include/asm/nand.h
@@ -0,0 +1,47 @@
1/* linux/include/asm-blackfin/nand.h
2 *
3 * Copyright (c) 2007 Analog Devices, Inc.
4 * Bryan Wu <bryan.wu@analog.com>
5 *
6 * BF5XX - NAND flash controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/* struct bf5xx_nand_platform
14 *
15 * define a interface between platfrom board specific code and
16 * bf54x NFC driver.
17 *
18 * nr_partitions = number of partitions pointed to be partitoons (or zero)
19 * partitions = mtd partition list
20 */
21
22#define NFC_PG_SIZE_256 0
23#define NFC_PG_SIZE_512 1
24#define NFC_PG_SIZE_OFFSET 9
25
26#define NFC_NWIDTH_8 0
27#define NFC_NWIDTH_16 1
28#define NFC_NWIDTH_OFFSET 8
29
30#define NFC_RDDLY_OFFSET 4
31#define NFC_WRDLY_OFFSET 0
32
33#define NFC_STAT_NBUSY 1
34
35struct bf5xx_nand_platform {
36 /* NAND chip information */
37 unsigned short page_size;
38 unsigned short data_width;
39
40 /* RD/WR strobe delay timing information, all times in SCLK cycles */
41 unsigned short rd_dly;
42 unsigned short wr_dly;
43
44 /* NAND MTD partition information */
45 int nr_partitions;
46 struct mtd_partition *partitions;
47};
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
new file mode 100644
index 000000000000..344f6a8c1f22
--- /dev/null
+++ b/arch/blackfin/include/asm/page.h
@@ -0,0 +1,88 @@
1#ifndef _BLACKFIN_PAGE_H
2#define _BLACKFIN_PAGE_H
3
4/* PAGE_SHIFT determines the page size */
5
6#define PAGE_SHIFT 12
7#ifdef __ASSEMBLY__
8#define PAGE_SIZE (1 << PAGE_SHIFT)
9#else
10#define PAGE_SIZE (1UL << PAGE_SHIFT)
11#endif
12#define PAGE_MASK (~(PAGE_SIZE-1))
13
14#include <asm/setup.h>
15
16#ifndef __ASSEMBLY__
17
18#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
19#define free_user_page(page, addr) free_page(addr)
20
21#define clear_page(page) memset((page), 0, PAGE_SIZE)
22#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
23
24#define clear_user_page(page, vaddr,pg) clear_page(page)
25#define copy_user_page(to, from, vaddr,pg) copy_page(to, from)
26
27/*
28 * These are used to make use of C type-checking..
29 */
30typedef struct {
31 unsigned long pte;
32} pte_t;
33typedef struct {
34 unsigned long pmd[16];
35} pmd_t;
36typedef struct {
37 unsigned long pgd;
38} pgd_t;
39typedef struct {
40 unsigned long pgprot;
41} pgprot_t;
42typedef struct page *pgtable_t;
43
44#define pte_val(x) ((x).pte)
45#define pmd_val(x) ((&x)->pmd[0])
46#define pgd_val(x) ((x).pgd)
47#define pgprot_val(x) ((x).pgprot)
48
49#define __pte(x) ((pte_t) { (x) } )
50#define __pmd(x) ((pmd_t) { (x) } )
51#define __pgd(x) ((pgd_t) { (x) } )
52#define __pgprot(x) ((pgprot_t) { (x) } )
53
54extern unsigned long memory_start;
55extern unsigned long memory_end;
56
57#endif /* !__ASSEMBLY__ */
58
59#include <asm/page_offset.h>
60#include <asm/io.h>
61
62#define PAGE_OFFSET (PAGE_OFFSET_RAW)
63
64#ifndef __ASSEMBLY__
65
66#define __pa(vaddr) virt_to_phys((void *)(vaddr))
67#define __va(paddr) phys_to_virt((unsigned long)(paddr))
68
69#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
70
71#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
72#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
73#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
74#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
75#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
76
77#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
78#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
79#define pfn_valid(pfn) ((pfn) < max_mapnr)
80
81#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
82 ((void *)(kaddr) < (void *)memory_end))
83
84#include <asm-generic/page.h>
85
86#endif /* __ASSEMBLY__ */
87
88#endif /* _BLACKFIN_PAGE_H */
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
new file mode 100644
index 000000000000..cbaff24b4b25
--- /dev/null
+++ b/arch/blackfin/include/asm/page_offset.h
@@ -0,0 +1,6 @@
1
2/* This handles the memory map.. */
3
4#ifdef CONFIG_BLACKFIN
5#define PAGE_OFFSET_RAW 0x00000000
6#endif
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h
new file mode 100644
index 000000000000..41564a6347f8
--- /dev/null
+++ b/arch/blackfin/include/asm/param.h
@@ -0,0 +1,22 @@
1#ifndef _BLACKFIN_PARAM_H
2#define _BLACKFIN_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ
6#define USER_HZ 100
7#define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _BLACKFIN_PARAM_H */
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
new file mode 100644
index 000000000000..61277358c865
--- /dev/null
+++ b/arch/blackfin/include/asm/pci.h
@@ -0,0 +1,148 @@
1/* Changed from asm-m68k version, Lineo Inc. May 2001 */
2
3#ifndef _ASM_BFIN_PCI_H
4#define _ASM_BFIN_PCI_H
5
6#include <asm/scatterlist.h>
7
8/*
9 *
10 * Written by Wout Klaren.
11 */
12
13/* Added by Chang Junxiao */
14#define PCIBIOS_MIN_IO 0x00001000
15#define PCIBIOS_MIN_MEM 0x10000000
16
17#define PCI_DMA_BUS_IS_PHYS (1)
18struct pci_ops;
19
20/*
21 * Structure with hardware dependent information and functions of the
22 * PCI bus.
23 */
24struct pci_bus_info {
25
26 /*
27 * Resources of the PCI bus.
28 */
29 struct resource mem_space;
30 struct resource io_space;
31
32 /*
33 * System dependent functions.
34 */
35 struct pci_ops *bfin_pci_ops;
36 void (*fixup) (int pci_modify);
37 void (*conf_device) (unsigned char bus, unsigned char device_fn);
38};
39
40#define pcibios_assign_all_busses() 0
41static inline void pcibios_set_master(struct pci_dev *dev)
42{
43
44 /* No special bus mastering setup handling */
45}
46static inline void pcibios_penalize_isa_irq(int irq)
47{
48
49 /* We don't do dynamic PCI IRQ allocation */
50}
51static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
52 size_t size, int direction)
53{
54 if (direction == PCI_DMA_NONE)
55 BUG();
56
57 /* return virt_to_bus(ptr); */
58 return (dma_addr_t) ptr;
59}
60
61/* Unmap a single streaming mode DMA translation. The dma_addr and size
62 * must match what was provided for in a previous pci_map_single call. All
63 * other usages are undefined.
64 *
65 * After this call, reads by the cpu to the buffer are guarenteed to see
66 * whatever the device wrote there.
67 */
68static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
69 size_t size, int direction)
70{
71 if (direction == PCI_DMA_NONE)
72 BUG();
73
74 /* Nothing to do */
75}
76
77/* Map a set of buffers described by scatterlist in streaming
78 * mode for DMA. This is the scather-gather version of the
79 * above pci_map_single interface. Here the scatter gather list
80 * elements are each tagged with the appropriate dma address
81 * and length. They are obtained via sg_dma_{address,length}(SG).
82 *
83 * NOTE: An implementation may be able to use a smaller number of
84 * DMA address/length pairs than there are SG table elements.
85 * (for example via virtual mapping capabilities)
86 * The routine returns the number of addr/length pairs actually
87 * used, at most nents.
88 *
89 * Device ownership issues as mentioned above for pci_map_single are
90 * the same here.
91 */
92static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
93 int nents, int direction)
94{
95 if (direction == PCI_DMA_NONE)
96 BUG();
97 return nents;
98}
99
100/* Unmap a set of streaming mode DMA translations.
101 * Again, cpu read rules concerning calls here are the same as for
102 * pci_unmap_single() above.
103 */
104static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
105 int nents, int direction)
106{
107 if (direction == PCI_DMA_NONE)
108 BUG();
109
110 /* Nothing to do */
111}
112
113/* Make physical memory consistent for a single
114 * streaming mode DMA translation after a transfer.
115 *
116 * If you perform a pci_map_single() but wish to interrogate the
117 * buffer using the cpu, yet do not wish to teardown the PCI dma
118 * mapping, you must call this function before doing so. At the
119 * next point you give the PCI dma address back to the card, the
120 * device again owns the buffer.
121 */
122static inline void pci_dma_sync_single(struct pci_dev *hwdev,
123 dma_addr_t dma_handle, size_t size,
124 int direction)
125{
126 if (direction == PCI_DMA_NONE)
127 BUG();
128
129 /* Nothing to do */
130}
131
132/* Make physical memory consistent for a set of streaming
133 * mode DMA translations after a transfer.
134 *
135 * The same as pci_dma_sync_single but for a scatter-gather list,
136 * same rules and usage.
137 */
138static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
139 struct scatterlist *sg, int nelems,
140 int direction)
141{
142 if (direction == PCI_DMA_NONE)
143 BUG();
144
145 /* Nothing to do */
146}
147
148#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
new file mode 100644
index 000000000000..78dd61f6b39f
--- /dev/null
+++ b/arch/blackfin/include/asm/percpu.h
@@ -0,0 +1,6 @@
1#ifndef __ARCH_BLACKFIN_PERCPU__
2#define __ARCH_BLACKFIN_PERCPU__
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h
new file mode 100644
index 000000000000..c686e0542fd0
--- /dev/null
+++ b/arch/blackfin/include/asm/pgalloc.h
@@ -0,0 +1,8 @@
1#ifndef _BLACKFIN_PGALLOC_H
2#define _BLACKFIN_PGALLOC_H
3
4#include <asm/setup.h>
5
6#define check_pgt_cache() do { } while (0)
7
8#endif /* _BLACKFIN_PGALLOC_H */
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
new file mode 100644
index 000000000000..f11684e4ade7
--- /dev/null
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -0,0 +1,96 @@
1#ifndef _BLACKFIN_PGTABLE_H
2#define _BLACKFIN_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6#include <asm/page.h>
7#include <asm/def_LPBlackfin.h>
8
9typedef pte_t *pte_addr_t;
10/*
11* Trivial page table functions.
12*/
13#define pgd_present(pgd) (1)
14#define pgd_none(pgd) (0)
15#define pgd_bad(pgd) (0)
16#define pgd_clear(pgdp)
17#define kern_addr_valid(addr) (1)
18
19#define pmd_offset(a, b) ((void *)0)
20#define pmd_none(x) (!pmd_val(x))
21#define pmd_present(x) (pmd_val(x))
22#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
23#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
24
25#define kern_addr_valid(addr) (1)
26
27#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
28#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
29#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
30#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
31#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
32
33extern void paging_init(void);
34
35#define __swp_type(x) (0)
36#define __swp_offset(x) (0)
37#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
38#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
39#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
40
41static inline int pte_file(pte_t pte)
42{
43 return 0;
44}
45
46#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
47#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
48
49/*
50 * Page assess control based on Blackfin CPLB management
51 */
52#define _PAGE_RD (CPLB_USER_RD)
53#define _PAGE_WR (CPLB_USER_WR)
54#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
55#define _PAGE_ACCESSED CPLB_ALL_ACCESS
56#define _PAGE_DIRTY (CPLB_DIRTY)
57
58#define PTE_BIT_FUNC(fn, op) \
59 static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
60
61PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
62PTE_BIT_FUNC(mkread, |= _PAGE_RD);
63PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
64PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
65PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
66PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
67PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
68PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
69PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
70PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
71
72/*
73 * ZERO_PAGE is a global shared page that is always zero: used
74 * for zero-mapped memory areas etc..
75 */
76#define ZERO_PAGE(vaddr) (virt_to_page(0))
77
78extern unsigned int kobjsize(const void *objp);
79
80#define swapper_pg_dir ((pgd_t *) 0)
81/*
82 * No page table caches to initialise.
83 */
84#define pgtable_cache_init() do { } while (0)
85#define io_remap_pfn_range remap_pfn_range
86
87/*
88 * All 32bit addresses are effectively valid for vmalloc...
89 * Sort of meaningless for non-VM targets.
90 */
91#define VMALLOC_START 0
92#define VMALLOC_END 0xffffffff
93
94#include <asm-generic/pgtable.h>
95
96#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/arch/blackfin/include/asm/poll.h b/arch/blackfin/include/asm/poll.h
new file mode 100644
index 000000000000..94cc2636e0e2
--- /dev/null
+++ b/arch/blackfin/include/asm/poll.h
@@ -0,0 +1,24 @@
1#ifndef __BFIN_POLL_H
2#define __BFIN_POLL_H
3
4#define POLLIN 1
5#define POLLPRI 2
6#define POLLOUT 4
7#define POLLERR 8
8#define POLLHUP 16
9#define POLLNVAL 32
10#define POLLRDNORM 64
11#define POLLWRNORM POLLOUT
12#define POLLRDBAND 128
13#define POLLWRBAND 256
14#define POLLMSG 0x0400
15#define POLLREMOVE 0x1000
16#define POLLRDHUP 0x2000
17
18struct pollfd {
19 int fd;
20 short events;
21 short revents;
22};
23
24#endif /* __BFIN_POLL_H */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
new file mode 100644
index 000000000000..88eb5c07cc24
--- /dev/null
+++ b/arch/blackfin/include/asm/portmux.h
@@ -0,0 +1,1188 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _PORTMUX_H_
7#define _PORTMUX_H_
8
9#define P_IDENT(x) ((x) & 0x1FF)
10#define P_FUNCT(x) (((x) & 0x3) << 9)
11#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
12#define P_DEFINED 0x8000
13#define P_UNDEF 0x4000
14#define P_MAYSHARE 0x2000
15#define P_DONTCARE 0x1000
16
17
18int peripheral_request(unsigned short per, const char *label);
19void peripheral_free(unsigned short per);
20int peripheral_request_list(const unsigned short per[], const char *label);
21void peripheral_free_list(const unsigned short per[]);
22
23#include <asm/gpio.h>
24#include <mach/portmux.h>
25
26#ifndef P_SPORT2_TFS
27#define P_SPORT2_TFS P_UNDEF
28#endif
29
30#ifndef P_SPORT2_DTSEC
31#define P_SPORT2_DTSEC P_UNDEF
32#endif
33
34#ifndef P_SPORT2_DTPRI
35#define P_SPORT2_DTPRI P_UNDEF
36#endif
37
38#ifndef P_SPORT2_TSCLK
39#define P_SPORT2_TSCLK P_UNDEF
40#endif
41
42#ifndef P_SPORT2_RFS
43#define P_SPORT2_RFS P_UNDEF
44#endif
45
46#ifndef P_SPORT2_DRSEC
47#define P_SPORT2_DRSEC P_UNDEF
48#endif
49
50#ifndef P_SPORT2_DRPRI
51#define P_SPORT2_DRPRI P_UNDEF
52#endif
53
54#ifndef P_SPORT2_RSCLK
55#define P_SPORT2_RSCLK P_UNDEF
56#endif
57
58#ifndef P_SPORT3_TFS
59#define P_SPORT3_TFS P_UNDEF
60#endif
61
62#ifndef P_SPORT3_DTSEC
63#define P_SPORT3_DTSEC P_UNDEF
64#endif
65
66#ifndef P_SPORT3_DTPRI
67#define P_SPORT3_DTPRI P_UNDEF
68#endif
69
70#ifndef P_SPORT3_TSCLK
71#define P_SPORT3_TSCLK P_UNDEF
72#endif
73
74#ifndef P_SPORT3_RFS
75#define P_SPORT3_RFS P_UNDEF
76#endif
77
78#ifndef P_SPORT3_DRSEC
79#define P_SPORT3_DRSEC P_UNDEF
80#endif
81
82#ifndef P_SPORT3_DRPRI
83#define P_SPORT3_DRPRI P_UNDEF
84#endif
85
86#ifndef P_SPORT3_RSCLK
87#define P_SPORT3_RSCLK P_UNDEF
88#endif
89
90#ifndef P_TMR4
91#define P_TMR4 P_UNDEF
92#endif
93
94#ifndef P_TMR5
95#define P_TMR5 P_UNDEF
96#endif
97
98#ifndef P_TMR6
99#define P_TMR6 P_UNDEF
100#endif
101
102#ifndef P_TMR7
103#define P_TMR7 P_UNDEF
104#endif
105
106#ifndef P_TWI1_SCL
107#define P_TWI1_SCL P_UNDEF
108#endif
109
110#ifndef P_TWI1_SDA
111#define P_TWI1_SDA P_UNDEF
112#endif
113
114#ifndef P_UART3_RTS
115#define P_UART3_RTS P_UNDEF
116#endif
117
118#ifndef P_UART3_CTS
119#define P_UART3_CTS P_UNDEF
120#endif
121
122#ifndef P_UART2_TX
123#define P_UART2_TX P_UNDEF
124#endif
125
126#ifndef P_UART2_RX
127#define P_UART2_RX P_UNDEF
128#endif
129
130#ifndef P_UART3_TX
131#define P_UART3_TX P_UNDEF
132#endif
133
134#ifndef P_UART3_RX
135#define P_UART3_RX P_UNDEF
136#endif
137
138#ifndef P_SPI2_SS
139#define P_SPI2_SS P_UNDEF
140#endif
141
142#ifndef P_SPI2_SSEL1
143#define P_SPI2_SSEL1 P_UNDEF
144#endif
145
146#ifndef P_SPI2_SSEL2
147#define P_SPI2_SSEL2 P_UNDEF
148#endif
149
150#ifndef P_SPI2_SSEL3
151#define P_SPI2_SSEL3 P_UNDEF
152#endif
153
154#ifndef P_SPI2_SSEL4
155#define P_SPI2_SSEL4 P_UNDEF
156#endif
157
158#ifndef P_SPI2_SSEL5
159#define P_SPI2_SSEL5 P_UNDEF
160#endif
161
162#ifndef P_SPI2_SSEL6
163#define P_SPI2_SSEL6 P_UNDEF
164#endif
165
166#ifndef P_SPI2_SSEL7
167#define P_SPI2_SSEL7 P_UNDEF
168#endif
169
170#ifndef P_SPI2_SCK
171#define P_SPI2_SCK P_UNDEF
172#endif
173
174#ifndef P_SPI2_MOSI
175#define P_SPI2_MOSI P_UNDEF
176#endif
177
178#ifndef P_SPI2_MISO
179#define P_SPI2_MISO P_UNDEF
180#endif
181
182#ifndef P_TMR0
183#define P_TMR0 P_UNDEF
184#endif
185
186#ifndef P_TMR1
187#define P_TMR1 P_UNDEF
188#endif
189
190#ifndef P_TMR2
191#define P_TMR2 P_UNDEF
192#endif
193
194#ifndef P_TMR3
195#define P_TMR3 P_UNDEF
196#endif
197
198#ifndef P_SPORT0_TFS
199#define P_SPORT0_TFS P_UNDEF
200#endif
201
202#ifndef P_SPORT0_DTSEC
203#define P_SPORT0_DTSEC P_UNDEF
204#endif
205
206#ifndef P_SPORT0_DTPRI
207#define P_SPORT0_DTPRI P_UNDEF
208#endif
209
210#ifndef P_SPORT0_TSCLK
211#define P_SPORT0_TSCLK P_UNDEF
212#endif
213
214#ifndef P_SPORT0_RFS
215#define P_SPORT0_RFS P_UNDEF
216#endif
217
218#ifndef P_SPORT0_DRSEC
219#define P_SPORT0_DRSEC P_UNDEF
220#endif
221
222#ifndef P_SPORT0_DRPRI
223#define P_SPORT0_DRPRI P_UNDEF
224#endif
225
226#ifndef P_SPORT0_RSCLK
227#define P_SPORT0_RSCLK P_UNDEF
228#endif
229
230#ifndef P_SD_D0
231#define P_SD_D0 P_UNDEF
232#endif
233
234#ifndef P_SD_D1
235#define P_SD_D1 P_UNDEF
236#endif
237
238#ifndef P_SD_D2
239#define P_SD_D2 P_UNDEF
240#endif
241
242#ifndef P_SD_D3
243#define P_SD_D3 P_UNDEF
244#endif
245
246#ifndef P_SD_CLK
247#define P_SD_CLK P_UNDEF
248#endif
249
250#ifndef P_SD_CMD
251#define P_SD_CMD P_UNDEF
252#endif
253
254#ifndef P_MMCLK
255#define P_MMCLK P_UNDEF
256#endif
257
258#ifndef P_MBCLK
259#define P_MBCLK P_UNDEF
260#endif
261
262#ifndef P_PPI1_D0
263#define P_PPI1_D0 P_UNDEF
264#endif
265
266#ifndef P_PPI1_D1
267#define P_PPI1_D1 P_UNDEF
268#endif
269
270#ifndef P_PPI1_D2
271#define P_PPI1_D2 P_UNDEF
272#endif
273
274#ifndef P_PPI1_D3
275#define P_PPI1_D3 P_UNDEF
276#endif
277
278#ifndef P_PPI1_D4
279#define P_PPI1_D4 P_UNDEF
280#endif
281
282#ifndef P_PPI1_D5
283#define P_PPI1_D5 P_UNDEF
284#endif
285
286#ifndef P_PPI1_D6
287#define P_PPI1_D6 P_UNDEF
288#endif
289
290#ifndef P_PPI1_D7
291#define P_PPI1_D7 P_UNDEF
292#endif
293
294#ifndef P_PPI1_D8
295#define P_PPI1_D8 P_UNDEF
296#endif
297
298#ifndef P_PPI1_D9
299#define P_PPI1_D9 P_UNDEF
300#endif
301
302#ifndef P_PPI1_D10
303#define P_PPI1_D10 P_UNDEF
304#endif
305
306#ifndef P_PPI1_D11
307#define P_PPI1_D11 P_UNDEF
308#endif
309
310#ifndef P_PPI1_D12
311#define P_PPI1_D12 P_UNDEF
312#endif
313
314#ifndef P_PPI1_D13
315#define P_PPI1_D13 P_UNDEF
316#endif
317
318#ifndef P_PPI1_D14
319#define P_PPI1_D14 P_UNDEF
320#endif
321
322#ifndef P_PPI1_D15
323#define P_PPI1_D15 P_UNDEF
324#endif
325
326#ifndef P_HOST_D8
327#define P_HOST_D8 P_UNDEF
328#endif
329
330#ifndef P_HOST_D9
331#define P_HOST_D9 P_UNDEF
332#endif
333
334#ifndef P_HOST_D10
335#define P_HOST_D10 P_UNDEF
336#endif
337
338#ifndef P_HOST_D11
339#define P_HOST_D11 P_UNDEF
340#endif
341
342#ifndef P_HOST_D12
343#define P_HOST_D12 P_UNDEF
344#endif
345
346#ifndef P_HOST_D13
347#define P_HOST_D13 P_UNDEF
348#endif
349
350#ifndef P_HOST_D14
351#define P_HOST_D14 P_UNDEF
352#endif
353
354#ifndef P_HOST_D15
355#define P_HOST_D15 P_UNDEF
356#endif
357
358#ifndef P_HOST_D0
359#define P_HOST_D0 P_UNDEF
360#endif
361
362#ifndef P_HOST_D1
363#define P_HOST_D1 P_UNDEF
364#endif
365
366#ifndef P_HOST_D2
367#define P_HOST_D2 P_UNDEF
368#endif
369
370#ifndef P_HOST_D3
371#define P_HOST_D3 P_UNDEF
372#endif
373
374#ifndef P_HOST_D4
375#define P_HOST_D4 P_UNDEF
376#endif
377
378#ifndef P_HOST_D5
379#define P_HOST_D5 P_UNDEF
380#endif
381
382#ifndef P_HOST_D6
383#define P_HOST_D6 P_UNDEF
384#endif
385
386#ifndef P_HOST_D7
387#define P_HOST_D7 P_UNDEF
388#endif
389
390#ifndef P_SPORT1_TFS
391#define P_SPORT1_TFS P_UNDEF
392#endif
393
394#ifndef P_SPORT1_DTSEC
395#define P_SPORT1_DTSEC P_UNDEF
396#endif
397
398#ifndef P_SPORT1_DTPRI
399#define P_SPORT1_DTPRI P_UNDEF
400#endif
401
402#ifndef P_SPORT1_TSCLK
403#define P_SPORT1_TSCLK P_UNDEF
404#endif
405
406#ifndef P_SPORT1_RFS
407#define P_SPORT1_RFS P_UNDEF
408#endif
409
410#ifndef P_SPORT1_DRSEC
411#define P_SPORT1_DRSEC P_UNDEF
412#endif
413
414#ifndef P_SPORT1_DRPRI
415#define P_SPORT1_DRPRI P_UNDEF
416#endif
417
418#ifndef P_SPORT1_RSCLK
419#define P_SPORT1_RSCLK P_UNDEF
420#endif
421
422#ifndef P_PPI2_D0
423#define P_PPI2_D0 P_UNDEF
424#endif
425
426#ifndef P_PPI2_D1
427#define P_PPI2_D1 P_UNDEF
428#endif
429
430#ifndef P_PPI2_D2
431#define P_PPI2_D2 P_UNDEF
432#endif
433
434#ifndef P_PPI2_D3
435#define P_PPI2_D3 P_UNDEF
436#endif
437
438#ifndef P_PPI2_D4
439#define P_PPI2_D4 P_UNDEF
440#endif
441
442#ifndef P_PPI2_D5
443#define P_PPI2_D5 P_UNDEF
444#endif
445
446#ifndef P_PPI2_D6
447#define P_PPI2_D6 P_UNDEF
448#endif
449
450#ifndef P_PPI2_D7
451#define P_PPI2_D7 P_UNDEF
452#endif
453
454#ifndef P_PPI0_D18
455#define P_PPI0_D18 P_UNDEF
456#endif
457
458#ifndef P_PPI0_D19
459#define P_PPI0_D19 P_UNDEF
460#endif
461
462#ifndef P_PPI0_D20
463#define P_PPI0_D20 P_UNDEF
464#endif
465
466#ifndef P_PPI0_D21
467#define P_PPI0_D21 P_UNDEF
468#endif
469
470#ifndef P_PPI0_D22
471#define P_PPI0_D22 P_UNDEF
472#endif
473
474#ifndef P_PPI0_D23
475#define P_PPI0_D23 P_UNDEF
476#endif
477
478#ifndef P_KEY_ROW0
479#define P_KEY_ROW0 P_UNDEF
480#endif
481
482#ifndef P_KEY_ROW1
483#define P_KEY_ROW1 P_UNDEF
484#endif
485
486#ifndef P_KEY_ROW2
487#define P_KEY_ROW2 P_UNDEF
488#endif
489
490#ifndef P_KEY_ROW3
491#define P_KEY_ROW3 P_UNDEF
492#endif
493
494#ifndef P_KEY_COL0
495#define P_KEY_COL0 P_UNDEF
496#endif
497
498#ifndef P_KEY_COL1
499#define P_KEY_COL1 P_UNDEF
500#endif
501
502#ifndef P_KEY_COL2
503#define P_KEY_COL2 P_UNDEF
504#endif
505
506#ifndef P_KEY_COL3
507#define P_KEY_COL3 P_UNDEF
508#endif
509
510#ifndef P_SPI0_SCK
511#define P_SPI0_SCK P_UNDEF
512#endif
513
514#ifndef P_SPI0_MISO
515#define P_SPI0_MISO P_UNDEF
516#endif
517
518#ifndef P_SPI0_MOSI
519#define P_SPI0_MOSI P_UNDEF
520#endif
521
522#ifndef P_SPI0_SS
523#define P_SPI0_SS P_UNDEF
524#endif
525
526#ifndef P_SPI0_SSEL1
527#define P_SPI0_SSEL1 P_UNDEF
528#endif
529
530#ifndef P_SPI0_SSEL2
531#define P_SPI0_SSEL2 P_UNDEF
532#endif
533
534#ifndef P_SPI0_SSEL3
535#define P_SPI0_SSEL3 P_UNDEF
536#endif
537
538#ifndef P_SPI0_SSEL4
539#define P_SPI0_SSEL4 P_UNDEF
540#endif
541
542#ifndef P_SPI0_SSEL5
543#define P_SPI0_SSEL5 P_UNDEF
544#endif
545
546#ifndef P_SPI0_SSEL6
547#define P_SPI0_SSEL6 P_UNDEF
548#endif
549
550#ifndef P_SPI0_SSEL7
551#define P_SPI0_SSEL7 P_UNDEF
552#endif
553
554#ifndef P_UART0_TX
555#define P_UART0_TX P_UNDEF
556#endif
557
558#ifndef P_UART0_RX
559#define P_UART0_RX P_UNDEF
560#endif
561
562#ifndef P_UART1_RTS
563#define P_UART1_RTS P_UNDEF
564#endif
565
566#ifndef P_UART1_CTS
567#define P_UART1_CTS P_UNDEF
568#endif
569
570#ifndef P_PPI1_CLK
571#define P_PPI1_CLK P_UNDEF
572#endif
573
574#ifndef P_PPI1_FS1
575#define P_PPI1_FS1 P_UNDEF
576#endif
577
578#ifndef P_PPI1_FS2
579#define P_PPI1_FS2 P_UNDEF
580#endif
581
582#ifndef P_TWI0_SCL
583#define P_TWI0_SCL P_UNDEF
584#endif
585
586#ifndef P_TWI0_SDA
587#define P_TWI0_SDA P_UNDEF
588#endif
589
590#ifndef P_KEY_COL7
591#define P_KEY_COL7 P_UNDEF
592#endif
593
594#ifndef P_KEY_ROW6
595#define P_KEY_ROW6 P_UNDEF
596#endif
597
598#ifndef P_KEY_COL6
599#define P_KEY_COL6 P_UNDEF
600#endif
601
602#ifndef P_KEY_ROW5
603#define P_KEY_ROW5 P_UNDEF
604#endif
605
606#ifndef P_KEY_COL5
607#define P_KEY_COL5 P_UNDEF
608#endif
609
610#ifndef P_KEY_ROW4
611#define P_KEY_ROW4 P_UNDEF
612#endif
613
614#ifndef P_KEY_COL4
615#define P_KEY_COL4 P_UNDEF
616#endif
617
618#ifndef P_KEY_ROW7
619#define P_KEY_ROW7 P_UNDEF
620#endif
621
622#ifndef P_PPI0_D0
623#define P_PPI0_D0 P_UNDEF
624#endif
625
626#ifndef P_PPI0_D1
627#define P_PPI0_D1 P_UNDEF
628#endif
629
630#ifndef P_PPI0_D2
631#define P_PPI0_D2 P_UNDEF
632#endif
633
634#ifndef P_PPI0_D3
635#define P_PPI0_D3 P_UNDEF
636#endif
637
638#ifndef P_PPI0_D4
639#define P_PPI0_D4 P_UNDEF
640#endif
641
642#ifndef P_PPI0_D5
643#define P_PPI0_D5 P_UNDEF
644#endif
645
646#ifndef P_PPI0_D6
647#define P_PPI0_D6 P_UNDEF
648#endif
649
650#ifndef P_PPI0_D7
651#define P_PPI0_D7 P_UNDEF
652#endif
653
654#ifndef P_PPI0_D8
655#define P_PPI0_D8 P_UNDEF
656#endif
657
658#ifndef P_PPI0_D9
659#define P_PPI0_D9 P_UNDEF
660#endif
661
662#ifndef P_PPI0_D10
663#define P_PPI0_D10 P_UNDEF
664#endif
665
666#ifndef P_PPI0_D11
667#define P_PPI0_D11 P_UNDEF
668#endif
669
670#ifndef P_PPI0_D12
671#define P_PPI0_D12 P_UNDEF
672#endif
673
674#ifndef P_PPI0_D13
675#define P_PPI0_D13 P_UNDEF
676#endif
677
678#ifndef P_PPI0_D14
679#define P_PPI0_D14 P_UNDEF
680#endif
681
682#ifndef P_PPI0_D15
683#define P_PPI0_D15 P_UNDEF
684#endif
685
686#ifndef P_ATAPI_D0A
687#define P_ATAPI_D0A P_UNDEF
688#endif
689
690#ifndef P_ATAPI_D1A
691#define P_ATAPI_D1A P_UNDEF
692#endif
693
694#ifndef P_ATAPI_D2A
695#define P_ATAPI_D2A P_UNDEF
696#endif
697
698#ifndef P_ATAPI_D3A
699#define P_ATAPI_D3A P_UNDEF
700#endif
701
702#ifndef P_ATAPI_D4A
703#define P_ATAPI_D4A P_UNDEF
704#endif
705
706#ifndef P_ATAPI_D5A
707#define P_ATAPI_D5A P_UNDEF
708#endif
709
710#ifndef P_ATAPI_D6A
711#define P_ATAPI_D6A P_UNDEF
712#endif
713
714#ifndef P_ATAPI_D7A
715#define P_ATAPI_D7A P_UNDEF
716#endif
717
718#ifndef P_ATAPI_D8A
719#define P_ATAPI_D8A P_UNDEF
720#endif
721
722#ifndef P_ATAPI_D9A
723#define P_ATAPI_D9A P_UNDEF
724#endif
725
726#ifndef P_ATAPI_D10A
727#define P_ATAPI_D10A P_UNDEF
728#endif
729
730#ifndef P_ATAPI_D11A
731#define P_ATAPI_D11A P_UNDEF
732#endif
733
734#ifndef P_ATAPI_D12A
735#define P_ATAPI_D12A P_UNDEF
736#endif
737
738#ifndef P_ATAPI_D13A
739#define P_ATAPI_D13A P_UNDEF
740#endif
741
742#ifndef P_ATAPI_D14A
743#define P_ATAPI_D14A P_UNDEF
744#endif
745
746#ifndef P_ATAPI_D15A
747#define P_ATAPI_D15A P_UNDEF
748#endif
749
750#ifndef P_PPI0_CLK
751#define P_PPI0_CLK P_UNDEF
752#endif
753
754#ifndef P_PPI0_FS1
755#define P_PPI0_FS1 P_UNDEF
756#endif
757
758#ifndef P_PPI0_FS2
759#define P_PPI0_FS2 P_UNDEF
760#endif
761
762#ifndef P_PPI0_D16
763#define P_PPI0_D16 P_UNDEF
764#endif
765
766#ifndef P_PPI0_D17
767#define P_PPI0_D17 P_UNDEF
768#endif
769
770#ifndef P_SPI1_SSEL1
771#define P_SPI1_SSEL1 P_UNDEF
772#endif
773
774#ifndef P_SPI1_SSEL2
775#define P_SPI1_SSEL2 P_UNDEF
776#endif
777
778#ifndef P_SPI1_SSEL3
779#define P_SPI1_SSEL3 P_UNDEF
780#endif
781
782
783#ifndef P_SPI1_SSEL4
784#define P_SPI1_SSEL4 P_UNDEF
785#endif
786
787#ifndef P_SPI1_SSEL5
788#define P_SPI1_SSEL5 P_UNDEF
789#endif
790
791#ifndef P_SPI1_SSEL6
792#define P_SPI1_SSEL6 P_UNDEF
793#endif
794
795#ifndef P_SPI1_SSEL7
796#define P_SPI1_SSEL7 P_UNDEF
797#endif
798
799#ifndef P_SPI1_SCK
800#define P_SPI1_SCK P_UNDEF
801#endif
802
803#ifndef P_SPI1_MISO
804#define P_SPI1_MISO P_UNDEF
805#endif
806
807#ifndef P_SPI1_MOSI
808#define P_SPI1_MOSI P_UNDEF
809#endif
810
811#ifndef P_SPI1_SS
812#define P_SPI1_SS P_UNDEF
813#endif
814
815#ifndef P_CAN0_TX
816#define P_CAN0_TX P_UNDEF
817#endif
818
819#ifndef P_CAN0_RX
820#define P_CAN0_RX P_UNDEF
821#endif
822
823#ifndef P_CAN1_TX
824#define P_CAN1_TX P_UNDEF
825#endif
826
827#ifndef P_CAN1_RX
828#define P_CAN1_RX P_UNDEF
829#endif
830
831#ifndef P_ATAPI_A0A
832#define P_ATAPI_A0A P_UNDEF
833#endif
834
835#ifndef P_ATAPI_A1A
836#define P_ATAPI_A1A P_UNDEF
837#endif
838
839#ifndef P_ATAPI_A2A
840#define P_ATAPI_A2A P_UNDEF
841#endif
842
843#ifndef P_HOST_CE
844#define P_HOST_CE P_UNDEF
845#endif
846
847#ifndef P_HOST_RD
848#define P_HOST_RD P_UNDEF
849#endif
850
851#ifndef P_HOST_WR
852#define P_HOST_WR P_UNDEF
853#endif
854
855#ifndef P_MTXONB
856#define P_MTXONB P_UNDEF
857#endif
858
859#ifndef P_PPI2_FS2
860#define P_PPI2_FS2 P_UNDEF
861#endif
862
863#ifndef P_PPI2_FS1
864#define P_PPI2_FS1 P_UNDEF
865#endif
866
867#ifndef P_PPI2_CLK
868#define P_PPI2_CLK P_UNDEF
869#endif
870
871#ifndef P_CNT_CZM
872#define P_CNT_CZM P_UNDEF
873#endif
874
875#ifndef P_UART1_TX
876#define P_UART1_TX P_UNDEF
877#endif
878
879#ifndef P_UART1_RX
880#define P_UART1_RX P_UNDEF
881#endif
882
883#ifndef P_ATAPI_RESET
884#define P_ATAPI_RESET P_UNDEF
885#endif
886
887#ifndef P_HOST_ADDR
888#define P_HOST_ADDR P_UNDEF
889#endif
890
891#ifndef P_HOST_ACK
892#define P_HOST_ACK P_UNDEF
893#endif
894
895#ifndef P_MTX
896#define P_MTX P_UNDEF
897#endif
898
899#ifndef P_MRX
900#define P_MRX P_UNDEF
901#endif
902
903#ifndef P_MRXONB
904#define P_MRXONB P_UNDEF
905#endif
906
907#ifndef P_A4
908#define P_A4 P_UNDEF
909#endif
910
911#ifndef P_A5
912#define P_A5 P_UNDEF
913#endif
914
915#ifndef P_A6
916#define P_A6 P_UNDEF
917#endif
918
919#ifndef P_A7
920#define P_A7 P_UNDEF
921#endif
922
923#ifndef P_A8
924#define P_A8 P_UNDEF
925#endif
926
927#ifndef P_A9
928#define P_A9 P_UNDEF
929#endif
930
931#ifndef P_PPI1_FS3
932#define P_PPI1_FS3 P_UNDEF
933#endif
934
935#ifndef P_PPI2_FS3
936#define P_PPI2_FS3 P_UNDEF
937#endif
938
939#ifndef P_TMR8
940#define P_TMR8 P_UNDEF
941#endif
942
943#ifndef P_TMR9
944#define P_TMR9 P_UNDEF
945#endif
946
947#ifndef P_TMR10
948#define P_TMR10 P_UNDEF
949#endif
950#ifndef P_TMR11
951#define P_TMR11 P_UNDEF
952#endif
953
954#ifndef P_DMAR0
955#define P_DMAR0 P_UNDEF
956#endif
957
958#ifndef P_DMAR1
959#define P_DMAR1 P_UNDEF
960#endif
961
962#ifndef P_PPI0_FS3
963#define P_PPI0_FS3 P_UNDEF
964#endif
965
966#ifndef P_CNT_CDG
967#define P_CNT_CDG P_UNDEF
968#endif
969
970#ifndef P_CNT_CUD
971#define P_CNT_CUD P_UNDEF
972#endif
973
974#ifndef P_A10
975#define P_A10 P_UNDEF
976#endif
977
978#ifndef P_A11
979#define P_A11 P_UNDEF
980#endif
981
982#ifndef P_A12
983#define P_A12 P_UNDEF
984#endif
985
986#ifndef P_A13
987#define P_A13 P_UNDEF
988#endif
989
990#ifndef P_A14
991#define P_A14 P_UNDEF
992#endif
993
994#ifndef P_A15
995#define P_A15 P_UNDEF
996#endif
997
998#ifndef P_A16
999#define P_A16 P_UNDEF
1000#endif
1001
1002#ifndef P_A17
1003#define P_A17 P_UNDEF
1004#endif
1005
1006#ifndef P_A18
1007#define P_A18 P_UNDEF
1008#endif
1009
1010#ifndef P_A19
1011#define P_A19 P_UNDEF
1012#endif
1013
1014#ifndef P_A20
1015#define P_A20 P_UNDEF
1016#endif
1017
1018#ifndef P_A21
1019#define P_A21 P_UNDEF
1020#endif
1021
1022#ifndef P_A22
1023#define P_A22 P_UNDEF
1024#endif
1025
1026#ifndef P_A23
1027#define P_A23 P_UNDEF
1028#endif
1029
1030#ifndef P_A24
1031#define P_A24 P_UNDEF
1032#endif
1033
1034#ifndef P_A25
1035#define P_A25 P_UNDEF
1036#endif
1037
1038#ifndef P_NOR_CLK
1039#define P_NOR_CLK P_UNDEF
1040#endif
1041
1042#ifndef P_TMRCLK
1043#define P_TMRCLK P_UNDEF
1044#endif
1045
1046#ifndef P_AMC_ARDY_NOR_WAIT
1047#define P_AMC_ARDY_NOR_WAIT P_UNDEF
1048#endif
1049
1050#ifndef P_NAND_CE
1051#define P_NAND_CE P_UNDEF
1052#endif
1053
1054#ifndef P_NAND_RB
1055#define P_NAND_RB P_UNDEF
1056#endif
1057
1058#ifndef P_ATAPI_DIOR
1059#define P_ATAPI_DIOR P_UNDEF
1060#endif
1061
1062#ifndef P_ATAPI_DIOW
1063#define P_ATAPI_DIOW P_UNDEF
1064#endif
1065
1066#ifndef P_ATAPI_CS0
1067#define P_ATAPI_CS0 P_UNDEF
1068#endif
1069
1070#ifndef P_ATAPI_CS1
1071#define P_ATAPI_CS1 P_UNDEF
1072#endif
1073
1074#ifndef P_ATAPI_DMACK
1075#define P_ATAPI_DMACK P_UNDEF
1076#endif
1077
1078#ifndef P_ATAPI_DMARQ
1079#define P_ATAPI_DMARQ P_UNDEF
1080#endif
1081
1082#ifndef P_ATAPI_INTRQ
1083#define P_ATAPI_INTRQ P_UNDEF
1084#endif
1085
1086#ifndef P_ATAPI_IORDY
1087#define P_ATAPI_IORDY P_UNDEF
1088#endif
1089
1090#ifndef P_AMC_BR
1091#define P_AMC_BR P_UNDEF
1092#endif
1093
1094#ifndef P_AMC_BG
1095#define P_AMC_BG P_UNDEF
1096#endif
1097
1098#ifndef P_AMC_BGH
1099#define P_AMC_BGH P_UNDEF
1100#endif
1101
1102/* EMAC */
1103
1104#ifndef P_MII0_ETxD0
1105#define P_MII0_ETxD0 P_UNDEF
1106#endif
1107
1108#ifndef P_MII0_ETxD1
1109#define P_MII0_ETxD1 P_UNDEF
1110#endif
1111
1112#ifndef P_MII0_ETxD2
1113#define P_MII0_ETxD2 P_UNDEF
1114#endif
1115
1116#ifndef P_MII0_ETxD3
1117#define P_MII0_ETxD3 P_UNDEF
1118#endif
1119
1120#ifndef P_MII0_ETxEN
1121#define P_MII0_ETxEN P_UNDEF
1122#endif
1123
1124#ifndef P_MII0_TxCLK
1125#define P_MII0_TxCLK P_UNDEF
1126#endif
1127
1128#ifndef P_MII0_PHYINT
1129#define P_MII0_PHYINT P_UNDEF
1130#endif
1131
1132#ifndef P_MII0_COL
1133#define P_MII0_COL P_UNDEF
1134#endif
1135
1136#ifndef P_MII0_ERxD0
1137#define P_MII0_ERxD0 P_UNDEF
1138#endif
1139
1140#ifndef P_MII0_ERxD1
1141#define P_MII0_ERxD1 P_UNDEF
1142#endif
1143
1144#ifndef P_MII0_ERxD2
1145#define P_MII0_ERxD2 P_UNDEF
1146#endif
1147
1148#ifndef P_MII0_ERxD3
1149#define P_MII0_ERxD3 P_UNDEF
1150#endif
1151
1152#ifndef P_MII0_ERxDV
1153#define P_MII0_ERxDV P_UNDEF
1154#endif
1155
1156#ifndef P_MII0_ERxCLK
1157#define P_MII0_ERxCLK P_UNDEF
1158#endif
1159
1160#ifndef P_MII0_ERxER
1161#define P_MII0_ERxER P_UNDEF
1162#endif
1163
1164#ifndef P_MII0_CRS
1165#define P_MII0_CRS P_UNDEF
1166#endif
1167
1168#ifndef P_RMII0_REF_CLK
1169#define P_RMII0_REF_CLK P_UNDEF
1170#endif
1171
1172#ifndef P_RMII0_MDINT
1173#define P_RMII0_MDINT P_UNDEF
1174#endif
1175
1176#ifndef P_RMII0_CRS_DV
1177#define P_RMII0_CRS_DV P_UNDEF
1178#endif
1179
1180#ifndef P_MDC
1181#define P_MDC P_UNDEF
1182#endif
1183
1184#ifndef P_MDIO
1185#define P_MDIO P_UNDEF
1186#endif
1187
1188#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
new file mode 100644
index 000000000000..23aa1f8c1bd1
--- /dev/null
+++ b/arch/blackfin/include/asm/posix_types.h
@@ -0,0 +1,61 @@
1#ifndef __ARCH_BFIN_POSIX_TYPES_H
2#define __ARCH_BFIN_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned short __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned int __kernel_ipc_pid_t;
16typedef unsigned int __kernel_uid_t;
17typedef unsigned int __kernel_gid_t;
18typedef unsigned long __kernel_size_t;
19typedef long __kernel_ssize_t;
20typedef int __kernel_ptrdiff_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char *__kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned short __kernel_old_uid_t;
34typedef unsigned short __kernel_old_gid_t;
35typedef unsigned short __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42 int val[2];
43} __kernel_fsid_t;
44
45#if defined(__KERNEL__)
46
47#undef __FD_SET
48#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
49
50#undef __FD_CLR
51#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
52
53#undef __FD_ISSET
54#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
55
56#undef __FD_ZERO
57#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
58
59#endif /* defined(__KERNEL__) */
60
61#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
new file mode 100644
index 000000000000..6f3995b119d8
--- /dev/null
+++ b/arch/blackfin/include/asm/processor.h
@@ -0,0 +1,158 @@
1#ifndef __ASM_BFIN_PROCESSOR_H
2#define __ASM_BFIN_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <asm/blackfin.h>
11#include <asm/segment.h>
12#include <linux/compiler.h>
13
14static inline unsigned long rdusp(void)
15{
16 unsigned long usp;
17
18 __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
19 return usp;
20}
21
22static inline void wrusp(unsigned long usp)
23{
24 __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
25}
26
27/*
28 * User space process size: 1st byte beyond user address space.
29 * Fairly meaningless on nommu. Parts of user programs can be scattered
30 * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
31 */
32#define TASK_SIZE 0xFFFFFFFF
33
34#ifdef __KERNEL__
35#define STACK_TOP TASK_SIZE
36#endif
37
38#define TASK_UNMAPPED_BASE 0
39
40struct thread_struct {
41 unsigned long ksp; /* kernel stack pointer */
42 unsigned long usp; /* user stack pointer */
43 unsigned short seqstat; /* saved status register */
44 unsigned long esp0; /* points to SR of stack frame pt_regs */
45 unsigned long pc; /* instruction pointer */
46 void * debuggerinfo;
47};
48
49#define INIT_THREAD { \
50 sizeof(init_stack) + (unsigned long) init_stack, 0, \
51 PS_S, 0, 0 \
52}
53
54/*
55 * Do necessary setup to start up a newly executed thread.
56 *
57 * pass the data segment into user programs if it exists,
58 * it can't hurt anything as far as I can tell
59 */
60#define start_thread(_regs, _pc, _usp) \
61do { \
62 set_fs(USER_DS); \
63 (_regs)->pc = (_pc); \
64 if (current->mm) \
65 (_regs)->p5 = current->mm->start_data; \
66 task_thread_info(current)->l1_task_info.stack_start \
67 = (void *)current->mm->context.stack_start; \
68 task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \
69 memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \
70 sizeof(*L1_SCRATCH_TASK_INFO)); \
71 wrusp(_usp); \
72} while(0)
73
74/* Forward declaration, a strange C thing */
75struct task_struct;
76
77/* Free all resources held by a thread. */
78static inline void release_thread(struct task_struct *dead_task)
79{
80}
81
82#define prepare_to_copy(tsk) do { } while (0)
83
84extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
85
86/*
87 * Free current thread data structures etc..
88 */
89static inline void exit_thread(void)
90{
91}
92
93/*
94 * Return saved PC of a blocked thread.
95 */
96#define thread_saved_pc(tsk) (tsk->thread.pc)
97
98unsigned long get_wchan(struct task_struct *p);
99
100#define KSTK_EIP(tsk) \
101 ({ \
102 unsigned long eip = 0; \
103 if ((tsk)->thread.esp0 > PAGE_SIZE && \
104 MAP_NR((tsk)->thread.esp0) < max_mapnr) \
105 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
106 eip; })
107#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
108
109#define cpu_relax() barrier()
110
111/* Get the Silicon Revision of the chip */
112static inline uint32_t __pure bfin_revid(void)
113{
114 /* stored in the upper 4 bits */
115 uint32_t revid = bfin_read_CHIPID() >> 28;
116
117#ifdef CONFIG_BF52x
118 /* ANOMALY_05000357
119 * Incorrect Revision Number in DSPID Register
120 */
121 if (revid == 0)
122 switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
123 case 0x0010:
124 revid = 0;
125 break;
126 case 0x2796:
127 revid = 1;
128 break;
129 default:
130 revid = 0xFFFF;
131 break;
132 }
133#endif
134 return revid;
135}
136
137static inline uint32_t __pure bfin_compiled_revid(void)
138{
139#if defined(CONFIG_BF_REV_0_0)
140 return 0;
141#elif defined(CONFIG_BF_REV_0_1)
142 return 1;
143#elif defined(CONFIG_BF_REV_0_2)
144 return 2;
145#elif defined(CONFIG_BF_REV_0_3)
146 return 3;
147#elif defined(CONFIG_BF_REV_0_4)
148 return 4;
149#elif defined(CONFIG_BF_REV_0_5)
150 return 5;
151#elif defined(CONFIG_BF_REV_ANY)
152 return 0xffff;
153#else
154 return -1;
155#endif
156}
157
158#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
new file mode 100644
index 000000000000..a45a80e54adc
--- /dev/null
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -0,0 +1,168 @@
1#ifndef _BFIN_PTRACE_H
2#define _BFIN_PTRACE_H
3
4/*
5 * GCC defines register number like this:
6 * -----------------------------
7 * 0 - 7 are data registers R0-R7
8 * 8 - 15 are address registers P0-P7
9 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
10 * 32 - 33 A registers A0 & A1
11 * 34 - status register
12 * -----------------------------
13 *
14 * We follows above, except:
15 * 32-33 --- Low 32-bit of A0&1
16 * 34-35 --- High 8-bit of A0&1
17 */
18
19#ifndef __ASSEMBLY__
20
21/* this struct defines the way the registers are stored on the
22 stack during a system call. */
23
24struct pt_regs {
25 long orig_pc;
26 long ipend;
27 long seqstat;
28 long rete;
29 long retn;
30 long retx;
31 long pc; /* PC == RETI */
32 long rets;
33 long reserved; /* Used as scratch during system calls */
34 long astat;
35 long lb1;
36 long lb0;
37 long lt1;
38 long lt0;
39 long lc1;
40 long lc0;
41 long a1w;
42 long a1x;
43 long a0w;
44 long a0x;
45 long b3;
46 long b2;
47 long b1;
48 long b0;
49 long l3;
50 long l2;
51 long l1;
52 long l0;
53 long m3;
54 long m2;
55 long m1;
56 long m0;
57 long i3;
58 long i2;
59 long i1;
60 long i0;
61 long usp;
62 long fp;
63 long p5;
64 long p4;
65 long p3;
66 long p2;
67 long p1;
68 long p0;
69 long r7;
70 long r6;
71 long r5;
72 long r4;
73 long r3;
74 long r2;
75 long r1;
76 long r0;
77 long orig_r0;
78 long orig_p0;
79 long syscfg;
80};
81
82/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
83#define PTRACE_GETREGS 12
84#define PTRACE_SETREGS 13 /* ptrace signal */
85
86#define PTRACE_GETFDPIC 31
87#define PTRACE_GETFDPIC_EXEC 0
88#define PTRACE_GETFDPIC_INTERP 1
89
90#define PS_S (0x0002)
91
92#ifdef __KERNEL__
93
94/* user_mode returns true if only one bit is set in IPEND, other than the
95 master interrupt enable. */
96#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
97#define instruction_pointer(regs) ((regs)->pc)
98#define profile_pc(regs) instruction_pointer(regs)
99extern void show_regs(struct pt_regs *);
100
101#endif /* __KERNEL__ */
102
103#endif /* __ASSEMBLY__ */
104
105/*
106 * Offsets used by 'ptrace' system call interface.
107 */
108
109#define PT_R0 204
110#define PT_R1 200
111#define PT_R2 196
112#define PT_R3 192
113#define PT_R4 188
114#define PT_R5 184
115#define PT_R6 180
116#define PT_R7 176
117#define PT_P0 172
118#define PT_P1 168
119#define PT_P2 164
120#define PT_P3 160
121#define PT_P4 156
122#define PT_P5 152
123#define PT_FP 148
124#define PT_USP 144
125#define PT_I0 140
126#define PT_I1 136
127#define PT_I2 132
128#define PT_I3 128
129#define PT_M0 124
130#define PT_M1 120
131#define PT_M2 116
132#define PT_M3 112
133#define PT_L0 108
134#define PT_L1 104
135#define PT_L2 100
136#define PT_L3 96
137#define PT_B0 92
138#define PT_B1 88
139#define PT_B2 84
140#define PT_B3 80
141#define PT_A0X 76
142#define PT_A0W 72
143#define PT_A1X 68
144#define PT_A1W 64
145#define PT_LC0 60
146#define PT_LC1 56
147#define PT_LT0 52
148#define PT_LT1 48
149#define PT_LB0 44
150#define PT_LB1 40
151#define PT_ASTAT 36
152#define PT_RESERVED 32
153#define PT_RETS 28
154#define PT_PC 24
155#define PT_RETX 20
156#define PT_RETN 16
157#define PT_RETE 12
158#define PT_SEQSTAT 8
159#define PT_IPEND 4
160
161#define PT_SYSCFG 216
162#define PT_TEXT_ADDR 220
163#define PT_TEXT_END_ADDR 224
164#define PT_DATA_ADDR 228
165#define PT_FDPIC_EXEC 232
166#define PT_FDPIC_INTERP 236
167
168#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
new file mode 100644
index 000000000000..6d448b5f5985
--- /dev/null
+++ b/arch/blackfin/include/asm/reboot.h
@@ -0,0 +1,20 @@
1/*
2 * include/asm-blackfin/reboot.h - shutdown/reboot header
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_REBOOT_H__
10#define __ASM_REBOOT_H__
11
12/* optional board specific hooks */
13extern void native_machine_restart(char *cmd);
14extern void native_machine_halt(void);
15extern void native_machine_power_off(void);
16
17/* common reboot workarounds */
18extern void bfin_gpio_reset_spi0_ssel1(void);
19
20#endif
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h
new file mode 100644
index 000000000000..091355ab3495
--- /dev/null
+++ b/arch/blackfin/include/asm/resource.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_RESOURCE_H
2#define _BFIN_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif /* _BFIN_RESOURCE_H */
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
new file mode 100644
index 000000000000..04f448711cd0
--- /dev/null
+++ b/arch/blackfin/include/asm/scatterlist.h
@@ -0,0 +1,28 @@
1#ifndef _BLACKFIN_SCATTERLIST_H
2#define _BLACKFIN_SCATTERLIST_H
3
4#include <linux/mm.h>
5
6struct scatterlist {
7#ifdef CONFIG_DEBUG_SG
8 unsigned long sg_magic;
9#endif
10 unsigned long page_link;
11 unsigned int offset;
12 dma_addr_t dma_address;
13 unsigned int length;
14};
15
16/*
17 * These macros should be used after a pci_map_sg call has been done
18 * to get bus addresses of each of the SG entries and their lengths.
19 * You should only work with the number of sg entries pci_map_sg
20 * returns, or alternatively stop on the first sg_dma_len(sg) which
21 * is 0.
22 */
23#define sg_dma_address(sg) ((sg)->dma_address)
24#define sg_dma_len(sg) ((sg)->length)
25
26#define ISA_DMA_THRESHOLD (0xffffffff)
27
28#endif /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
new file mode 100644
index 000000000000..1443c3353a8c
--- /dev/null
+++ b/arch/blackfin/include/asm/sections.h
@@ -0,0 +1,7 @@
1#ifndef _BLACKFIN_SECTIONS_H
2#define _BLACKFIN_SECTIONS_H
3
4/* nothing to see, move along */
5#include <asm-generic/sections.h>
6
7#endif
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
new file mode 100644
index 000000000000..02cfd09b5a99
--- /dev/null
+++ b/arch/blackfin/include/asm/segment.h
@@ -0,0 +1,7 @@
1#ifndef _BFIN_SEGMENT_H
2#define _BFIN_SEGMENT_H
3
4#define KERNEL_DS (0x5)
5#define USER_DS (0x1)
6
7#endif /* _BFIN_SEGMENT_H */
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h
new file mode 100644
index 000000000000..18deb5c7fa5d
--- /dev/null
+++ b/arch/blackfin/include/asm/sembuf.h
@@ -0,0 +1,25 @@
1#ifndef _BFIN_SEMBUF_H
2#define _BFIN_SEMBUF_H
3
4/*
5 * The semid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17 unsigned long __unused1;
18 __kernel_time_t sem_ctime; /* last change time */
19 unsigned long __unused2;
20 unsigned long sem_nsems; /* no. of semaphores in array */
21 unsigned long __unused3;
22 unsigned long __unused4;
23};
24
25#endif /* _BFIN_SEMBUF_H */
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
new file mode 100644
index 000000000000..994dd869558c
--- /dev/null
+++ b/arch/blackfin/include/asm/serial.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-blackfin/serial.h
3 */
4
5#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
new file mode 100644
index 000000000000..01c8c6cbe6fc
--- /dev/null
+++ b/arch/blackfin/include/asm/setup.h
@@ -0,0 +1,17 @@
1/*
2** asm/setup.h -- Definition of the Linux/bfin setup information
3**
4** This file is subject to the terms and conditions of the GNU General Public
5** License. See the file COPYING in the main directory of this archive
6** for more details.
7**
8** Copyright Lineo, Inc 2001 Tony Kou
9**
10*/
11
12#ifndef _BFIN_SETUP_H
13#define _BFIN_SETUP_H
14
15#define COMMAND_LINE_SIZE 512
16
17#endif /* _BFIN_SETUP_H */
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h
new file mode 100644
index 000000000000..612436303e89
--- /dev/null
+++ b/arch/blackfin/include/asm/shmbuf.h
@@ -0,0 +1,42 @@
1#ifndef _BFIN_SHMBUF_H
2#define _BFIN_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18 unsigned long __unused1;
19 __kernel_time_t shm_dtime; /* last detach time */
20 unsigned long __unused2;
21 __kernel_time_t shm_ctime; /* last change time */
22 unsigned long __unused3;
23 __kernel_pid_t shm_cpid; /* pid of creator */
24 __kernel_pid_t shm_lpid; /* pid of last operator */
25 unsigned long shm_nattch; /* no. of current attaches */
26 unsigned long __unused4;
27 unsigned long __unused5;
28};
29
30struct shminfo64 {
31 unsigned long shmmax;
32 unsigned long shmmin;
33 unsigned long shmmni;
34 unsigned long shmseg;
35 unsigned long shmall;
36 unsigned long __unused1;
37 unsigned long __unused2;
38 unsigned long __unused3;
39 unsigned long __unused4;
40};
41
42#endif /* _BFIN_SHMBUF_H */
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h
new file mode 100644
index 000000000000..3c03906b7664
--- /dev/null
+++ b/arch/blackfin/include/asm/shmparam.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_SHMPARAM_H
2#define _BFIN_SHMPARAM_H
3
4#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
5
6#endif /* _BFIN_SHMPARAM_H */
diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h
new file mode 100644
index 000000000000..ce00b03c2775
--- /dev/null
+++ b/arch/blackfin/include/asm/sigcontext.h
@@ -0,0 +1,55 @@
1#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
2#define _ASM_BLACKFIN_SIGCONTEXT_H
3
4/* Add new entries at the end of the structure only. */
5struct sigcontext {
6 unsigned long sc_r0;
7 unsigned long sc_r1;
8 unsigned long sc_r2;
9 unsigned long sc_r3;
10 unsigned long sc_r4;
11 unsigned long sc_r5;
12 unsigned long sc_r6;
13 unsigned long sc_r7;
14 unsigned long sc_p0;
15 unsigned long sc_p1;
16 unsigned long sc_p2;
17 unsigned long sc_p3;
18 unsigned long sc_p4;
19 unsigned long sc_p5;
20 unsigned long sc_usp;
21 unsigned long sc_a0w;
22 unsigned long sc_a1w;
23 unsigned long sc_a0x;
24 unsigned long sc_a1x;
25 unsigned long sc_astat;
26 unsigned long sc_rets;
27 unsigned long sc_pc;
28 unsigned long sc_retx;
29 unsigned long sc_fp;
30 unsigned long sc_i0;
31 unsigned long sc_i1;
32 unsigned long sc_i2;
33 unsigned long sc_i3;
34 unsigned long sc_m0;
35 unsigned long sc_m1;
36 unsigned long sc_m2;
37 unsigned long sc_m3;
38 unsigned long sc_l0;
39 unsigned long sc_l1;
40 unsigned long sc_l2;
41 unsigned long sc_l3;
42 unsigned long sc_b0;
43 unsigned long sc_b1;
44 unsigned long sc_b2;
45 unsigned long sc_b3;
46 unsigned long sc_lc0;
47 unsigned long sc_lc1;
48 unsigned long sc_lt0;
49 unsigned long sc_lt1;
50 unsigned long sc_lb0;
51 unsigned long sc_lb1;
52 unsigned long sc_seqstat;
53};
54
55#endif
diff --git a/arch/blackfin/include/asm/siginfo.h b/arch/blackfin/include/asm/siginfo.h
new file mode 100644
index 000000000000..eca4565cea37
--- /dev/null
+++ b/arch/blackfin/include/asm/siginfo.h
@@ -0,0 +1,35 @@
1#ifndef _BFIN_SIGINFO_H
2#define _BFIN_SIGINFO_H
3
4#include <linux/types.h>
5#include <asm-generic/siginfo.h>
6
7#define UID16_SIGINFO_COMPAT_NEEDED
8
9#define si_uid16 _sifields._kill._uid
10
11#define ILL_ILLPARAOP (__SI_FAULT|2) /* illegal opcode combine ********** */
12#define ILL_ILLEXCPT (__SI_FAULT|4) /* unrecoverable exception ********** */
13#define ILL_CPLB_VI (__SI_FAULT|9) /* D/I CPLB protect violation ******** */
14#define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */
15#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
16
17/*
18 * SIGBUS si_codes
19 */
20#define BUS_OPFETCH (__SI_FAULT|4) /* error from instruction fetch ******** */
21
22/*
23 * SIGTRAP si_codes
24 */
25#define TRAP_STEP (__SI_FAULT|1) /* single-step breakpoint************* */
26#define TRAP_TRACEFLOW (__SI_FAULT|2) /* trace buffer overflow ************* */
27#define TRAP_WATCHPT (__SI_FAULT|3) /* watchpoint match ************* */
28#define TRAP_ILLTRAP (__SI_FAULT|4) /* illegal trap ************* */
29
30/*
31 * SIGSEGV si_codes
32 */
33#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */
34
35#endif
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h
new file mode 100644
index 000000000000..87951d251458
--- /dev/null
+++ b/arch/blackfin/include/asm/signal.h
@@ -0,0 +1,160 @@
1#ifndef _BLACKFIN_SIGNAL_H
2#define _BLACKFIN_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct siginfo;
8
9#ifdef __KERNEL__
10/* Most things should be clean enough to redefine this at will, if care
11 is taken to make libc match. */
12
13#define _NSIG 64
14#define _NSIG_BPW 32
15#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
16
17typedef unsigned long old_sigset_t; /* at least 32 bits */
18
19typedef struct {
20 unsigned long sig[_NSIG_WORDS];
21} sigset_t;
22
23#else
24/* Here we must cater to libcs that poke about in kernel headers. */
25
26#define NSIG 32
27typedef unsigned long sigset_t;
28
29#endif /* __KERNEL__ */
30
31#define SIGHUP 1
32#define SIGINT 2
33#define SIGQUIT 3
34#define SIGILL 4
35#define SIGTRAP 5
36#define SIGABRT 6
37#define SIGIOT 6
38#define SIGBUS 7
39#define SIGFPE 8
40#define SIGKILL 9
41#define SIGUSR1 10
42#define SIGSEGV 11
43#define SIGUSR2 12
44#define SIGPIPE 13
45#define SIGALRM 14
46#define SIGTERM 15
47#define SIGSTKFLT 16
48#define SIGCHLD 17
49#define SIGCONT 18
50#define SIGSTOP 19
51#define SIGTSTP 20
52#define SIGTTIN 21
53#define SIGTTOU 22
54#define SIGURG 23
55#define SIGXCPU 24
56#define SIGXFSZ 25
57#define SIGVTALRM 26
58#define SIGPROF 27
59#define SIGWINCH 28
60#define SIGIO 29
61#define SIGPOLL SIGIO
62/*
63#define SIGLOST 29
64*/
65#define SIGPWR 30
66#define SIGSYS 31
67#define SIGUNUSED 31
68
69/* These should not be considered constants from userland. */
70#define SIGRTMIN 32
71#define SIGRTMAX _NSIG
72
73/*
74 * SA_FLAGS values:
75 *
76 * SA_ONSTACK indicates that a registered stack_t will be used.
77 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
78 * SA_RESTART flag to get restarting signals (which were the default long ago)
79 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
80 * SA_RESETHAND clears the handler when the signal is delivered.
81 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
82 * SA_NODEFER prevents the current signal from being masked in the handler.
83 *
84 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
85 * Unix names RESETHAND and NODEFER respectively.
86 */
87#define SA_NOCLDSTOP 0x00000001
88#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
89#define SA_SIGINFO 0x00000004
90#define SA_ONSTACK 0x08000000
91#define SA_RESTART 0x10000000
92#define SA_NODEFER 0x40000000
93#define SA_RESETHAND 0x80000000
94
95#define SA_NOMASK SA_NODEFER
96#define SA_ONESHOT SA_RESETHAND
97
98/*
99 * sigaltstack controls
100 */
101#define SS_ONSTACK 1
102#define SS_DISABLE 2
103
104#define MINSIGSTKSZ 2048
105#define SIGSTKSZ 8192
106
107#include <asm-generic/signal.h>
108
109#ifdef __KERNEL__
110struct old_sigaction {
111 __sighandler_t sa_handler;
112 old_sigset_t sa_mask;
113 unsigned long sa_flags;
114 void (*sa_restorer) (void);
115};
116
117struct sigaction {
118 __sighandler_t sa_handler;
119 unsigned long sa_flags;
120 void (*sa_restorer) (void);
121 sigset_t sa_mask; /* mask last for extensibility */
122};
123
124struct k_sigaction {
125 struct sigaction sa;
126};
127#else
128/* Here we must cater to libcs that poke about in kernel headers. */
129
130struct sigaction {
131 union {
132 __sighandler_t _sa_handler;
133 void (*_sa_sigaction) (int, struct siginfo *, void *);
134 } _u;
135 sigset_t sa_mask;
136 unsigned long sa_flags;
137 void (*sa_restorer) (void);
138};
139
140#define sa_handler _u._sa_handler
141#define sa_sigaction _u._sa_sigaction
142
143#endif /* __KERNEL__ */
144
145typedef struct sigaltstack {
146 void __user *ss_sp;
147 int ss_flags;
148 size_t ss_size;
149} stack_t;
150
151#ifdef __KERNEL__
152
153#include <asm/sigcontext.h>
154#undef __HAVE_ARCH_SIG_BITOPS
155
156#define ptrace_signal_deliver(regs, cookie) do { } while (0)
157
158#endif /* __KERNEL__ */
159
160#endif /* _BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h
new file mode 100644
index 000000000000..2ca702e44d47
--- /dev/null
+++ b/arch/blackfin/include/asm/socket.h
@@ -0,0 +1,56 @@
1#ifndef _ASM_SOCKET_H
2#define _ASM_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockoptions(2) */
7#define SOL_SOCKET 1
8
9#define SO_DEBUG 1
10#define SO_REUSEADDR 2
11#define SO_TYPE 3
12#define SO_ERROR 4
13#define SO_DONTROUTE 5
14#define SO_BROADCAST 6
15#define SO_SNDBUF 7
16#define SO_RCVBUF 8
17#define SO_SNDBUFFORCE 32
18#define SO_RCVBUFFORCE 33
19#define SO_KEEPALIVE 9
20#define SO_OOBINLINE 10
21#define SO_NO_CHECK 11
22#define SO_PRIORITY 12
23#define SO_LINGER 13
24#define SO_BSDCOMPAT 14
25/* To add :#define SO_REUSEPORT 15 */
26#define SO_PASSCRED 16
27#define SO_PEERCRED 17
28#define SO_RCVLOWAT 18
29#define SO_SNDLOWAT 19
30#define SO_RCVTIMEO 20
31#define SO_SNDTIMEO 21
32
33/* Security levels - as per NRL IPv6 - don't actually do anything */
34#define SO_SECURITY_AUTHENTICATION 22
35#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
36#define SO_SECURITY_ENCRYPTION_NETWORK 24
37
38#define SO_BINDTODEVICE 25
39
40/* Socket filtering */
41#define SO_ATTACH_FILTER 26
42#define SO_DETACH_FILTER 27
43
44#define SO_PEERNAME 28
45#define SO_TIMESTAMP 29
46#define SCM_TIMESTAMP SO_TIMESTAMP
47
48#define SO_ACCEPTCONN 30
49#define SO_PEERSEC 31
50#define SO_PASSSEC 34
51#define SO_TIMESTAMPNS 35
52#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
53
54#define SO_MARK 36
55
56#endif /* _ASM_SOCKET_H */
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h
new file mode 100644
index 000000000000..426b89bfaa8b
--- /dev/null
+++ b/arch/blackfin/include/asm/sockios.h
@@ -0,0 +1,13 @@
1#ifndef __ARCH_BFIN_SOCKIOS__
2#define __ARCH_BFIN_SOCKIOS__
3
4/* Socket-level I/O control calls. */
5#define FIOSETOWN 0x8901
6#define SIOCSPGRP 0x8902
7#define FIOGETOWN 0x8903
8#define SIOCGPGRP 0x8904
9#define SIOCATMARK 0x8905
10#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
11#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
12
13#endif /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
new file mode 100644
index 000000000000..64e908a50646
--- /dev/null
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -0,0 +1,6 @@
1#ifndef __BFIN_SPINLOCK_H
2#define __BFIN_SPINLOCK_H
3
4#error blackfin architecture does not support SMP spin lock yet
5
6#endif
diff --git a/arch/blackfin/include/asm/stat.h b/arch/blackfin/include/asm/stat.h
new file mode 100644
index 000000000000..d2b6f11ec231
--- /dev/null
+++ b/arch/blackfin/include/asm/stat.h
@@ -0,0 +1,63 @@
1#ifndef _BFIN_STAT_H
2#define _BFIN_STAT_H
3
4struct stat {
5 unsigned short st_dev;
6 unsigned short __pad1;
7 unsigned long st_ino;
8 unsigned short st_mode;
9 unsigned short st_nlink;
10 unsigned short st_uid;
11 unsigned short st_gid;
12 unsigned short st_rdev;
13 unsigned short __pad2;
14 unsigned long st_size;
15 unsigned long st_blksize;
16 unsigned long st_blocks;
17 unsigned long st_atime;
18 unsigned long __unused1;
19 unsigned long st_mtime;
20 unsigned long __unused2;
21 unsigned long st_ctime;
22 unsigned long __unused3;
23 unsigned long __unused4;
24 unsigned long __unused5;
25};
26
27/* This matches struct stat64 in glibc2.1, hence the absolutely
28 * insane amounts of padding around dev_t's.
29 */
30struct stat64 {
31 unsigned long long st_dev;
32 unsigned char __pad1[4];
33
34#define STAT64_HAS_BROKEN_ST_INO 1
35 unsigned long __st_ino;
36
37 unsigned int st_mode;
38 unsigned int st_nlink;
39
40 unsigned long st_uid;
41 unsigned long st_gid;
42
43 unsigned long long st_rdev;
44 unsigned char __pad2[4];
45
46 long long st_size;
47 unsigned long st_blksize;
48
49 long long st_blocks; /* Number 512-byte blocks allocated. */
50
51 unsigned long st_atime;
52 unsigned long st_atime_nsec;
53
54 unsigned long st_mtime;
55 unsigned long st_mtime_nsec;
56
57 unsigned long st_ctime;
58 unsigned long st_ctime_nsec;
59
60 unsigned long long st_ino;
61};
62
63#endif /* _BFIN_STAT_H */
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h
new file mode 100644
index 000000000000..350672091ba3
--- /dev/null
+++ b/arch/blackfin/include/asm/statfs.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_STATFS_H
2#define _BFIN_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif /* _BFIN_STATFS_H */
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
new file mode 100644
index 000000000000..321f4d96e4ae
--- /dev/null
+++ b/arch/blackfin/include/asm/string.h
@@ -0,0 +1,137 @@
1#ifndef _BLACKFIN_STRING_H_
2#define _BLACKFIN_STRING_H_
3
4#include <linux/types.h>
5
6#ifdef __KERNEL__ /* only set these up for kernel code */
7
8#define __HAVE_ARCH_STRCPY
9extern inline char *strcpy(char *dest, const char *src)
10{
11 char *xdest = dest;
12 char temp = 0;
13
14 __asm__ __volatile__ (
15 "1:"
16 "%2 = B [%1++] (Z);"
17 "B [%0++] = %2;"
18 "CC = %2;"
19 "if cc jump 1b (bp);"
20 : "+&a" (dest), "+&a" (src), "=&d" (temp)
21 :
22 : "memory", "CC");
23
24 return xdest;
25}
26
27#define __HAVE_ARCH_STRNCPY
28extern inline char *strncpy(char *dest, const char *src, size_t n)
29{
30 char *xdest = dest;
31 char temp = 0;
32
33 if (n == 0)
34 return xdest;
35
36 __asm__ __volatile__ (
37 "1:"
38 "%3 = B [%1++] (Z);"
39 "B [%0++] = %3;"
40 "CC = %3;"
41 "if ! cc jump 2f;"
42 "%2 += -1;"
43 "CC = %2 == 0;"
44 "if ! cc jump 1b (bp);"
45 "jump 4f;"
46 "2:"
47 /* if src is shorter than n, we need to null pad bytes now */
48 "%3 = 0;"
49 "3:"
50 "%2 += -1;"
51 "CC = %2 == 0;"
52 "if cc jump 4f;"
53 "B [%0++] = %3;"
54 "jump 3b;"
55 "4:"
56 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
57 :
58 : "memory", "CC");
59
60 return xdest;
61}
62
63#define __HAVE_ARCH_STRCMP
64extern inline int strcmp(const char *cs, const char *ct)
65{
66 /* need to use int's here so the char's in the assembly don't get
67 * sign extended incorrectly when we don't want them to be
68 */
69 int __res1, __res2;
70
71 __asm__ __volatile__ (
72 "1:"
73 "%2 = B[%0++] (Z);" /* get *cs */
74 "%3 = B[%1++] (Z);" /* get *ct */
75 "CC = %2 == %3;" /* compare a byte */
76 "if ! cc jump 2f;" /* not equal, break out */
77 "CC = %2;" /* at end of cs? */
78 "if cc jump 1b (bp);" /* no, keep going */
79 "jump.s 3f;" /* strings are equal */
80 "2:"
81 "%2 = %2 - %3;" /* *cs - *ct */
82 "3:"
83 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
84 :
85 : "memory", "CC");
86
87 return __res1;
88}
89
90#define __HAVE_ARCH_STRNCMP
91extern inline int strncmp(const char *cs, const char *ct, size_t count)
92{
93 /* need to use int's here so the char's in the assembly don't get
94 * sign extended incorrectly when we don't want them to be
95 */
96 int __res1, __res2;
97
98 if (!count)
99 return 0;
100
101 __asm__ __volatile__ (
102 "1:"
103 "%3 = B[%0++] (Z);" /* get *cs */
104 "%4 = B[%1++] (Z);" /* get *ct */
105 "CC = %3 == %4;" /* compare a byte */
106 "if ! cc jump 3f;" /* not equal, break out */
107 "CC = %3;" /* at end of cs? */
108 "if ! cc jump 4f;" /* yes, all done */
109 "%2 += -1;" /* no, adjust count */
110 "CC = %2 == 0;"
111 "if ! cc jump 1b;" /* more to do, keep going */
112 "2:"
113 "%3 = 0;" /* strings are equal */
114 "jump.s 4f;"
115 "3:"
116 "%3 = %3 - %4;" /* *cs - *ct */
117 "4:"
118 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
119 :
120 : "memory", "CC");
121
122 return __res1;
123}
124
125#define __HAVE_ARCH_MEMSET
126extern void *memset(void *s, int c, size_t count);
127#define __HAVE_ARCH_MEMCPY
128extern void *memcpy(void *d, const void *s, size_t count);
129#define __HAVE_ARCH_MEMCMP
130extern int memcmp(const void *, const void *, __kernel_size_t);
131#define __HAVE_ARCH_MEMCHR
132extern void *memchr(const void *s, int c, size_t n);
133#define __HAVE_ARCH_MEMMOVE
134extern void *memmove(void *dest, const void *src, size_t count);
135
136#endif /*__KERNEL__*/
137#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
new file mode 100644
index 000000000000..8f1627d8bf09
--- /dev/null
+++ b/arch/blackfin/include/asm/system.h
@@ -0,0 +1,221 @@
1/*
2 * File: include/asm/system.h
3 * Based on:
4 * Author: Tony Kou (tonyko@lineo.ca)
5 * Copyright (c) 2002 Arcturus Networks Inc.
6 * (www.arcturusnetworks.com)
7 * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
8 * Copyright (c) 2004 Analog Device Inc.
9 * Created: 25Jan2001 - Tony Kou
10 * Description: system.h include file
11 *
12 * Modified: 22Sep2006 - Robin Getz
13 * - move include blackfin.h down, so I can get access to
14 * irq functions in other include files.
15 *
16 * Bugs: Enter bugs at http://blackfin.uclinux.org/
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2, or (at your option)
21 * any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; see the file COPYING.
30 * If not, write to the Free Software Foundation,
31 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33
34#ifndef _BLACKFIN_SYSTEM_H
35#define _BLACKFIN_SYSTEM_H
36
37#include <linux/linkage.h>
38#include <linux/compiler.h>
39#include <mach/anomaly.h>
40
41/*
42 * Interrupt configuring macros.
43 */
44
45extern unsigned long irq_flags;
46
47#define local_irq_enable() \
48 __asm__ __volatile__( \
49 "sti %0;" \
50 : \
51 : "d" (irq_flags) \
52 )
53
54#define local_irq_disable() \
55 do { \
56 int __tmp_dummy; \
57 __asm__ __volatile__( \
58 "cli %0;" \
59 : "=d" (__tmp_dummy) \
60 ); \
61 } while (0)
62
63#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
64# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
65#else
66# define NOP_PAD_ANOMALY_05000244
67#endif
68
69#define idle_with_irq_disabled() \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000244 \
72 ".align 8;" \
73 "sti %0;" \
74 "idle;" \
75 : \
76 : "d" (irq_flags) \
77 )
78
79#ifdef CONFIG_DEBUG_HWERR
80# define __save_and_cli(x) \
81 __asm__ __volatile__( \
82 "cli %0;" \
83 "sti %1;" \
84 : "=&d" (x) \
85 : "d" (0x3F) \
86 )
87#else
88# define __save_and_cli(x) \
89 __asm__ __volatile__( \
90 "cli %0;" \
91 : "=&d" (x) \
92 )
93#endif
94
95#define local_save_flags(x) \
96 __asm__ __volatile__( \
97 "cli %0;" \
98 "sti %0;" \
99 : "=d" (x) \
100 )
101
102#ifdef CONFIG_DEBUG_HWERR
103#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
104#else
105#define irqs_enabled_from_flags(x) ((x) != 0x1f)
106#endif
107
108#define local_irq_restore(x) \
109 do { \
110 if (irqs_enabled_from_flags(x)) \
111 local_irq_enable(); \
112 } while (0)
113
114/* For spinlocks etc */
115#define local_irq_save(x) __save_and_cli(x)
116
117#define irqs_disabled() \
118({ \
119 unsigned long flags; \
120 local_save_flags(flags); \
121 !irqs_enabled_from_flags(flags); \
122})
123
124/*
125 * Force strict CPU ordering.
126 */
127#define nop() asm volatile ("nop;\n\t"::)
128#define mb() asm volatile ("" : : :"memory")
129#define rmb() asm volatile ("" : : :"memory")
130#define wmb() asm volatile ("" : : :"memory")
131#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
132
133#define read_barrier_depends() do { } while(0)
134
135#ifdef CONFIG_SMP
136#define smp_mb() mb()
137#define smp_rmb() rmb()
138#define smp_wmb() wmb()
139#define smp_read_barrier_depends() read_barrier_depends()
140#else
141#define smp_mb() barrier()
142#define smp_rmb() barrier()
143#define smp_wmb() barrier()
144#define smp_read_barrier_depends() do { } while(0)
145#endif
146
147#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
148
149struct __xchg_dummy {
150 unsigned long a[100];
151};
152#define __xg(x) ((volatile struct __xchg_dummy *)(x))
153
154static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
155 int size)
156{
157 unsigned long tmp = 0;
158 unsigned long flags = 0;
159
160 local_irq_save(flags);
161
162 switch (size) {
163 case 1:
164 __asm__ __volatile__
165 ("%0 = b%2 (z);\n\t"
166 "b%2 = %1;\n\t"
167 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
168 break;
169 case 2:
170 __asm__ __volatile__
171 ("%0 = w%2 (z);\n\t"
172 "w%2 = %1;\n\t"
173 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
174 break;
175 case 4:
176 __asm__ __volatile__
177 ("%0 = %2;\n\t"
178 "%2 = %1;\n\t"
179 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
180 break;
181 }
182 local_irq_restore(flags);
183 return tmp;
184}
185
186#include <asm-generic/cmpxchg-local.h>
187
188/*
189 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
190 * them available.
191 */
192#define cmpxchg_local(ptr, o, n) \
193 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
194 (unsigned long)(n), sizeof(*(ptr))))
195#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
196
197#ifndef CONFIG_SMP
198#include <asm-generic/cmpxchg.h>
199#endif
200
201#define prepare_to_switch() do { } while(0)
202
203/*
204 * switch_to(n) should switch tasks to task ptr, first checking that
205 * ptr isn't the current task, in which case it does nothing.
206 */
207
208#include <asm/blackfin.h>
209
210asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
211
212#define switch_to(prev,next,last) \
213do { \
214 memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
215 sizeof *L1_SCRATCH_TASK_INFO); \
216 memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
217 sizeof *L1_SCRATCH_TASK_INFO); \
218 (last) = resume (prev, next); \
219} while (0)
220
221#endif /* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h
new file mode 100644
index 000000000000..f37feb7cf895
--- /dev/null
+++ b/arch/blackfin/include/asm/termbits.h
@@ -0,0 +1,198 @@
1#ifndef __ARCH_BFIN_TERMBITS_H__
2#define __ARCH_BFIN_TERMBITS_H__
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8typedef unsigned int tcflag_t;
9
10#define NCCS 19
11struct termios {
12 tcflag_t c_iflag; /* input mode flags */
13 tcflag_t c_oflag; /* output mode flags */
14 tcflag_t c_cflag; /* control mode flags */
15 tcflag_t c_lflag; /* local mode flags */
16 cc_t c_line; /* line discipline */
17 cc_t c_cc[NCCS]; /* control characters */
18};
19
20struct termios2 {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27 speed_t c_ispeed; /* input speed */
28 speed_t c_ospeed; /* output speed */
29};
30
31struct ktermios {
32 tcflag_t c_iflag; /* input mode flags */
33 tcflag_t c_oflag; /* output mode flags */
34 tcflag_t c_cflag; /* control mode flags */
35 tcflag_t c_lflag; /* local mode flags */
36 cc_t c_line; /* line discipline */
37 cc_t c_cc[NCCS]; /* control characters */
38 speed_t c_ispeed; /* input speed */
39 speed_t c_ospeed; /* output speed */
40};
41
42/* c_cc characters */
43#define VINTR 0
44#define VQUIT 1
45#define VERASE 2
46#define VKILL 3
47#define VEOF 4
48#define VTIME 5
49#define VMIN 6
50#define VSWTC 7
51#define VSTART 8
52#define VSTOP 9
53#define VSUSP 10
54#define VEOL 11
55#define VREPRINT 12
56#define VDISCARD 13
57#define VWERASE 14
58#define VLNEXT 15
59#define VEOL2 16
60
61/* c_iflag bits */
62#define IGNBRK 0000001
63#define BRKINT 0000002
64#define IGNPAR 0000004
65#define PARMRK 0000010
66#define INPCK 0000020
67#define ISTRIP 0000040
68#define INLCR 0000100
69#define IGNCR 0000200
70#define ICRNL 0000400
71#define IUCLC 0001000
72#define IXON 0002000
73#define IXANY 0004000
74#define IXOFF 0010000
75#define IMAXBEL 0020000
76#define IUTF8 0040000
77
78/* c_oflag bits */
79#define OPOST 0000001
80#define OLCUC 0000002
81#define ONLCR 0000004
82#define OCRNL 0000010
83#define ONOCR 0000020
84#define ONLRET 0000040
85#define OFILL 0000100
86#define OFDEL 0000200
87#define NLDLY 0000400
88#define NL0 0000000
89#define NL1 0000400
90#define CRDLY 0003000
91#define CR0 0000000
92#define CR1 0001000
93#define CR2 0002000
94#define CR3 0003000
95#define TABDLY 0014000
96#define TAB0 0000000
97#define TAB1 0004000
98#define TAB2 0010000
99#define TAB3 0014000
100#define XTABS 0014000
101#define BSDLY 0020000
102#define BS0 0000000
103#define BS1 0020000
104#define VTDLY 0040000
105#define VT0 0000000
106#define VT1 0040000
107#define FFDLY 0100000
108#define FF0 0000000
109#define FF1 0100000
110
111/* c_cflag bit meaning */
112#define CBAUD 0010017
113#define B0 0000000 /* hang up */
114#define B50 0000001
115#define B75 0000002
116#define B110 0000003
117#define B134 0000004
118#define B150 0000005
119#define B200 0000006
120#define B300 0000007
121#define B600 0000010
122#define B1200 0000011
123#define B1800 0000012
124#define B2400 0000013
125#define B4800 0000014
126#define B9600 0000015
127#define B19200 0000016
128#define B38400 0000017
129#define EXTA B19200
130#define EXTB B38400
131#define CSIZE 0000060
132#define CS5 0000000
133#define CS6 0000020
134#define CS7 0000040
135#define CS8 0000060
136#define CSTOPB 0000100
137#define CREAD 0000200
138#define PARENB 0000400
139#define PARODD 0001000
140#define HUPCL 0002000
141#define CLOCAL 0004000
142#define CBAUDEX 0010000
143#define BOTHER 0010000
144#define B57600 0010001
145#define B115200 0010002
146#define B230400 0010003
147#define B460800 0010004
148#define B500000 0010005
149#define B576000 0010006
150#define B921600 0010007
151#define B1000000 0010010
152#define B1152000 0010011
153#define B1500000 0010012
154#define B2000000 0010013
155#define B2500000 0010014
156#define B3000000 0010015
157#define B3500000 0010016
158#define B4000000 0010017
159#define CIBAUD 002003600000 /* input baud rate */
160#define CMSPAR 010000000000 /* mark or space (stick) parity */
161#define CRTSCTS 020000000000 /* flow control */
162
163#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
164
165/* c_lflag bits */
166#define ISIG 0000001
167#define ICANON 0000002
168#define XCASE 0000004
169#define ECHO 0000010
170#define ECHOE 0000020
171#define ECHOK 0000040
172#define ECHONL 0000100
173#define NOFLSH 0000200
174#define TOSTOP 0000400
175#define ECHOCTL 0001000
176#define ECHOPRT 0002000
177#define ECHOKE 0004000
178#define FLUSHO 0010000
179#define PENDIN 0040000
180#define IEXTEN 0100000
181
182/* tcflow() and TCXONC use these */
183#define TCOOFF 0
184#define TCOON 1
185#define TCIOFF 2
186#define TCION 3
187
188/* tcflush() and TCFLSH use these */
189#define TCIFLUSH 0
190#define TCOFLUSH 1
191#define TCIOFLUSH 2
192
193/* tcsetattr uses these */
194#define TCSANOW 0
195#define TCSADRAIN 1
196#define TCSAFLUSH 2
197
198#endif /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h
new file mode 100644
index 000000000000..d50d063c605a
--- /dev/null
+++ b/arch/blackfin/include/asm/termios.h
@@ -0,0 +1,94 @@
1#ifndef __BFIN_TERMIOS_H__
2#define __BFIN_TERMIOS_H__
3
4#include <asm/termbits.h>
5#include <asm/ioctls.h>
6
7struct winsize {
8 unsigned short ws_row;
9 unsigned short ws_col;
10 unsigned short ws_xpixel;
11 unsigned short ws_ypixel;
12};
13
14#define NCC 8
15struct termio {
16 unsigned short c_iflag; /* input mode flags */
17 unsigned short c_oflag; /* output mode flags */
18 unsigned short c_cflag; /* control mode flags */
19 unsigned short c_lflag; /* local mode flags */
20 unsigned char c_line; /* line discipline */
21 unsigned char c_cc[NCC]; /* control characters */
22};
23
24/* modem lines */
25#define TIOCM_LE 0x001
26#define TIOCM_DTR 0x002
27#define TIOCM_RTS 0x004
28#define TIOCM_ST 0x008
29#define TIOCM_SR 0x010
30#define TIOCM_CTS 0x020
31#define TIOCM_CAR 0x040
32#define TIOCM_RNG 0x080
33#define TIOCM_DSR 0x100
34#define TIOCM_CD TIOCM_CAR
35#define TIOCM_RI TIOCM_RNG
36#define TIOCM_OUT1 0x2000
37#define TIOCM_OUT2 0x4000
38#define TIOCM_LOOP 0x8000
39
40/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
41
42#ifdef __KERNEL__
43
44/* intr=^C quit=^\ erase=del kill=^U
45 eof=^D vtime=\0 vmin=\1 sxtc=\0
46 start=^Q stop=^S susp=^Z eol=\0
47 reprint=^R discard=^U werase=^W lnext=^V
48 eol2=\0
49*/
50#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
51
52/*
53 * Translate a "termio" structure into a "termios". Ugh.
54 */
55#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
56 unsigned short __tmp; \
57 get_user(__tmp,&(termio)->x); \
58 *(unsigned short *) &(termios)->x = __tmp; \
59}
60
61#define user_termio_to_kernel_termios(termios, termio) \
62({ \
63 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
64 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
65 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
66 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
67 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
68})
69
70/*
71 * Translate a "termios" structure into a "termio". Ugh.
72 */
73#define kernel_termios_to_user_termio(termio, termios) \
74({ \
75 put_user((termios)->c_iflag, &(termio)->c_iflag); \
76 put_user((termios)->c_oflag, &(termio)->c_oflag); \
77 put_user((termios)->c_cflag, &(termio)->c_cflag); \
78 put_user((termios)->c_lflag, &(termio)->c_lflag); \
79 put_user((termios)->c_line, &(termio)->c_line); \
80 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
81})
82
83#define user_termios_to_kernel_termios(k, u) \
84 copy_from_user(k, u, sizeof(struct termios2))
85#define kernel_termios_to_user_termios(u, k) \
86 copy_to_user(u, k, sizeof(struct termios2))
87#define user_termios_to_kernel_termios_1(k, u) \
88 copy_from_user(k, u, sizeof(struct termios))
89#define kernel_termios_to_user_termios_1(u, k) \
90 copy_to_user(u, k, sizeof(struct termios))
91
92#endif /* __KERNEL__ */
93
94#endif /* __BFIN_TERMIOS_H__ */
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
new file mode 100644
index 000000000000..642769329d12
--- /dev/null
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -0,0 +1,135 @@
1/*
2 * File: include/asm-blackfin/thread_info.h
3 * Based on: include/asm-m68knommu/thread_info.h
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level thread information
8 * Modified:
9 * Bugs: Enter bugs at http://blackfin.uclinux.org/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING.
23 * If not, write to the Free Software Foundation,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 */
26
27#ifndef _ASM_THREAD_INFO_H
28#define _ASM_THREAD_INFO_H
29
30#include <asm/page.h>
31#include <asm/entry.h>
32#include <asm/l1layout.h>
33#include <linux/compiler.h>
34
35#ifdef __KERNEL__
36
37/* Thread Align Mask to reach to the top of the stack
38 * for any process
39 */
40#define ALIGN_PAGE_MASK 0xffffe000
41
42/*
43 * Size of kernel stack for each process. This must be a power of 2...
44 */
45#define THREAD_SIZE_ORDER 1
46#define THREAD_SIZE 8192 /* 2 pages */
47
48#ifndef __ASSEMBLY__
49
50typedef unsigned long mm_segment_t;
51
52/*
53 * low level task data.
54 * If you change this, change the TI_* offsets below to match.
55 */
56
57struct thread_info {
58 struct task_struct *task; /* main task structure */
59 struct exec_domain *exec_domain; /* execution domain */
60 unsigned long flags; /* low level flags */
61 int cpu; /* cpu we're on */
62 int preempt_count; /* 0 => preemptable, <0 => BUG */
63 mm_segment_t addr_limit; /* address limit */
64 struct restart_block restart_block;
65 struct l1_scratch_task_info l1_task_info;
66};
67
68/*
69 * macros/functions for gaining access to the thread information structure
70 */
71#define INIT_THREAD_INFO(tsk) \
72{ \
73 .task = &tsk, \
74 .exec_domain = &default_exec_domain, \
75 .flags = 0, \
76 .cpu = 0, \
77 .preempt_count = 1, \
78 .restart_block = { \
79 .fn = do_no_restart_syscall, \
80 }, \
81}
82#define init_thread_info (init_thread_union.thread_info)
83#define init_stack (init_thread_union.stack)
84
85/* Given a task stack pointer, you can find its corresponding
86 * thread_info structure just by masking it to the THREAD_SIZE
87 * boundary (currently 8K as you can see above).
88 */
89__attribute_const__
90static inline struct thread_info *current_thread_info(void)
91{
92 struct thread_info *ti;
93 __asm__("%0 = sp;": "=&d"(ti):
94 );
95 return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
96}
97
98#endif /* __ASSEMBLY__ */
99
100/*
101 * Offsets in thread_info structure, used in assembly code
102 */
103#define TI_TASK 0
104#define TI_EXECDOMAIN 4
105#define TI_FLAGS 8
106#define TI_CPU 12
107#define TI_PREEMPT 16
108
109#define PREEMPT_ACTIVE 0x4000000
110
111/*
112 * thread information flag bit numbers
113 */
114#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
115#define TIF_SIGPENDING 1 /* signal pending */
116#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
117#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
118 TIF_NEED_RESCHED */
119#define TIF_MEMDIE 4
120#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
121#define TIF_FREEZE 6 /* is freezing for suspend */
122
123/* as above, but as bit values */
124#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
125#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
126#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
127#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
128#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
129#define _TIF_FREEZE (1<<TIF_FREEZE)
130
131#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
132
133#endif /* __KERNEL__ */
134
135#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
new file mode 100644
index 000000000000..ddc43ce38533
--- /dev/null
+++ b/arch/blackfin/include/asm/time.h
@@ -0,0 +1,40 @@
1/*
2 * asm-blackfin/time.h:
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIME_H
10#define _ASM_BLACKFIN_TIME_H
11
12/*
13 * The way that the Blackfin core timer works is:
14 * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
15 * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
16 *
17 * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
18 * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
19 * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
20 * to use TSCALE, and program it to zero (which is pass CCLK through).
21 * If you feel like using it, try to keep HZ * TIMESCALE to some
22 * value that divides easy (like power of 2).
23 */
24
25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1
27#define __bfin_cycles_off (0)
28#define __bfin_cycles_mod (0)
29#else
30/*
31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
32 * Whenever we change the Core Clock frequency changes we immediately
33 * adjust the Core Timer Presale Register. This way we don't lose time.
34 */
35#define TIME_SCALE 4
36extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod;
38#endif
39
40#endif
diff --git a/arch/blackfin/include/asm/timex.h b/arch/blackfin/include/asm/timex.h
new file mode 100644
index 000000000000..22b0806161bb
--- /dev/null
+++ b/arch/blackfin/include/asm/timex.h
@@ -0,0 +1,23 @@
1/*
2 * asm-blackfin/timex.h: cpu cycles!
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIMEX_H
10#define _ASM_BLACKFIN_TIMEX_H
11
12#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
13
14typedef unsigned long long cycles_t;
15
16static inline cycles_t get_cycles(void)
17{
18 unsigned long tmp, tmp2;
19 __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
20 return tmp | ((cycles_t)tmp2 << 32);
21}
22
23#endif
diff --git a/arch/blackfin/include/asm/tlb.h b/arch/blackfin/include/asm/tlb.h
new file mode 100644
index 000000000000..89a12ee916d8
--- /dev/null
+++ b/arch/blackfin/include/asm/tlb.h
@@ -0,0 +1,16 @@
1#ifndef _BLACKFIN_TLB_H
2#define _BLACKFIN_TLB_H
3
4#define tlb_start_vma(tlb, vma) do { } while (0)
5#define tlb_end_vma(tlb, vma) do { } while (0)
6#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
7
8/*
9 * .. because we flush the whole mm when it
10 * fills up.
11 */
12#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
13
14#include <asm-generic/tlb.h>
15
16#endif /* _BLACKFIN_TLB_H */
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
new file mode 100644
index 000000000000..277b400924b8
--- /dev/null
+++ b/arch/blackfin/include/asm/tlbflush.h
@@ -0,0 +1,56 @@
1#ifndef _BLACKFIN_TLBFLUSH_H
2#define _BLACKFIN_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
6 * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
7 */
8
9#include <asm/setup.h>
10
11/*
12 * flush all user-space atc entries.
13 */
14static inline void __flush_tlb(void)
15{
16 BUG();
17}
18
19static inline void __flush_tlb_one(unsigned long addr)
20{
21 BUG();
22}
23
24#define flush_tlb() __flush_tlb()
25
26/*
27 * flush all atc entries (both kernel and user-space entries).
28 */
29static inline void flush_tlb_all(void)
30{
31 BUG();
32}
33
34static inline void flush_tlb_mm(struct mm_struct *mm)
35{
36 BUG();
37}
38
39static inline void flush_tlb_page(struct vm_area_struct *vma,
40 unsigned long addr)
41{
42 BUG();
43}
44
45static inline void flush_tlb_range(struct mm_struct *mm,
46 unsigned long start, unsigned long end)
47{
48 BUG();
49}
50
51static inline void flush_tlb_kernel_page(unsigned long addr)
52{
53 BUG();
54}
55
56#endif
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h
new file mode 100644
index 000000000000..acee23987897
--- /dev/null
+++ b/arch/blackfin/include/asm/topology.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_TOPOLOGY_H
2#define _ASM_BLACKFIN_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
new file mode 100644
index 000000000000..312b596b9731
--- /dev/null
+++ b/arch/blackfin/include/asm/trace.h
@@ -0,0 +1,94 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_TRACE_
7#define _BLACKFIN_TRACE_
8
9/* Normally, we use ON, but you can't turn on software expansion until
10 * interrupts subsystem is ready
11 */
12
13#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
14#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
15#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
16#else
17#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
18#endif
19
20#ifndef __ASSEMBLY__
21extern unsigned long trace_buff_offset;
22extern unsigned long software_trace_buff[];
23
24/* Trace Macros for C files */
25
26#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
27
28#define trace_buffer_save(x) \
29 do { \
30 (x) = bfin_read_TBUFCTL(); \
31 bfin_write_TBUFCTL((x) & ~TBUFEN); \
32 } while (0)
33
34#define trace_buffer_restore(x) \
35 do { \
36 bfin_write_TBUFCTL((x)); \
37 } while (0)
38#else /* DEBUG_BFIN_HWTRACE_ON */
39
40#define trace_buffer_save(x)
41#define trace_buffer_restore(x)
42#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
43
44#else
45/* Trace Macros for Assembly files */
46
47#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
48
49#define trace_buffer_stop(preg, dreg) \
50 preg.L = LO(TBUFCTL); \
51 preg.H = HI(TBUFCTL); \
52 dreg = 0x1; \
53 [preg] = dreg;
54
55#define trace_buffer_init(preg, dreg) \
56 preg.L = LO(TBUFCTL); \
57 preg.H = HI(TBUFCTL); \
58 dreg = BFIN_TRACE_INIT; \
59 [preg] = dreg;
60
61#define trace_buffer_save(preg, dreg) \
62 preg.L = LO(TBUFCTL); \
63 preg.H = HI(TBUFCTL); \
64 dreg = [preg]; \
65 [--sp] = dreg; \
66 dreg = 0x1; \
67 [preg] = dreg;
68
69#define trace_buffer_restore(preg, dreg) \
70 preg.L = LO(TBUFCTL); \
71 preg.H = HI(TBUFCTL); \
72 dreg = [sp++]; \
73 [preg] = dreg;
74
75#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
76
77#define trace_buffer_stop(preg, dreg)
78#define trace_buffer_init(preg, dreg)
79#define trace_buffer_save(preg, dreg)
80#define trace_buffer_restore(preg, dreg)
81
82#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
83
84#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
85# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
86# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
87#else
88# define DEBUG_HWTRACE_SAVE(preg, dreg)
89# define DEBUG_HWTRACE_RESTORE(preg, dreg)
90#endif
91
92#endif /* __ASSEMBLY__ */
93
94#endif /* _BLACKFIN_TRACE_ */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
new file mode 100644
index 000000000000..f0e5f940d9ca
--- /dev/null
+++ b/arch/blackfin/include/asm/traps.h
@@ -0,0 +1,131 @@
1/*
2 * linux/include/asm/traps.h
3 *
4 * Copyright (C) 1993 Hamish Macdonald
5 *
6 * Lineo, Inc Jul 2001 Tony Kou
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef _BFIN_TRAPS_H
14#define _BFIN_TRAPS_H
15
16#define VEC_SYS (0)
17#define VEC_EXCPT01 (1)
18#define VEC_EXCPT02 (2)
19#define VEC_EXCPT03 (3)
20#define VEC_EXCPT04 (4)
21#define VEC_EXCPT05 (5)
22#define VEC_EXCPT06 (6)
23#define VEC_EXCPT07 (7)
24#define VEC_EXCPT08 (8)
25#define VEC_EXCPT09 (9)
26#define VEC_EXCPT10 (10)
27#define VEC_EXCPT11 (11)
28#define VEC_EXCPT12 (12)
29#define VEC_EXCPT13 (13)
30#define VEC_EXCPT14 (14)
31#define VEC_EXCPT15 (15)
32#define VEC_STEP (16)
33#define VEC_OVFLOW (17)
34#define VEC_UNDEF_I (33)
35#define VEC_ILGAL_I (34)
36#define VEC_CPLB_VL (35)
37#define VEC_MISALI_D (36)
38#define VEC_UNCOV (37)
39#define VEC_CPLB_M (38)
40#define VEC_CPLB_MHIT (39)
41#define VEC_WATCH (40)
42#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
43#define VEC_MISALI_I (42)
44#define VEC_CPLB_I_VL (43)
45#define VEC_CPLB_I_M (44)
46#define VEC_CPLB_I_MHIT (45)
47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
48/* The hardware reserves (63) for future use - we use it to tell our
49 * normal exception handling code we have a hardware error
50 */
51#define VEC_HWERR (63)
52
53#ifndef __ASSEMBLY__
54
55#define HWC_x2(level) \
56 "System MMR Error\n" \
57 level " - An error occurred due to an invalid access to an System MMR location\n" \
58 level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
59 level " or a 16-bit register is accessed with a 32-bit instruction.\n"
60#define HWC_x3(level) \
61 "External Memory Addressing Error\n"
62#define HWC_x12(level) \
63 "Performance Monitor Overflow\n"
64#define HWC_x18(level) \
65 "RAISE 5 instruction\n" \
66 level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
67#define HWC_default(level) \
68 "Reserved\n"
69#define EXC_0x03(level) \
70 "Application stack overflow\n" \
71 level " - Please increase the stack size of the application using elf2flt -s option,\n" \
72 level " and/or reduce the stack use of the application.\n"
73#define EXC_0x10(level) \
74 "Single step\n" \
75 level " - When the processor is in single step mode, every instruction\n" \
76 level " generates an exception. Primarily used for debugging.\n"
77#define EXC_0x11(level) \
78 "Exception caused by a trace buffer full condition\n" \
79 level " - The processor takes this exception when the trace\n" \
80 level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
81#define EXC_0x21(level) \
82 "Undefined instruction\n" \
83 level " - May be used to emulate instructions that are not defined for\n" \
84 level " a particular processor implementation.\n"
85#define EXC_0x22(level) \
86 "Illegal instruction combination\n" \
87 level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
88 level " Processor Instruction Set Reference.\n"
89#define EXC_0x23(level) \
90 "Data access CPLB protection violation\n" \
91 level " - Attempted read or write to Supervisor resource,\n" \
92 level " or illegal data memory access. \n"
93#define EXC_0x24(level) \
94 "Data access misaligned address violation\n" \
95 level " - Attempted misaligned data memory or data cache access.\n"
96#define EXC_0x25(level) \
97 "Unrecoverable event\n" \
98 level " - For example, an exception generated while processing a previous exception.\n"
99#define EXC_0x26(level) \
100 "Data access CPLB miss\n" \
101 level " - Used by the MMU to signal a CPLB miss on a data access.\n"
102#define EXC_0x27(level) \
103 "Data access multiple CPLB hits\n" \
104 level " - More than one CPLB entry matches data fetch address.\n"
105#define EXC_0x28(level) \
106 "Program Sequencer Exception caused by an emulation watchpoint match\n" \
107 level " - There is a watchpoint match, and one of the EMUSW\n" \
108 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
109#define EXC_0x2A(level) \
110 "Instruction fetch misaligned address violation\n" \
111 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
112 level " exception, the return address provided in RETX is the destination address which is\n" \
113 level " misaligned, rather than the address of the offending instruction.\n"
114#define EXC_0x2B(level) \
115 "CPLB protection violation\n" \
116 level " - Illegal instruction fetch access (memory protection violation).\n"
117#define EXC_0x2C(level) \
118 "Instruction fetch CPLB miss\n" \
119 level " - CPLB miss on an instruction fetch.\n"
120#define EXC_0x2D(level) \
121 "Instruction fetch multiple CPLB hits\n" \
122 level " - More than one CPLB entry matches instruction fetch address.\n"
123#define EXC_0x2E(level) \
124 "Illegal use of supervisor resource\n" \
125 level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
126 level " Supervisor resources are registers and instructions that are reserved\n" \
127 level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
128 level " only instructions.\n"
129
130#endif /* __ASSEMBLY__ */
131#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
new file mode 100644
index 000000000000..8441cbc2bf9e
--- /dev/null
+++ b/arch/blackfin/include/asm/types.h
@@ -0,0 +1,36 @@
1#ifndef _BFIN_TYPES_H
2#define _BFIN_TYPES_H
3
4/*
5 * This file is never included by application software unless
6 * explicitly requested (e.g., via linux/types.h) in which case the
7 * application is Linux specific so (user-) name space pollution is
8 * not a major issue. However, for interoperability, libraries still
9 * need to be careful to avoid a name clashes.
10 */
11#include <asm-generic/int-ll64.h>
12
13#ifndef __ASSEMBLY__
14
15typedef unsigned short umode_t;
16
17#endif /* __ASSEMBLY__ */
18/*
19 * These aren't exported outside the kernel to avoid name space clashes
20 */
21#ifdef __KERNEL__
22
23#define BITS_PER_LONG 32
24
25#ifndef __ASSEMBLY__
26
27/* Dma addresses are 32-bits wide. */
28
29typedef u32 dma_addr_t;
30typedef u64 dma64_addr_t;
31
32#endif /* __ASSEMBLY__ */
33
34#endif /* __KERNEL__ */
35
36#endif /* _BFIN_TYPES_H */
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
new file mode 100644
index 000000000000..d928b8099056
--- /dev/null
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -0,0 +1,271 @@
1/* Changes made by Lineo Inc. May 2001
2 *
3 * Based on: include/asm-m68knommu/uaccess.h
4 */
5
6#ifndef __BLACKFIN_UACCESS_H
7#define __BLACKFIN_UACCESS_H
8
9/*
10 * User space memory access functions
11 */
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/string.h>
15
16#include <asm/segment.h>
17#ifdef CONFIG_ACCESS_CHECK
18# include <asm/bfin-global.h>
19#endif
20
21#define get_ds() (KERNEL_DS)
22#define get_fs() (current_thread_info()->addr_limit)
23
24static inline void set_fs(mm_segment_t fs)
25{
26 current_thread_info()->addr_limit = fs;
27}
28
29#define segment_eq(a,b) ((a) == (b))
30
31#define VERIFY_READ 0
32#define VERIFY_WRITE 1
33
34#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
35
36static inline int is_in_rom(unsigned long addr)
37{
38 /*
39 * What we are really trying to do is determine if addr is
40 * in an allocated kernel memory region. If not then assume
41 * we cannot free it or otherwise de-allocate it. Ideally
42 * we could restrict this to really being in a ROM or flash,
43 * but that would need to be done on a board by board basis,
44 * not globally.
45 */
46 if ((addr < _ramstart) || (addr >= _ramend))
47 return (1);
48
49 /* Default case, not in ROM */
50 return (0);
51}
52
53/*
54 * The fs value determines whether argument validity checking should be
55 * performed or not. If get_fs() == USER_DS, checking is performed, with
56 * get_fs() == KERNEL_DS, checking is bypassed.
57 */
58
59#ifndef CONFIG_ACCESS_CHECK
60static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
61#else
62#ifdef CONFIG_ACCESS_OK_L1
63extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
64#else
65extern int _access_ok(unsigned long addr, unsigned long size);
66#endif
67#endif
68
69/*
70 * The exception table consists of pairs of addresses: the first is the
71 * address of an instruction that is allowed to fault, and the second is
72 * the address at which the program should continue. No registers are
73 * modified, so it is entirely up to the continuation code to figure out
74 * what to do.
75 *
76 * All the routines below use bits of fixup code that are out of line
77 * with the main instruction path. This means when everything is well,
78 * we don't even have to jump over them. Further, they do not intrude
79 * on our cache or tlb entries.
80 */
81
82struct exception_table_entry {
83 unsigned long insn, fixup;
84};
85
86/* Returns 0 if exception not found and fixup otherwise. */
87extern unsigned long search_exception_table(unsigned long);
88
89/*
90 * These are the main single-value transfer routines. They automatically
91 * use the right size if we just have the right pointer type.
92 */
93
94#define put_user(x,p) \
95 ({ \
96 int _err = 0; \
97 typeof(*(p)) _x = (x); \
98 typeof(*(p)) *_p = (p); \
99 if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
100 _err = -EFAULT; \
101 } \
102 else { \
103 switch (sizeof (*(_p))) { \
104 case 1: \
105 __put_user_asm(_x, _p, B); \
106 break; \
107 case 2: \
108 __put_user_asm(_x, _p, W); \
109 break; \
110 case 4: \
111 __put_user_asm(_x, _p, ); \
112 break; \
113 case 8: { \
114 long _xl, _xh; \
115 _xl = ((long *)&_x)[0]; \
116 _xh = ((long *)&_x)[1]; \
117 __put_user_asm(_xl, ((long *)_p)+0, ); \
118 __put_user_asm(_xh, ((long *)_p)+1, ); \
119 } break; \
120 default: \
121 _err = __put_user_bad(); \
122 break; \
123 } \
124 } \
125 _err; \
126 })
127
128#define __put_user(x,p) put_user(x,p)
129static inline int bad_user_access_length(void)
130{
131 panic("bad_user_access_length");
132 return -1;
133}
134
135#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
136 __FILE__, __LINE__, __func__),\
137 bad_user_access_length(), (-EFAULT))
138
139/*
140 * Tell gcc we read from memory instead of writing: this is because
141 * we do not write to any memory gcc knows about, so there are no
142 * aliasing issues.
143 */
144
145#define __ptr(x) ((unsigned long *)(x))
146
147#define __put_user_asm(x,p,bhw) \
148 __asm__ (#bhw"[%1] = %0;\n\t" \
149 : /* no outputs */ \
150 :"d" (x),"a" (__ptr(p)) : "memory")
151
152#define get_user(x,p) \
153 ({ \
154 int _err = 0; \
155 typeof(*(p)) *_p = (p); \
156 if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) { \
157 _err = -EFAULT; \
158 } \
159 else { \
160 switch (sizeof(*(_p))) { \
161 case 1: \
162 __get_user_asm(x, _p, B,(Z)); \
163 break; \
164 case 2: \
165 __get_user_asm(x, _p, W,(Z)); \
166 break; \
167 case 4: \
168 __get_user_asm(x, _p, , ); \
169 break; \
170 case 8: { \
171 unsigned long _xl, _xh; \
172 __get_user_asm(_xl, ((unsigned long *)_p)+0, , ); \
173 __get_user_asm(_xh, ((unsigned long *)_p)+1, , ); \
174 ((unsigned long *)&x)[0] = _xl; \
175 ((unsigned long *)&x)[1] = _xh; \
176 } break; \
177 default: \
178 x = 0; \
179 printk(KERN_INFO "get_user_bad: %s:%d %s\n", \
180 __FILE__, __LINE__, __func__); \
181 _err = __get_user_bad(); \
182 break; \
183 } \
184 } \
185 _err; \
186 })
187
188#define __get_user(x,p) get_user(x,p)
189
190#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
191
192#define __get_user_asm(x,p,bhw,option) \
193 { \
194 unsigned long _tmp; \
195 __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \
196 : "=d" (_tmp) \
197 : "a" (__ptr(p))); \
198 (x) = (__typeof__(*(p))) _tmp; \
199 }
200
201#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
202#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
203#define __copy_to_user_inatomic __copy_to_user
204#define __copy_from_user_inatomic __copy_from_user
205
206#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
207 return retval; })
208
209#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
210 return retval; })
211
212static inline long copy_from_user(void *to,
213 const void __user * from, unsigned long n)
214{
215 if (access_ok(VERIFY_READ, from, n))
216 memcpy(to, from, n);
217 else
218 return n;
219 return 0;
220}
221
222static inline long copy_to_user(void *to,
223 const void __user * from, unsigned long n)
224{
225 if (access_ok(VERIFY_WRITE, to, n))
226 memcpy(to, from, n);
227 else
228 return n;
229 return 0;
230}
231
232/*
233 * Copy a null terminated string from userspace.
234 */
235
236static inline long strncpy_from_user(char *dst,
237 const char *src, long count)
238{
239 char *tmp;
240 if (!access_ok(VERIFY_READ, src, 1))
241 return -EFAULT;
242 strncpy(dst, src, count);
243 for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
244 return (tmp - dst);
245}
246
247/*
248 * Return the size of a string (including the ending 0)
249 *
250 * Return 0 on exception, a value greater than N if too long
251 */
252static inline long strnlen_user(const char *src, long n)
253{
254 return (strlen(src) + 1);
255}
256
257#define strlen_user(str) strnlen_user(str, 32767)
258
259/*
260 * Zero Userspace
261 */
262
263static inline unsigned long __clear_user(void *to, unsigned long n)
264{
265 memset(to, 0, n);
266 return 0;
267}
268
269#define clear_user(to, n) __clear_user(to, n)
270
271#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h
new file mode 100644
index 000000000000..4a4e3856beba
--- /dev/null
+++ b/arch/blackfin/include/asm/ucontext.h
@@ -0,0 +1,17 @@
1/** Changes made by Tony Kou Lineo Inc. May 2001
2 *
3 * Based on: include/m68knommu/ucontext.h
4 */
5
6#ifndef _BLACKFIN_UCONTEXT_H
7#define _BLACKFIN_UCONTEXT_H
8
9struct ucontext {
10 unsigned long uc_flags; /* the others are necessary */
11 struct ucontext *uc_link;
12 stack_t uc_stack;
13 struct sigcontext uc_mcontext;
14 sigset_t uc_sigmask; /* mask last for extensibility */
15};
16
17#endif /* _BLACKFIN_UCONTEXT_H */
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
new file mode 100644
index 000000000000..fd8a1d634945
--- /dev/null
+++ b/arch/blackfin/include/asm/unaligned.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_BLACKFIN_UNALIGNED_H
2#define _ASM_BLACKFIN_UNALIGNED_H
3
4#include <linux/unaligned/le_struct.h>
5#include <linux/unaligned/be_byteshift.h>
6#include <linux/unaligned/generic.h>
7
8#define get_unaligned __get_unaligned_le
9#define put_unaligned __put_unaligned_le
10
11#endif /* _ASM_BLACKFIN_UNALIGNED_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
new file mode 100644
index 000000000000..1e57b636e0bc
--- /dev/null
+++ b/arch/blackfin/include/asm/unistd.h
@@ -0,0 +1,438 @@
1#ifndef __ASM_BFIN_UNISTD_H
2#define __ASM_BFIN_UNISTD_H
3/*
4 * This file contains the system call numbers.
5 */
6#define __NR_restart_syscall 0
7#define __NR_exit 1
8#define __NR_fork 2
9#define __NR_read 3
10#define __NR_write 4
11#define __NR_open 5
12#define __NR_close 6
13 /* 7 __NR_waitpid obsolete */
14#define __NR_creat 8
15#define __NR_link 9
16#define __NR_unlink 10
17#define __NR_execve 11
18#define __NR_chdir 12
19#define __NR_time 13
20#define __NR_mknod 14
21#define __NR_chmod 15
22#define __NR_chown 16
23 /* 17 __NR_break obsolete */
24 /* 18 __NR_oldstat obsolete */
25#define __NR_lseek 19
26#define __NR_getpid 20
27#define __NR_mount 21
28 /* 22 __NR_umount obsolete */
29#define __NR_setuid 23
30#define __NR_getuid 24
31#define __NR_stime 25
32#define __NR_ptrace 26
33#define __NR_alarm 27
34 /* 28 __NR_oldfstat obsolete */
35#define __NR_pause 29
36 /* 30 __NR_utime obsolete */
37 /* 31 __NR_stty obsolete */
38 /* 32 __NR_gtty obsolete */
39#define __NR_access 33
40#define __NR_nice 34
41 /* 35 __NR_ftime obsolete */
42#define __NR_sync 36
43#define __NR_kill 37
44#define __NR_rename 38
45#define __NR_mkdir 39
46#define __NR_rmdir 40
47#define __NR_dup 41
48#define __NR_pipe 42
49#define __NR_times 43
50 /* 44 __NR_prof obsolete */
51#define __NR_brk 45
52#define __NR_setgid 46
53#define __NR_getgid 47
54 /* 48 __NR_signal obsolete */
55#define __NR_geteuid 49
56#define __NR_getegid 50
57#define __NR_acct 51
58#define __NR_umount2 52
59 /* 53 __NR_lock obsolete */
60#define __NR_ioctl 54
61#define __NR_fcntl 55
62 /* 56 __NR_mpx obsolete */
63#define __NR_setpgid 57
64 /* 58 __NR_ulimit obsolete */
65 /* 59 __NR_oldolduname obsolete */
66#define __NR_umask 60
67#define __NR_chroot 61
68#define __NR_ustat 62
69#define __NR_dup2 63
70#define __NR_getppid 64
71#define __NR_getpgrp 65
72#define __NR_setsid 66
73 /* 67 __NR_sigaction obsolete */
74#define __NR_sgetmask 68
75#define __NR_ssetmask 69
76#define __NR_setreuid 70
77#define __NR_setregid 71
78 /* 72 __NR_sigsuspend obsolete */
79 /* 73 __NR_sigpending obsolete */
80#define __NR_sethostname 74
81#define __NR_setrlimit 75
82 /* 76 __NR_old_getrlimit obsolete */
83#define __NR_getrusage 77
84#define __NR_gettimeofday 78
85#define __NR_settimeofday 79
86#define __NR_getgroups 80
87#define __NR_setgroups 81
88 /* 82 __NR_select obsolete */
89#define __NR_symlink 83
90 /* 84 __NR_oldlstat obsolete */
91#define __NR_readlink 85
92 /* 86 __NR_uselib obsolete */
93 /* 87 __NR_swapon obsolete */
94#define __NR_reboot 88
95 /* 89 __NR_readdir obsolete */
96 /* 90 __NR_mmap obsolete */
97#define __NR_munmap 91
98#define __NR_truncate 92
99#define __NR_ftruncate 93
100#define __NR_fchmod 94
101#define __NR_fchown 95
102#define __NR_getpriority 96
103#define __NR_setpriority 97
104 /* 98 __NR_profil obsolete */
105#define __NR_statfs 99
106#define __NR_fstatfs 100
107 /* 101 __NR_ioperm */
108 /* 102 __NR_socketcall obsolete */
109#define __NR_syslog 103
110#define __NR_setitimer 104
111#define __NR_getitimer 105
112#define __NR_stat 106
113#define __NR_lstat 107
114#define __NR_fstat 108
115 /* 109 __NR_olduname obsolete */
116 /* 110 __NR_iopl obsolete */
117#define __NR_vhangup 111
118 /* 112 __NR_idle obsolete */
119 /* 113 __NR_vm86old */
120#define __NR_wait4 114
121 /* 115 __NR_swapoff obsolete */
122#define __NR_sysinfo 116
123 /* 117 __NR_ipc oboslete */
124#define __NR_fsync 118
125 /* 119 __NR_sigreturn obsolete */
126#define __NR_clone 120
127#define __NR_setdomainname 121
128#define __NR_uname 122
129 /* 123 __NR_modify_ldt obsolete */
130#define __NR_adjtimex 124
131#define __NR_mprotect 125
132 /* 126 __NR_sigprocmask obsolete */
133 /* 127 __NR_create_module obsolete */
134#define __NR_init_module 128
135#define __NR_delete_module 129
136 /* 130 __NR_get_kernel_syms obsolete */
137#define __NR_quotactl 131
138#define __NR_getpgid 132
139#define __NR_fchdir 133
140#define __NR_bdflush 134
141 /* 135 was sysfs */
142#define __NR_personality 136
143 /* 137 __NR_afs_syscall */
144#define __NR_setfsuid 138
145#define __NR_setfsgid 139
146#define __NR__llseek 140
147#define __NR_getdents 141
148 /* 142 __NR__newselect obsolete */
149#define __NR_flock 143
150 /* 144 __NR_msync obsolete */
151#define __NR_readv 145
152#define __NR_writev 146
153#define __NR_getsid 147
154#define __NR_fdatasync 148
155#define __NR__sysctl 149
156 /* 150 __NR_mlock */
157 /* 151 __NR_munlock */
158 /* 152 __NR_mlockall */
159 /* 153 __NR_munlockall */
160#define __NR_sched_setparam 154
161#define __NR_sched_getparam 155
162#define __NR_sched_setscheduler 156
163#define __NR_sched_getscheduler 157
164#define __NR_sched_yield 158
165#define __NR_sched_get_priority_max 159
166#define __NR_sched_get_priority_min 160
167#define __NR_sched_rr_get_interval 161
168#define __NR_nanosleep 162
169#define __NR_mremap 163
170#define __NR_setresuid 164
171#define __NR_getresuid 165
172 /* 166 __NR_vm86 */
173 /* 167 __NR_query_module */
174 /* 168 __NR_poll */
175#define __NR_nfsservctl 169
176#define __NR_setresgid 170
177#define __NR_getresgid 171
178#define __NR_prctl 172
179#define __NR_rt_sigreturn 173
180#define __NR_rt_sigaction 174
181#define __NR_rt_sigprocmask 175
182#define __NR_rt_sigpending 176
183#define __NR_rt_sigtimedwait 177
184#define __NR_rt_sigqueueinfo 178
185#define __NR_rt_sigsuspend 179
186#define __NR_pread 180
187#define __NR_pwrite 181
188#define __NR_lchown 182
189#define __NR_getcwd 183
190#define __NR_capget 184
191#define __NR_capset 185
192#define __NR_sigaltstack 186
193#define __NR_sendfile 187
194 /* 188 __NR_getpmsg */
195 /* 189 __NR_putpmsg */
196#define __NR_vfork 190
197#define __NR_getrlimit 191
198#define __NR_mmap2 192
199#define __NR_truncate64 193
200#define __NR_ftruncate64 194
201#define __NR_stat64 195
202#define __NR_lstat64 196
203#define __NR_fstat64 197
204#define __NR_chown32 198
205#define __NR_getuid32 199
206#define __NR_getgid32 200
207#define __NR_geteuid32 201
208#define __NR_getegid32 202
209#define __NR_setreuid32 203
210#define __NR_setregid32 204
211#define __NR_getgroups32 205
212#define __NR_setgroups32 206
213#define __NR_fchown32 207
214#define __NR_setresuid32 208
215#define __NR_getresuid32 209
216#define __NR_setresgid32 210
217#define __NR_getresgid32 211
218#define __NR_lchown32 212
219#define __NR_setuid32 213
220#define __NR_setgid32 214
221#define __NR_setfsuid32 215
222#define __NR_setfsgid32 216
223#define __NR_pivot_root 217
224 /* 218 __NR_mincore */
225 /* 219 __NR_madvise */
226#define __NR_getdents64 220
227#define __NR_fcntl64 221
228 /* 222 reserved for TUX */
229 /* 223 reserved for TUX */
230#define __NR_gettid 224
231#define __NR_readahead 225
232#define __NR_setxattr 226
233#define __NR_lsetxattr 227
234#define __NR_fsetxattr 228
235#define __NR_getxattr 229
236#define __NR_lgetxattr 230
237#define __NR_fgetxattr 231
238#define __NR_listxattr 232
239#define __NR_llistxattr 233
240#define __NR_flistxattr 234
241#define __NR_removexattr 235
242#define __NR_lremovexattr 236
243#define __NR_fremovexattr 237
244#define __NR_tkill 238
245#define __NR_sendfile64 239
246#define __NR_futex 240
247#define __NR_sched_setaffinity 241
248#define __NR_sched_getaffinity 242
249 /* 243 __NR_set_thread_area */
250 /* 244 __NR_get_thread_area */
251#define __NR_io_setup 245
252#define __NR_io_destroy 246
253#define __NR_io_getevents 247
254#define __NR_io_submit 248
255#define __NR_io_cancel 249
256 /* 250 __NR_alloc_hugepages */
257 /* 251 __NR_free_hugepages */
258#define __NR_exit_group 252
259#define __NR_lookup_dcookie 253
260#define __NR_bfin_spinlock 254
261
262#define __NR_epoll_create 255
263#define __NR_epoll_ctl 256
264#define __NR_epoll_wait 257
265 /* 258 __NR_remap_file_pages */
266#define __NR_set_tid_address 259
267#define __NR_timer_create 260
268#define __NR_timer_settime 261
269#define __NR_timer_gettime 262
270#define __NR_timer_getoverrun 263
271#define __NR_timer_delete 264
272#define __NR_clock_settime 265
273#define __NR_clock_gettime 266
274#define __NR_clock_getres 267
275#define __NR_clock_nanosleep 268
276#define __NR_statfs64 269
277#define __NR_fstatfs64 270
278#define __NR_tgkill 271
279#define __NR_utimes 272
280#define __NR_fadvise64_64 273
281 /* 274 __NR_vserver */
282 /* 275 __NR_mbind */
283 /* 276 __NR_get_mempolicy */
284 /* 277 __NR_set_mempolicy */
285#define __NR_mq_open 278
286#define __NR_mq_unlink 279
287#define __NR_mq_timedsend 280
288#define __NR_mq_timedreceive 281
289#define __NR_mq_notify 282
290#define __NR_mq_getsetattr 283
291#define __NR_kexec_load 284
292#define __NR_waitid 285
293#define __NR_add_key 286
294#define __NR_request_key 287
295#define __NR_keyctl 288
296#define __NR_ioprio_set 289
297#define __NR_ioprio_get 290
298#define __NR_inotify_init 291
299#define __NR_inotify_add_watch 292
300#define __NR_inotify_rm_watch 293
301 /* 294 __NR_migrate_pages */
302#define __NR_openat 295
303#define __NR_mkdirat 296
304#define __NR_mknodat 297
305#define __NR_fchownat 298
306#define __NR_futimesat 299
307#define __NR_fstatat64 300
308#define __NR_unlinkat 301
309#define __NR_renameat 302
310#define __NR_linkat 303
311#define __NR_symlinkat 304
312#define __NR_readlinkat 305
313#define __NR_fchmodat 306
314#define __NR_faccessat 307
315#define __NR_pselect6 308
316#define __NR_ppoll 309
317#define __NR_unshare 310
318
319/* Blackfin private syscalls */
320#define __NR_sram_alloc 311
321#define __NR_sram_free 312
322#define __NR_dma_memcpy 313
323
324/* socket syscalls */
325#define __NR_accept 314
326#define __NR_bind 315
327#define __NR_connect 316
328#define __NR_getpeername 317
329#define __NR_getsockname 318
330#define __NR_getsockopt 319
331#define __NR_listen 320
332#define __NR_recv 321
333#define __NR_recvfrom 322
334#define __NR_recvmsg 323
335#define __NR_send 324
336#define __NR_sendmsg 325
337#define __NR_sendto 326
338#define __NR_setsockopt 327
339#define __NR_shutdown 328
340#define __NR_socket 329
341#define __NR_socketpair 330
342
343/* sysv ipc syscalls */
344#define __NR_semctl 331
345#define __NR_semget 332
346#define __NR_semop 333
347#define __NR_msgctl 334
348#define __NR_msgget 335
349#define __NR_msgrcv 336
350#define __NR_msgsnd 337
351#define __NR_shmat 338
352#define __NR_shmctl 339
353#define __NR_shmdt 340
354#define __NR_shmget 341
355
356#define __NR_splice 342
357#define __NR_sync_file_range 343
358#define __NR_tee 344
359#define __NR_vmsplice 345
360
361#define __NR_epoll_pwait 346
362#define __NR_utimensat 347
363#define __NR_signalfd 348
364#define __NR_timerfd_create 349
365#define __NR_eventfd 350
366#define __NR_pread64 351
367#define __NR_pwrite64 352
368#define __NR_fadvise64 353
369#define __NR_set_robust_list 354
370#define __NR_get_robust_list 355
371#define __NR_fallocate 356
372#define __NR_semtimedop 357
373#define __NR_timerfd_settime 358
374#define __NR_timerfd_gettime 359
375#define __NR_signalfd4 360
376#define __NR_eventfd2 361
377#define __NR_epoll_create1 362
378#define __NR_dup3 363
379#define __NR_pipe2 364
380#define __NR_inotify_init1 365
381
382#define __NR_syscall 366
383#define NR_syscalls __NR_syscall
384
385/* Old optional stuff no one actually uses */
386#define __IGNORE_sysfs
387#define __IGNORE_uselib
388
389/* Implement the newer interfaces */
390#define __IGNORE_mmap
391#define __IGNORE_poll
392#define __IGNORE_select
393#define __IGNORE_utime
394
395/* Not relevant on no-mmu */
396#define __IGNORE_swapon
397#define __IGNORE_swapoff
398#define __IGNORE_msync
399#define __IGNORE_mlock
400#define __IGNORE_munlock
401#define __IGNORE_mlockall
402#define __IGNORE_munlockall
403#define __IGNORE_mincore
404#define __IGNORE_madvise
405#define __IGNORE_remap_file_pages
406#define __IGNORE_mbind
407#define __IGNORE_get_mempolicy
408#define __IGNORE_set_mempolicy
409#define __IGNORE_migrate_pages
410#define __IGNORE_move_pages
411#define __IGNORE_getcpu
412
413#ifdef __KERNEL__
414#define __ARCH_WANT_IPC_PARSE_VERSION
415#define __ARCH_WANT_STAT64
416#define __ARCH_WANT_SYS_ALARM
417#define __ARCH_WANT_SYS_GETHOSTNAME
418#define __ARCH_WANT_SYS_PAUSE
419#define __ARCH_WANT_SYS_SGETMASK
420#define __ARCH_WANT_SYS_TIME
421#define __ARCH_WANT_SYS_FADVISE64
422#define __ARCH_WANT_SYS_GETPGRP
423#define __ARCH_WANT_SYS_LLSEEK
424#define __ARCH_WANT_SYS_NICE
425#define __ARCH_WANT_SYS_RT_SIGACTION
426#define __ARCH_WANT_SYS_RT_SIGSUSPEND
427
428/*
429 * "Conditional" syscalls
430 *
431 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
432 * but it doesn't work on all toolchains, so we just do it by hand
433 */
434#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
435
436#endif /* __KERNEL__ */
437
438#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h
new file mode 100644
index 000000000000..afe6a0e1f7ce
--- /dev/null
+++ b/arch/blackfin/include/asm/user.h
@@ -0,0 +1,89 @@
1#ifndef _BFIN_USER_H
2#define _BFIN_USER_H
3
4/* Changes by Tony Kou Lineo, Inc. July, 2001
5 *
6 * Based include/asm-m68knommu/user.h
7 *
8 */
9
10/* Core file format: The core file is written in such a way that gdb
11 can understand it and provide useful information to the user (under
12 linux we use the 'trad-core' bfd). There are quite a number of
13 obstacles to being able to view the contents of the floating point
14 registers, and until these are solved you will not be able to view the
15 contents of them. Actually, you can read in the core file and look at
16 the contents of the user struct to find out what the floating point
17 registers contain.
18 The actual file contents are as follows:
19 UPAGE: 1 page consisting of a user struct that tells gdb what is present
20 in the file. Directly after this is a copy of the task_struct, which
21 is currently not used by gdb, but it may come in useful at some point.
22 All of the registers are stored as part of the upage. The upage should
23 always be only one page.
24 DATA: The data area is stored. We use current->end_text to
25 current->brk to pick up all of the user variables, plus any memory
26 that may have been malloced. No attempt is made to determine if a page
27 is demand-zero or if a page is totally unused, we just cover the entire
28 range. All of the addresses are rounded in such a way that an integral
29 number of pages is written.
30 STACK: We need the stack information in order to get a meaningful
31 backtrace. We need to write the data from (esp) to
32 current->start_stack, so we round each of these off in order to be able
33 to write an integer number of pages.
34 The minimum core file size is 3 pages, or 12288 bytes.
35*/
36struct user_bfinfp_struct {
37};
38
39/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
40 is still the layout used by user (the new pt_regs doesn't have
41 all registers). */
42struct user_regs_struct {
43 long r0, r1, r2, r3, r4, r5, r6, r7;
44 long p0, p1, p2, p3, p4, p5, usp, fp;
45 long i0, i1, i2, i3;
46 long l0, l1, l2, l3;
47 long b0, b1, b2, b3;
48 long m0, m1, m2, m3;
49 long a0w, a1w;
50 long a0x, a1x;
51 unsigned long rets;
52 unsigned long astat;
53 unsigned long pc;
54 unsigned long orig_p0;
55};
56
57/* When the kernel dumps core, it starts by dumping the user struct -
58 this will be used by gdb to figure out where the data and stack segments
59 are within the file, and what virtual addresses to use. */
60
61struct user {
62/* We start with the registers, to mimic the way that "memory" is returned
63 from the ptrace(3,...) function. */
64
65 struct user_regs_struct regs; /* Where the registers are actually stored */
66
67/* The rest of this junk is to help gdb figure out what goes where */
68 unsigned long int u_tsize; /* Text segment size (pages). */
69 unsigned long int u_dsize; /* Data segment size (pages). */
70 unsigned long int u_ssize; /* Stack segment size (pages). */
71 unsigned long start_code; /* Starting virtual address of text. */
72 unsigned long start_stack; /* Starting virtual address of stack area.
73 This is actually the bottom of the stack,
74 the top of the stack is always found in the
75 esp register. */
76 long int signal; /* Signal that caused the core dump. */
77 int reserved; /* No longer used */
78 unsigned long u_ar0;
79 /* Used by gdb to help find the values for */
80 /* the registers. */
81 unsigned long magic; /* To uniquely identify a core file */
82 char u_comm[32]; /* User command that was responsible */
83};
84#define NBPG PAGE_SIZE
85#define UPAGES 1
86#define HOST_TEXT_START_ADDR (u.start_code)
87#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
88
89#endif
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