blackfin: SEC: clean up SEC interrupt initialization

Append the SEC IRQ after the IVG6, which is consistent to BF5xx SIC.
Exclude SIC irqchip fucntions from SEC code.
Call handle_fasteoi_irq in SEC error and fault handler.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
index cab14e911dc2..af9fc8171ebc 100644
--- a/arch/blackfin/include/mach-common/irq.h
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -40,8 +40,6 @@
 #define IRQ_HWERR               5       /* Hardware Error */
 #define IRQ_CORETMR             6       /* Core timer */
 
-#define BFIN_IRQ(x)             ((x) + 7)
-
 #define IVG7                    7
 #define IVG8                    8
 #define IVG9                    9
@@ -52,6 +50,9 @@
 #define IVG14                   14
 #define IVG15                   15
 
+#define BFIN_IRQ(x)             ((x) + IVG7)
+#define BFIN_SYSIRQ(x)          ((x) - IVG7)
+
 #define NR_IRQS                 (NR_MACH_IRQS + NR_SPARE_IRQS)
 
 #endif