aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/include
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-18 20:02:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-18 20:02:35 -0400
commit39710479303fd3affb3e204e9a7a75cc676977b5 (patch)
tree3fff5fb412df77170883f02fc54bdbee9aba4f22 /arch/blackfin/include
parent9d20593a722c2dab7a5ab74f5d8c9b604aca52f9 (diff)
parenteb63e5d15758d2b1e607ddd5fb861b5596629380 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (96 commits) Blackfin: stop cleaning include/asm/asm-offsets.h Blackfin: scale calibration when cpu freq changes Blackfin: eat spurious space in asm/dpmc.h Blackfin: fix anomaly 283 handling with exact hardware error Blackfin: bf537-stamp: add example ADXL346 orientation resources Blackfin: bf537-stamp: add example AD2S1210 IIO resources Blackfin: don't support keypad wakeup from hibernate Blackfin: bf537-stamp: add example AD7416 IIO resources Blackfin: bf537-stamp: add example ADP8860 backlight/led resources Blackfin: bf537-stamp: add example AD7414 temp sensor resources Blackfin: rename AD1836 to AD183X in board files Blackfin: bf537-stamp: add example AD2S120x resources Blackfin: add support for the on-chip MAC status interrupts Blackfin: asm/page.h: pull in asm-generic headers Blackfin: mark gpio lib functions static Blackfin: bf537-stamp: add example ADAU1361 resources Blackfin: GPIO: implement to_irq handler Blackfin: bf537-stamp: add example ADP122/ADP150 power regulator resources Blackfin: bf537-stamp: add example AD2S90 resources Blackfin: bf537-stamp: add example AD5398 power regulator resources ...
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r--arch/blackfin/include/asm/bfin-lq035q1.h12
-rw-r--r--arch/blackfin/include/asm/bfin_can.h725
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h227
-rw-r--r--arch/blackfin/include/asm/bfin_watchdog.h30
-rw-r--r--arch/blackfin/include/asm/bitops.h74
-rw-r--r--arch/blackfin/include/asm/context.S22
-rw-r--r--arch/blackfin/include/asm/cpu.h2
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h58
-rw-r--r--arch/blackfin/include/asm/delay.h16
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h15
-rw-r--r--arch/blackfin/include/asm/dma.h4
-rw-r--r--arch/blackfin/include/asm/dpmc.h4
-rw-r--r--arch/blackfin/include/asm/elf.h8
-rw-r--r--arch/blackfin/include/asm/ftrace.h53
-rw-r--r--arch/blackfin/include/asm/gpio.h17
-rw-r--r--arch/blackfin/include/asm/irq.h7
-rw-r--r--arch/blackfin/include/asm/mmu_context.h14
-rw-r--r--arch/blackfin/include/asm/nmi.h12
-rw-r--r--arch/blackfin/include/asm/page.h3
-rw-r--r--arch/blackfin/include/asm/ptrace.h25
-rw-r--r--arch/blackfin/include/asm/sections.h3
-rw-r--r--arch/blackfin/include/asm/smp.h15
-rw-r--r--arch/blackfin/include/asm/syscall.h96
-rw-r--r--arch/blackfin/include/asm/thread_info.h25
-rw-r--r--arch/blackfin/include/asm/time.h13
25 files changed, 1284 insertions, 196 deletions
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
index 57bc21ac2296..836895156b5b 100644
--- a/arch/blackfin/include/asm/bfin-lq035q1.h
+++ b/arch/blackfin/include/asm/bfin-lq035q1.h
@@ -8,6 +8,9 @@
8#ifndef BFIN_LQ035Q1_H 8#ifndef BFIN_LQ035Q1_H
9#define BFIN_LQ035Q1_H 9#define BFIN_LQ035Q1_H
10 10
11/*
12 * LCD Modes
13 */
11#define LQ035_RL (0 << 8) /* Right -> Left Scan */ 14#define LQ035_RL (0 << 8) /* Right -> Left Scan */
12#define LQ035_LR (1 << 8) /* Left -> Right Scan */ 15#define LQ035_LR (1 << 8) /* Left -> Right Scan */
13#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ 16#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
@@ -17,9 +20,18 @@
17#define LQ035_NORM (1 << 13) /* Reversal */ 20#define LQ035_NORM (1 << 13) /* Reversal */
18#define LQ035_REV (0 << 13) /* Reversal */ 21#define LQ035_REV (0 << 13) /* Reversal */
19 22
23/*
24 * PPI Modes
25 */
26
27#define USE_RGB565_16_BIT_PPI 1
28#define USE_RGB565_8_BIT_PPI 2
29#define USE_RGB888_8_BIT_PPI 3
30
20struct bfin_lq035q1fb_disp_info { 31struct bfin_lq035q1fb_disp_info {
21 32
22 unsigned mode; 33 unsigned mode;
34 unsigned ppi_mode;
23 /* GPIOs */ 35 /* GPIOs */
24 int use_bl; 36 int use_bl;
25 unsigned gpio_bl; 37 unsigned gpio_bl;
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
new file mode 100644
index 000000000000..eec0076a385b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_can.h
@@ -0,0 +1,725 @@
1/*
2 * bfin_can.h - interface to Blackfin CANs
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_CAN_H__
10#define __ASM_BFIN_CAN_H__
11
12/*
13 * transmit and receive channels
14 */
15#define TRANSMIT_CHL 24
16#define RECEIVE_STD_CHL 0
17#define RECEIVE_EXT_CHL 4
18#define RECEIVE_RTR_CHL 8
19#define RECEIVE_EXT_RTR_CHL 12
20#define MAX_CHL_NUMBER 32
21
22/*
23 * All Blackfin system MMRs are padded to 32bits even if the register
24 * itself is only 16bits. So use a helper macro to streamline this.
25 */
26#define __BFP(m) u16 m; u16 __pad_##m
27
28/*
29 * bfin can registers layout
30 */
31struct bfin_can_mask_regs {
32 __BFP(aml);
33 __BFP(amh);
34};
35
36struct bfin_can_channel_regs {
37 u16 data[8];
38 __BFP(dlc);
39 __BFP(tsv);
40 __BFP(id0);
41 __BFP(id1);
42};
43
44struct bfin_can_regs {
45 /*
46 * global control and status registers
47 */
48 __BFP(mc1); /* offset 0x00 */
49 __BFP(md1); /* offset 0x04 */
50 __BFP(trs1); /* offset 0x08 */
51 __BFP(trr1); /* offset 0x0c */
52 __BFP(ta1); /* offset 0x10 */
53 __BFP(aa1); /* offset 0x14 */
54 __BFP(rmp1); /* offset 0x18 */
55 __BFP(rml1); /* offset 0x1c */
56 __BFP(mbtif1); /* offset 0x20 */
57 __BFP(mbrif1); /* offset 0x24 */
58 __BFP(mbim1); /* offset 0x28 */
59 __BFP(rfh1); /* offset 0x2c */
60 __BFP(opss1); /* offset 0x30 */
61 u32 __pad1[3];
62 __BFP(mc2); /* offset 0x40 */
63 __BFP(md2); /* offset 0x44 */
64 __BFP(trs2); /* offset 0x48 */
65 __BFP(trr2); /* offset 0x4c */
66 __BFP(ta2); /* offset 0x50 */
67 __BFP(aa2); /* offset 0x54 */
68 __BFP(rmp2); /* offset 0x58 */
69 __BFP(rml2); /* offset 0x5c */
70 __BFP(mbtif2); /* offset 0x60 */
71 __BFP(mbrif2); /* offset 0x64 */
72 __BFP(mbim2); /* offset 0x68 */
73 __BFP(rfh2); /* offset 0x6c */
74 __BFP(opss2); /* offset 0x70 */
75 u32 __pad2[3];
76 __BFP(clock); /* offset 0x80 */
77 __BFP(timing); /* offset 0x84 */
78 __BFP(debug); /* offset 0x88 */
79 __BFP(status); /* offset 0x8c */
80 __BFP(cec); /* offset 0x90 */
81 __BFP(gis); /* offset 0x94 */
82 __BFP(gim); /* offset 0x98 */
83 __BFP(gif); /* offset 0x9c */
84 __BFP(control); /* offset 0xa0 */
85 __BFP(intr); /* offset 0xa4 */
86 u32 __pad3[1];
87 __BFP(mbtd); /* offset 0xac */
88 __BFP(ewr); /* offset 0xb0 */
89 __BFP(esr); /* offset 0xb4 */
90 u32 __pad4[2];
91 __BFP(ucreg); /* offset 0xc0 */
92 __BFP(uccnt); /* offset 0xc4 */
93 __BFP(ucrc); /* offset 0xc8 */
94 __BFP(uccnf); /* offset 0xcc */
95 u32 __pad5[12];
96
97 /*
98 * channel(mailbox) mask and message registers
99 */
100 struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
101 struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
102};
103
104#undef __BFP
105
106/* CAN_CONTROL Masks */
107#define SRS 0x0001 /* Software Reset */
108#define DNM 0x0002 /* Device Net Mode */
109#define ABO 0x0004 /* Auto-Bus On Enable */
110#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
111#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
112#define SMR 0x0020 /* Sleep Mode Request */
113#define CSR 0x0040 /* CAN Suspend Mode Request */
114#define CCR 0x0080 /* CAN Configuration Mode Request */
115
116/* CAN_STATUS Masks */
117#define WT 0x0001 /* TX Warning Flag */
118#define WR 0x0002 /* RX Warning Flag */
119#define EP 0x0004 /* Error Passive Mode */
120#define EBO 0x0008 /* Error Bus Off Mode */
121#define SMA 0x0020 /* Sleep Mode Acknowledge */
122#define CSA 0x0040 /* Suspend Mode Acknowledge */
123#define CCA 0x0080 /* Configuration Mode Acknowledge */
124#define MBPTR 0x1F00 /* Mailbox Pointer */
125#define TRM 0x4000 /* Transmit Mode */
126#define REC 0x8000 /* Receive Mode */
127
128/* CAN_CLOCK Masks */
129#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
130
131/* CAN_TIMING Masks */
132#define TSEG1 0x000F /* Time Segment 1 */
133#define TSEG2 0x0070 /* Time Segment 2 */
134#define SAM 0x0080 /* Sampling */
135#define SJW 0x0300 /* Synchronization Jump Width */
136
137/* CAN_DEBUG Masks */
138#define DEC 0x0001 /* Disable CAN Error Counters */
139#define DRI 0x0002 /* Disable CAN RX Input */
140#define DTO 0x0004 /* Disable CAN TX Output */
141#define DIL 0x0008 /* Disable CAN Internal Loop */
142#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
143#define MRB 0x0020 /* Mode Read Back Enable */
144#define CDE 0x8000 /* CAN Debug Enable */
145
146/* CAN_CEC Masks */
147#define RXECNT 0x00FF /* Receive Error Counter */
148#define TXECNT 0xFF00 /* Transmit Error Counter */
149
150/* CAN_INTR Masks */
151#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
152#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
153#define GIRQ 0x0004 /* Global Interrupt */
154#define SMACK 0x0008 /* Sleep Mode Acknowledge */
155#define CANTX 0x0040 /* CAN TX Bus Value */
156#define CANRX 0x0080 /* CAN RX Bus Value */
157
158/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
159#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
160#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
161#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
162#define BASEID 0x1FFC /* Base Identifier */
163#define IDE 0x2000 /* Identifier Extension */
164#define RTR 0x4000 /* Remote Frame Transmission Request */
165#define AME 0x8000 /* Acceptance Mask Enable */
166
167/* CAN_MBxx_TIMESTAMP Masks */
168#define TSV 0xFFFF /* Timestamp */
169
170/* CAN_MBxx_LENGTH Masks */
171#define DLC 0x000F /* Data Length Code */
172
173/* CAN_AMxxH and CAN_AMxxL Masks */
174#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
175#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
176#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
177#define BASEID 0x1FFC /* Base Identifier */
178#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
179#define FMD 0x4000 /* Full Mask Data Field Enable */
180#define FDF 0x8000 /* Filter On Data Field Enable */
181
182/* CAN_MC1 Masks */
183#define MC0 0x0001 /* Enable Mailbox 0 */
184#define MC1 0x0002 /* Enable Mailbox 1 */
185#define MC2 0x0004 /* Enable Mailbox 2 */
186#define MC3 0x0008 /* Enable Mailbox 3 */
187#define MC4 0x0010 /* Enable Mailbox 4 */
188#define MC5 0x0020 /* Enable Mailbox 5 */
189#define MC6 0x0040 /* Enable Mailbox 6 */
190#define MC7 0x0080 /* Enable Mailbox 7 */
191#define MC8 0x0100 /* Enable Mailbox 8 */
192#define MC9 0x0200 /* Enable Mailbox 9 */
193#define MC10 0x0400 /* Enable Mailbox 10 */
194#define MC11 0x0800 /* Enable Mailbox 11 */
195#define MC12 0x1000 /* Enable Mailbox 12 */
196#define MC13 0x2000 /* Enable Mailbox 13 */
197#define MC14 0x4000 /* Enable Mailbox 14 */
198#define MC15 0x8000 /* Enable Mailbox 15 */
199
200/* CAN_MC2 Masks */
201#define MC16 0x0001 /* Enable Mailbox 16 */
202#define MC17 0x0002 /* Enable Mailbox 17 */
203#define MC18 0x0004 /* Enable Mailbox 18 */
204#define MC19 0x0008 /* Enable Mailbox 19 */
205#define MC20 0x0010 /* Enable Mailbox 20 */
206#define MC21 0x0020 /* Enable Mailbox 21 */
207#define MC22 0x0040 /* Enable Mailbox 22 */
208#define MC23 0x0080 /* Enable Mailbox 23 */
209#define MC24 0x0100 /* Enable Mailbox 24 */
210#define MC25 0x0200 /* Enable Mailbox 25 */
211#define MC26 0x0400 /* Enable Mailbox 26 */
212#define MC27 0x0800 /* Enable Mailbox 27 */
213#define MC28 0x1000 /* Enable Mailbox 28 */
214#define MC29 0x2000 /* Enable Mailbox 29 */
215#define MC30 0x4000 /* Enable Mailbox 30 */
216#define MC31 0x8000 /* Enable Mailbox 31 */
217
218/* CAN_MD1 Masks */
219#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
220#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
221#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
222#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
223#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
224#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
225#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
226#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
227#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
228#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
229#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
230#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
231#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
232#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
233#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
234#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
235
236/* CAN_MD2 Masks */
237#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
238#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
239#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
240#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
241#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
242#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
243#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
244#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
245#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
246#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
247#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
248#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
249#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
250#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
251#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
252#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
253
254/* CAN_RMP1 Masks */
255#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
256#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
257#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
258#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
259#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
260#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
261#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
262#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
263#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
264#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
265#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
266#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
267#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
268#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
269#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
270#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
271
272/* CAN_RMP2 Masks */
273#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
274#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
275#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
276#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
277#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
278#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
279#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
280#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
281#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
282#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
283#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
284#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
285#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
286#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
287#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
288#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
289
290/* CAN_RML1 Masks */
291#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
292#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
293#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
294#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
295#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
296#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
297#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
298#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
299#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
300#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
301#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
302#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
303#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
304#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
305#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
306#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
307
308/* CAN_RML2 Masks */
309#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
310#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
311#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
312#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
313#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
314#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
315#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
316#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
317#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
318#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
319#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
320#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
321#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
322#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
323#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
324#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
325
326/* CAN_OPSS1 Masks */
327#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
328#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
329#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
330#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
331#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
332#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
333#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
334#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
335#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
336#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
337#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
338#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
339#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
340#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
341#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
342#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
343
344/* CAN_OPSS2 Masks */
345#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
346#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
347#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
348#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
349#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
350#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
351#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
352#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
353#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
354#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
355#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
356#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
357#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
358#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
359#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
360#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
361
362/* CAN_TRR1 Masks */
363#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
364#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
365#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
366#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
367#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
368#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
369#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
370#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
371#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
372#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
373#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
374#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
375#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
376#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
377#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
378#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
379
380/* CAN_TRR2 Masks */
381#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
382#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
383#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
384#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
385#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
386#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
387#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
388#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
389#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
390#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
391#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
392#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
393#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
394#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
395#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
396#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
397
398/* CAN_TRS1 Masks */
399#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
400#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
401#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
402#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
403#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
404#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
405#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
406#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
407#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
408#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
409#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
410#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
411#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
412#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
413#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
414#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
415
416/* CAN_TRS2 Masks */
417#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
418#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
419#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
420#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
421#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
422#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
423#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
424#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
425#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
426#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
427#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
428#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
429#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
430#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
431#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
432#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
433
434/* CAN_AA1 Masks */
435#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
436#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
437#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
438#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
439#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
440#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
441#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
442#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
443#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
444#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
445#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
446#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
447#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
448#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
449#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
450#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
451
452/* CAN_AA2 Masks */
453#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
454#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
455#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
456#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
457#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
458#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
459#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
460#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
461#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
462#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
463#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
464#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
465#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
466#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
467#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
468#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
469
470/* CAN_TA1 Masks */
471#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
472#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
473#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
474#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
475#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
476#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
477#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
478#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
479#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
480#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
481#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
482#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
483#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
484#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
485#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
486#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
487
488/* CAN_TA2 Masks */
489#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
490#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
491#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
492#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
493#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
494#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
495#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
496#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
497#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
498#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
499#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
500#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
501#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
502#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
503#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
504#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
505
506/* CAN_MBTD Masks */
507#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
508#define TDA 0x0040 /* Temporary Disable Acknowledge */
509#define TDR 0x0080 /* Temporary Disable Request */
510
511/* CAN_RFH1 Masks */
512#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
513#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
514#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
515#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
516#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
517#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
518#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
519#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
520#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
521#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
522#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
523#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
524#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
525#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
526#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
527#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
528
529/* CAN_RFH2 Masks */
530#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
531#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
532#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
533#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
534#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
535#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
536#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
537#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
538#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
539#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
540#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
541#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
542#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
543#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
544#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
545#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
546
547/* CAN_MBTIF1 Masks */
548#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
549#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
550#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
551#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
552#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
553#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
554#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
555#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
556#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
557#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
558#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
559#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
560#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
561#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
562#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
563#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
564
565/* CAN_MBTIF2 Masks */
566#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
567#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
568#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
569#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
570#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
571#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
572#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
573#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
574#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
575#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
576#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
577#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
578#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
579#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
580#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
581#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
582
583/* CAN_MBRIF1 Masks */
584#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
585#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
586#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
587#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
588#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
589#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
590#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
591#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
592#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
593#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
594#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
595#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
596#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
597#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
598#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
599#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
600
601/* CAN_MBRIF2 Masks */
602#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
603#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
604#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
605#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
606#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
607#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
608#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
609#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
610#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
611#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
612#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
613#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
614#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
615#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
616#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
617#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
618
619/* CAN_MBIM1 Masks */
620#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
621#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
622#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
623#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
624#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
625#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
626#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
627#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
628#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
629#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
630#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
631#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
632#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
633#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
634#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
635#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
636
637/* CAN_MBIM2 Masks */
638#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
639#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
640#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
641#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
642#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
643#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
644#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
645#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
646#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
647#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
648#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
649#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
650#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
651#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
652#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
653#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
654
655/* CAN_GIM Masks */
656#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
657#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
658#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
659#define BOIM 0x0008 /* Enable Bus Off Interrupt */
660#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
661#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
662#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
663#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
664#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
665#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
666#define ADIM 0x0400 /* Enable Access Denied Interrupt */
667
668/* CAN_GIS Masks */
669#define EWTIS 0x0001 /* TX Error Count IRQ Status */
670#define EWRIS 0x0002 /* RX Error Count IRQ Status */
671#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
672#define BOIS 0x0008 /* Bus Off IRQ Status */
673#define WUIS 0x0010 /* Wake-Up IRQ Status */
674#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
675#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
676#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
677#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
678#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
679#define ADIS 0x0400 /* Access Denied IRQ Status */
680
681/* CAN_GIF Masks */
682#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
683#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
684#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
685#define BOIF 0x0008 /* Bus Off IRQ Flag */
686#define WUIF 0x0010 /* Wake-Up IRQ Flag */
687#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
688#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
689#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
690#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
691#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
692#define ADIF 0x0400 /* Access Denied IRQ Flag */
693
694/* CAN_UCCNF Masks */
695#define UCCNF 0x000F /* Universal Counter Mode */
696#define UC_STAMP 0x0001 /* Timestamp Mode */
697#define UC_WDOG 0x0002 /* Watchdog Mode */
698#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
699#define UC_ERROR 0x0006 /* CAN Error Frame Count */
700#define UC_OVER 0x0007 /* CAN Overload Frame Count */
701#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
702#define UC_AA 0x0009 /* TX Abort Count */
703#define UC_TA 0x000A /* TX Successful Count */
704#define UC_REJECT 0x000B /* RX Message Rejected Count */
705#define UC_RML 0x000C /* RX Message Lost Count */
706#define UC_RX 0x000D /* Total Successful RX Messages Count */
707#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
708#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
709#define UCRC 0x0020 /* Universal Counter Reload/Clear */
710#define UCCT 0x0040 /* Universal Counter CAN Trigger */
711#define UCE 0x0080 /* Universal Counter Enable */
712
713/* CAN_ESR Masks */
714#define ACKE 0x0004 /* Acknowledge Error */
715#define SER 0x0008 /* Stuff Error */
716#define CRCE 0x0010 /* CRC Error */
717#define SA0 0x0020 /* Stuck At Dominant Error */
718#define BEF 0x0040 /* Bit Error Flag */
719#define FER 0x0080 /* Form Error Flag */
720
721/* CAN_EWR Masks */
722#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
723#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
724
725#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index b558908e1c79..9626cf7e4251 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * bfin_sport.h - userspace header for bfin sport driver 2 * bfin_sport.h - interface to Blackfin SPORTs
3 * 3 *
4 * Copyright 2004-2008 Analog Devices Inc. 4 * Copyright 2004-2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -9,16 +9,6 @@
9#ifndef __BFIN_SPORT_H__ 9#ifndef __BFIN_SPORT_H__
10#define __BFIN_SPORT_H__ 10#define __BFIN_SPORT_H__
11 11
12#ifdef __KERNEL__
13#include <linux/cdev.h>
14#include <linux/mutex.h>
15#include <linux/sched.h>
16#include <linux/wait.h>
17#endif
18
19#define SPORT_MAJOR 237
20#define SPORT_NR_DEVS 2
21
22/* Sport mode: it can be set to TDM, i2s or others */ 12/* Sport mode: it can be set to TDM, i2s or others */
23#define NORM_MODE 0x0 13#define NORM_MODE 0x0
24#define TDM_MODE 0x1 14#define TDM_MODE 0x1
@@ -35,7 +25,7 @@ struct sport_config {
35 unsigned int mode:3; 25 unsigned int mode:3;
36 26
37 /* if TDM mode is selected, channels must be set */ 27 /* if TDM mode is selected, channels must be set */
38 int channels; /* Must be in 8 units */ 28 int channels; /* Must be in 8 units */
39 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ 29 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
40 30
41 /* I2S mode */ 31 /* I2S mode */
@@ -69,94 +59,137 @@ struct sport_config {
69 59
70#ifdef __KERNEL__ 60#ifdef __KERNEL__
71 61
72struct sport_register { 62#include <linux/types.h>
73 unsigned short tcr1;
74 unsigned short reserved0;
75 unsigned short tcr2;
76 unsigned short reserved1;
77 unsigned short tclkdiv;
78 unsigned short reserved2;
79 unsigned short tfsdiv;
80 unsigned short reserved3;
81 unsigned long tx;
82 unsigned long reserved_l0;
83 unsigned long rx;
84 unsigned long reserved_l1;
85 unsigned short rcr1;
86 unsigned short reserved4;
87 unsigned short rcr2;
88 unsigned short reserved5;
89 unsigned short rclkdiv;
90 unsigned short reserved6;
91 unsigned short rfsdiv;
92 unsigned short reserved7;
93 unsigned short stat;
94 unsigned short reserved8;
95 unsigned short chnl;
96 unsigned short reserved9;
97 unsigned short mcmc1;
98 unsigned short reserved10;
99 unsigned short mcmc2;
100 unsigned short reserved11;
101 unsigned long mtcs0;
102 unsigned long mtcs1;
103 unsigned long mtcs2;
104 unsigned long mtcs3;
105 unsigned long mrcs0;
106 unsigned long mrcs1;
107 unsigned long mrcs2;
108 unsigned long mrcs3;
109};
110
111struct sport_dev {
112 struct cdev cdev; /* Char device structure */
113
114 int sport_num;
115 63
116 int dma_rx_chan; 64/*
117 int dma_tx_chan; 65 * All Blackfin system MMRs are padded to 32bits even if the register
118 66 * itself is only 16bits. So use a helper macro to streamline this.
119 int rx_irq; 67 */
120 unsigned char *rx_buf; /* Buffer store the received data */ 68#define __BFP(m) u16 m; u16 __pad_##m
121 int rx_len; /* How many bytes will be received */ 69struct sport_register {
122 int rx_received; /* How many bytes has been received */ 70 __BFP(tcr1);
123 71 __BFP(tcr2);
124 int tx_irq; 72 __BFP(tclkdiv);
125 const unsigned char *tx_buf; 73 __BFP(tfsdiv);
126 int tx_len; 74 union {
127 int tx_sent; 75 u32 tx32;
128 76 u16 tx16;
129 int err_irq; 77 };
130 78 u32 __pad_tx;
131 struct mutex mutex; /* mutual exclusion semaphore */ 79 union {
132 struct task_struct *task; 80 u32 rx32; /* use the anomaly wrapper below */
133 81 u16 rx16;
134 wait_queue_head_t waitq; 82 };
135 int wait_con; 83 u32 __pad_rx;
136 struct sport_register *regs; 84 __BFP(rcr1);
137 struct sport_config config; 85 __BFP(rcr2);
86 __BFP(rclkdiv);
87 __BFP(rfsdiv);
88 __BFP(stat);
89 __BFP(chnl);
90 __BFP(mcmc1);
91 __BFP(mcmc2);
92 u32 mtcs0;
93 u32 mtcs1;
94 u32 mtcs2;
95 u32 mtcs3;
96 u32 mrcs0;
97 u32 mrcs1;
98 u32 mrcs2;
99 u32 mrcs3;
138}; 100};
101#undef __BFP
102
103#define bfin_read_sport_rx32(base) \
104({ \
105 struct sport_register *__mmrs = (void *)base; \
106 u32 __ret; \
107 unsigned long flags; \
108 if (ANOMALY_05000473) \
109 local_irq_save(flags); \
110 __ret = __mmrs->rx32; \
111 if (ANOMALY_05000473) \
112 local_irq_restore(flags); \
113 __ret; \
114})
139 115
140#endif 116#endif
141 117
142#define SPORT_TCR1 0 118/* Workaround defBF*.h SPORT MMRs till they get cleansed */
143#define SPORT_TCR2 1 119#undef DTYPE_NORM
144#define SPORT_TCLKDIV 2 120#undef SLEN
145#define SPORT_TFSDIV 3 121#undef SP_WOFF
146#define SPORT_RCR1 8 122#undef SP_WSIZE
147#define SPORT_RCR2 9 123
148#define SPORT_RCLKDIV 10 124/* SPORT_TCR1 Masks */
149#define SPORT_RFSDIV 11 125#define TSPEN 0x0001 /* TX enable */
150#define SPORT_CHANNEL 13 126#define ITCLK 0x0002 /* Internal TX Clock Select */
151#define SPORT_MCMC1 14 127#define TDTYPE 0x000C /* TX Data Formatting Select */
152#define SPORT_MCMC2 15 128#define DTYPE_NORM 0x0000 /* Data Format Normal */
153#define SPORT_MTCS0 16 129#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
154#define SPORT_MTCS1 17 130#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
155#define SPORT_MTCS2 18 131#define TLSBIT 0x0010 /* TX Bit Order */
156#define SPORT_MTCS3 19 132#define ITFS 0x0200 /* Internal TX Frame Sync Select */
157#define SPORT_MRCS0 20 133#define TFSR 0x0400 /* TX Frame Sync Required Select */
158#define SPORT_MRCS1 21 134#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
159#define SPORT_MRCS2 22 135#define LTFS 0x1000 /* Low TX Frame Sync Select */
160#define SPORT_MRCS3 23 136#define LATFS 0x2000 /* Late TX Frame Sync Select */
137#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
138
139/* SPORT_TCR2 Masks */
140#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
141#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
142#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
143#define TXSE 0x0100 /* TX Secondary Enable */
144#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
145#define TRFST 0x0400 /* TX Right-First Data Order */
146
147/* SPORT_RCR1 Masks */
148#define RSPEN 0x0001 /* RX enable */
149#define IRCLK 0x0002 /* Internal RX Clock Select */
150#define RDTYPE 0x000C /* RX Data Formatting Select */
151/* DTYPE_* defined above */
152#define RLSBIT 0x0010 /* RX Bit Order */
153#define IRFS 0x0200 /* Internal RX Frame Sync Select */
154#define RFSR 0x0400 /* RX Frame Sync Required Select */
155#define LRFS 0x1000 /* Low RX Frame Sync Select */
156#define LARFS 0x2000 /* Late RX Frame Sync Select */
157#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
158
159/* SPORT_RCR2 Masks */
160/* SLEN defined above */
161#define RXSE 0x0100 /* RX Secondary Enable */
162#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
163#define RRFST 0x0400 /* Right-First Data Order */
164
165/* SPORT_STAT Masks */
166#define RXNE 0x0001 /* RX FIFO Not Empty Status */
167#define RUVF 0x0002 /* RX Underflow Status */
168#define ROVF 0x0004 /* RX Overflow Status */
169#define TXF 0x0008 /* TX FIFO Full Status */
170#define TUVF 0x0010 /* TX Underflow Status */
171#define TOVF 0x0020 /* TX Overflow Status */
172#define TXHRE 0x0040 /* TX Hold Register Empty */
173
174/* SPORT_MCMC1 Masks */
175#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
176#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
177#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
178#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
179#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
180#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
181
182/* SPORT_MCMC2 Masks */
183#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
184#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
185#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
186#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
187#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
188#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
189#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
190#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
191#define MFD 0xF000 /* Multichannel Frame Delay */
192#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
193#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
161 194
162#endif 195#endif
diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h
new file mode 100644
index 000000000000..dce09829a095
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_watchdog.h
@@ -0,0 +1,30 @@
1/*
2 * bfin_watchdog.h - Blackfin watchdog definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _BFIN_WATCHDOG_H
10#define _BFIN_WATCHDOG_H
11
12/* Bit in SWRST that indicates boot caused by watchdog */
13#define SWRST_RESET_WDOG 0x4000
14
15/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
16#define WDOG_EXPIRED 0x8000
17
18/* Masks for WDEV field in WDOG_CTL register */
19#define ICTL_RESET 0x0
20#define ICTL_NMI 0x2
21#define ICTL_GPI 0x4
22#define ICTL_NONE 0x6
23#define ICTL_MASK 0x6
24
25/* Masks for WDEN field in WDOG_CTL register */
26#define WDEN_MASK 0x0FF0
27#define WDEN_ENABLE 0x0000
28#define WDEN_DISABLE 0x0AD0
29
30#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index a2ff3fb3568d..605ba8e9b2e4 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -7,22 +7,41 @@
7#ifndef _BLACKFIN_BITOPS_H 7#ifndef _BLACKFIN_BITOPS_H
8#define _BLACKFIN_BITOPS_H 8#define _BLACKFIN_BITOPS_H
9 9
10#ifndef CONFIG_SMP 10#include <linux/compiler.h>
11# include <asm-generic/bitops.h> 11
12#else 12#include <asm-generic/bitops/__ffs.h>
13#include <asm-generic/bitops/ffz.h>
14#include <asm-generic/bitops/fls.h>
15#include <asm-generic/bitops/__fls.h>
16#include <asm-generic/bitops/fls64.h>
17#include <asm-generic/bitops/find.h>
13 18
14#ifndef _LINUX_BITOPS_H 19#ifndef _LINUX_BITOPS_H
15#error only <linux/bitops.h> can be included directly 20#error only <linux/bitops.h> can be included directly
16#endif 21#endif
17 22
18#include <linux/compiler.h>
19#include <asm/byteorder.h> /* swab32 */
20
21#include <asm-generic/bitops/ffs.h>
22#include <asm-generic/bitops/__ffs.h>
23#include <asm-generic/bitops/sched.h> 23#include <asm-generic/bitops/sched.h>
24#include <asm-generic/bitops/ffz.h> 24#include <asm-generic/bitops/ffs.h>
25#include <asm-generic/bitops/lock.h>
26#include <asm-generic/bitops/ext2-non-atomic.h>
27#include <asm-generic/bitops/ext2-atomic.h>
28#include <asm-generic/bitops/minix.h>
29
30#ifndef CONFIG_SMP
31#include <linux/irqflags.h>
32
33/*
34 * clear_bit may not imply a memory barrier
35 */
36#ifndef smp_mb__before_clear_bit
37#define smp_mb__before_clear_bit() smp_mb()
38#define smp_mb__after_clear_bit() smp_mb()
39#endif
40#include <asm-generic/bitops/atomic.h>
41#include <asm-generic/bitops/non-atomic.h>
42#else
25 43
44#include <asm/byteorder.h> /* swab32 */
26#include <linux/linkage.h> 45#include <linux/linkage.h>
27 46
28asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); 47asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
@@ -89,19 +108,36 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
89 108
90#include <asm-generic/bitops/non-atomic.h> 109#include <asm-generic/bitops/non-atomic.h>
91 110
92#include <asm-generic/bitops/find.h> 111#endif /* CONFIG_SMP */
93#include <asm-generic/bitops/hweight.h>
94#include <asm-generic/bitops/lock.h>
95 112
96#include <asm-generic/bitops/ext2-atomic.h> 113/*
97#include <asm-generic/bitops/ext2-non-atomic.h> 114 * hweightN: returns the hamming weight (i.e. the number
115 * of bits set) of a N-bit word
116 */
98 117
99#include <asm-generic/bitops/minix.h> 118static inline unsigned int hweight32(unsigned int w)
119{
120 unsigned int res;
100 121
101#include <asm-generic/bitops/fls.h> 122 __asm__ ("%0.l = ONES %0;"
102#include <asm-generic/bitops/__fls.h> 123 "%0 = %0.l (Z);"
103#include <asm-generic/bitops/fls64.h> 124 : "=d" (res) : "d" (w));
125 return res;
126}
104 127
105#endif /* CONFIG_SMP */ 128static inline unsigned int hweight64(__u64 w)
129{
130 return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w);
131}
132
133static inline unsigned int hweight16(unsigned int w)
134{
135 return hweight32(w & 0xffff);
136}
137
138static inline unsigned int hweight8(unsigned int w)
139{
140 return hweight32(w & 0xff);
141}
106 142
107#endif /* _BLACKFIN_BITOPS_H */ 143#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 5dffaf582a22..1f9060395a0a 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -73,6 +73,11 @@
73#else 73#else
74 cli r0; 74 cli r0;
75#endif 75#endif
76#ifdef CONFIG_TRACE_IRQFLAGS
77 sp += -12;
78 call _trace_hardirqs_off;
79 sp += 12;
80#endif
76 [--sp] = RETI; /*orig_pc*/ 81 [--sp] = RETI; /*orig_pc*/
77 /* Clear all L registers. */ 82 /* Clear all L registers. */
78 r0 = 0 (x); 83 r0 = 0 (x);
@@ -279,6 +284,13 @@
279 RETN = [sp++]; 284 RETN = [sp++];
280 RETX = [sp++]; 285 RETX = [sp++];
281 RETI = [sp++]; 286 RETI = [sp++];
287
288#ifdef CONFIG_TRACE_IRQFLAGS
289 sp += -12;
290 call _trace_hardirqs_on;
291 sp += 12;
292#endif
293
282 RETS = [sp++]; 294 RETS = [sp++];
283 295
284#ifdef CONFIG_SMP 296#ifdef CONFIG_SMP
@@ -374,3 +386,13 @@
374 386
375 (R7:0, P5:0) = [SP++]; 387 (R7:0, P5:0) = [SP++];
376.endm 388.endm
389
390.macro pseudo_long_call func:req, scratch:req
391#ifdef CONFIG_ROMKERNEL
392 \scratch\().l = \func;
393 \scratch\().h = \func;
394 call (\scratch);
395#else
396 call \func;
397#endif
398.endm
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index b191dc662bd8..16883e582e3c 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -17,8 +17,6 @@ struct blackfin_cpudata {
17 struct task_struct *idle; 17 struct task_struct *idle;
18 unsigned int imemctl; 18 unsigned int imemctl;
19 unsigned int dmemctl; 19 unsigned int dmemctl;
20 unsigned long dcache_invld_count;
21 unsigned long icache_invld_count;
22}; 20};
23 21
24DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); 22DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 25906468622f..f342ff0319df 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -12,6 +12,8 @@
12#include <mach/anomaly.h> 12#include <mach/anomaly.h>
13 13
14#define MK_BMSK_(x) (1<<x) 14#define MK_BMSK_(x) (1<<x)
15#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
16#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
15 17
16#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
17 19
@@ -23,62 +25,30 @@
23# define NOP_PAD_ANOMALY_05000198 25# define NOP_PAD_ANOMALY_05000198
24#endif 26#endif
25 27
26#define bfin_read8(addr) ({ \ 28#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
27 uint32_t __v; \ 29 u32 __v; \
28 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
29 NOP_PAD_ANOMALY_05000198 \ 31 NOP_PAD_ANOMALY_05000198 \
30 "%0 = b[%1] (z);" \ 32 "%0 = " #asm_size "[%1]" #asm_ext ";" \
31 : "=d" (__v) \ 33 : "=d" (__v) \
32 : "a" (addr) \ 34 : "a" (addr) \
33 ); \ 35 ); \
34 __v; }) 36 __v; })
35 37#define _bfin_writeX(addr, val, size, asm_size) \
36#define bfin_read16(addr) ({ \
37 uint32_t __v; \
38 __asm__ __volatile__( \
39 NOP_PAD_ANOMALY_05000198 \
40 "%0 = w[%1] (z);" \
41 : "=d" (__v) \
42 : "a" (addr) \
43 ); \
44 __v; })
45
46#define bfin_read32(addr) ({ \
47 uint32_t __v; \
48 __asm__ __volatile__( \
49 NOP_PAD_ANOMALY_05000198 \
50 "%0 = [%1];" \
51 : "=d" (__v) \
52 : "a" (addr) \
53 ); \
54 __v; })
55
56#define bfin_write8(addr, val) \
57 __asm__ __volatile__( \ 38 __asm__ __volatile__( \
58 NOP_PAD_ANOMALY_05000198 \ 39 NOP_PAD_ANOMALY_05000198 \
59 "b[%0] = %1;" \ 40 #asm_size "[%0] = %1;" \
60 : \ 41 : \
61 : "a" (addr), "d" ((uint8_t)(val)) \ 42 : "a" (addr), "d" ((u##size)(val)) \
62 : "memory" \ 43 : "memory" \
63 ) 44 )
64 45
65#define bfin_write16(addr, val) \ 46#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
66 __asm__ __volatile__( \ 47#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
67 NOP_PAD_ANOMALY_05000198 \ 48#define bfin_read32(addr) _bfin_readX(addr, 32, , )
68 "w[%0] = %1;" \ 49#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
69 : \ 50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
70 : "a" (addr), "d" ((uint16_t)(val)) \ 51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
71 : "memory" \
72 )
73
74#define bfin_write32(addr, val) \
75 __asm__ __volatile__( \
76 NOP_PAD_ANOMALY_05000198 \
77 "[%0] = %1;" \
78 : \
79 : "a" (addr), "d" (val) \
80 : "memory" \
81 )
82 52
83#endif /* __ASSEMBLY__ */ 53#endif /* __ASSEMBLY__ */
84 54
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
index c31f91cc1d5d..171d8deb04a5 100644
--- a/arch/blackfin/include/asm/delay.h
+++ b/arch/blackfin/include/asm/delay.h
@@ -30,10 +30,22 @@ __asm__ __volatile__ (
30 30
31#define HZSCALE (268435456 / (1000000/HZ)) 31#define HZSCALE (268435456 / (1000000/HZ))
32 32
33static inline void udelay(unsigned long usecs) 33static inline unsigned long __to_delay(unsigned long scale)
34{ 34{
35 extern unsigned long loops_per_jiffy; 35 extern unsigned long loops_per_jiffy;
36 __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6); 36 return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
37}
38
39static inline void udelay(unsigned long usecs)
40{
41 __delay(__to_delay(usecs));
37} 42}
38 43
44static inline void ndelay(unsigned long nsecs)
45{
46 __delay(__to_delay(1) * nsecs / 1000);
47}
48
49#define ndelay ndelay
50
39#endif 51#endif
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 413a30314a6f..212cb80fd74b 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -44,13 +44,8 @@ dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
44extern void 44extern void
45__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir); 45__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
46static inline void 46static inline void
47_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) 47__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
48{ 48{
49 if (!__builtin_constant_p(dir)) {
50 __dma_sync(addr, size, dir);
51 return;
52 }
53
54 switch (dir) { 49 switch (dir) {
55 case DMA_NONE: 50 case DMA_NONE:
56 BUG(); 51 BUG();
@@ -64,6 +59,14 @@ _dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
64 break; 59 break;
65 } 60 }
66} 61}
62static inline void
63_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
64{
65 if (__builtin_constant_p(dir))
66 __dma_sync_inline(addr, size, dir);
67 else
68 __dma_sync(addr, size, dir);
69}
67 70
68static inline dma_addr_t 71static inline dma_addr_t
69dma_map_single(struct device *dev, void *ptr, size_t size, 72dma_map_single(struct device *dev, void *ptr, size_t size,
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index bd2e62243abe..2c09b1d50ec9 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -262,6 +262,10 @@ static inline void dma_disable_irq(unsigned int channel)
262{ 262{
263 disable_irq(dma_ch[channel].irq); 263 disable_irq(dma_ch[channel].irq);
264} 264}
265static inline void dma_disable_irq_nosync(unsigned int channel)
266{
267 disable_irq_nosync(dma_ch[channel].irq);
268}
265static inline void dma_enable_irq(unsigned int channel) 269static inline void dma_enable_irq(unsigned int channel)
266{ 270{
267 enable_irq(dma_ch[channel].irq); 271 enable_irq(dma_ch[channel].irq);
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 1597ae5041ee..efcc3aebeae4 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -75,7 +75,7 @@
75 75
76#define VLEV 0x00F0 /* Internal Voltage Level */ 76#define VLEV 0x00F0 /* Internal Voltage Level */
77#ifdef __ADSPBF52x__ 77#ifdef __ADSPBF52x__
78#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 78#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
79#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 79#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
80#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 80#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
81#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 81#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
@@ -84,7 +84,7 @@
84#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 84#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
85#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 85#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
86#else 86#else
87#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 87#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
88#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 88#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
89#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 89#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
90#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 90#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 5b50f0ecacf8..117713adea7f 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -22,12 +22,15 @@
22#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */ 22#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
23#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */ 23#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
24 24
25#if 1 /* core dumps not supported, but linux/elfcore.h needs these */
25typedef unsigned long elf_greg_t; 26typedef unsigned long elf_greg_t;
26 27
27#define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */ 28#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
28typedef elf_greg_t elf_gregset_t[ELF_NGREG]; 29typedef elf_greg_t elf_gregset_t[ELF_NGREG];
29 30
30typedef struct { } elf_fpregset_t; 31typedef struct { } elf_fpregset_t;
32#endif
33
31/* 34/*
32 * This is used to ensure we don't load something for the wrong architecture. 35 * This is used to ensure we don't load something for the wrong architecture.
33 */ 36 */
@@ -55,6 +58,9 @@ do { \
55 _regs->p2 = _dynamic_addr; \ 58 _regs->p2 = _dynamic_addr; \
56} while(0) 59} while(0)
57 60
61#if 0
62#define CORE_DUMP_USE_REGSET
63#endif
58#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC 64#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
59#define ELF_EXEC_PAGESIZE 4096 65#define ELF_EXEC_PAGESIZE 4096
60 66
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 90c9b400ba6d..4cfe2d9ba7e8 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -10,4 +10,57 @@
10 10
11#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */ 11#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */
12 12
13#ifndef __ASSEMBLY__
14
15#ifdef CONFIG_FRAME_POINTER
16#include <linux/mm.h>
17
18extern inline void *return_address(unsigned int level)
19{
20 unsigned long *endstack, *fp, *ret_addr;
21 unsigned int current_level = 0;
22
23 if (level == 0)
24 return __builtin_return_address(0);
25
26 fp = (unsigned long *)__builtin_frame_address(0);
27 endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
28
29 while (((unsigned long)fp & 0x3) == 0 && fp &&
30 (fp + 1) < endstack && current_level < level) {
31 fp = (unsigned long *)*fp;
32 current_level++;
33 }
34
35 if (((unsigned long)fp & 0x3) == 0 && fp &&
36 (fp + 1) < endstack)
37 ret_addr = (unsigned long *)*(fp + 1);
38 else
39 ret_addr = NULL;
40
41 return ret_addr;
42}
43
44#else
45
46extern inline void *return_address(unsigned int level)
47{
48 return NULL;
49}
50
51#endif /* CONFIG_FRAME_POINTER */
52
53#define HAVE_ARCH_CALLER_ADDR
54
55/* inline function or macro may lead to unexpected result */
56#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
57#define CALLER_ADDR1 ((unsigned long)return_address(1))
58#define CALLER_ADDR2 ((unsigned long)return_address(2))
59#define CALLER_ADDR3 ((unsigned long)return_address(3))
60#define CALLER_ADDR4 ((unsigned long)return_address(4))
61#define CALLER_ADDR5 ((unsigned long)return_address(5))
62#define CALLER_ADDR6 ((unsigned long)return_address(6))
63
64#endif /* __ASSEMBLY__ */
65
13#endif 66#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 539468a05057..91bd2d7b9d55 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -70,6 +70,8 @@
70 70
71#ifndef __ASSEMBLY__ 71#ifndef __ASSEMBLY__
72 72
73#include <linux/compiler.h>
74
73/*********************************************************** 75/***********************************************************
74* 76*
75* FUNCTIONS: Blackfin General Purpose Ports Access Functions 77* FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -223,6 +225,9 @@ int bfin_gpio_direction_output(unsigned gpio, int value);
223int bfin_gpio_get_value(unsigned gpio); 225int bfin_gpio_get_value(unsigned gpio);
224void bfin_gpio_set_value(unsigned gpio, int value); 226void bfin_gpio_set_value(unsigned gpio, int value);
225 227
228#include <asm/irq.h>
229#include <asm/errno.h>
230
226#ifdef CONFIG_GPIOLIB 231#ifdef CONFIG_GPIOLIB
227#include <asm-generic/gpio.h> /* cansleep wrappers */ 232#include <asm-generic/gpio.h> /* cansleep wrappers */
228 233
@@ -247,6 +252,11 @@ static inline int gpio_cansleep(unsigned int gpio)
247 return __gpio_cansleep(gpio); 252 return __gpio_cansleep(gpio);
248} 253}
249 254
255static inline int gpio_to_irq(unsigned gpio)
256{
257 return __gpio_to_irq(gpio);
258}
259
250#else /* !CONFIG_GPIOLIB */ 260#else /* !CONFIG_GPIOLIB */
251 261
252static inline int gpio_request(unsigned gpio, const char *label) 262static inline int gpio_request(unsigned gpio, const char *label)
@@ -279,10 +289,6 @@ static inline void gpio_set_value(unsigned gpio, int value)
279 return bfin_gpio_set_value(gpio, value); 289 return bfin_gpio_set_value(gpio, value);
280} 290}
281 291
282#include <asm-generic/gpio.h> /* cansleep wrappers */
283#endif /* !CONFIG_GPIOLIB */
284#include <asm/irq.h>
285
286static inline int gpio_to_irq(unsigned gpio) 292static inline int gpio_to_irq(unsigned gpio)
287{ 293{
288 if (likely(gpio < MAX_BLACKFIN_GPIOS)) 294 if (likely(gpio < MAX_BLACKFIN_GPIOS))
@@ -291,6 +297,9 @@ static inline int gpio_to_irq(unsigned gpio)
291 return -EINVAL; 297 return -EINVAL;
292} 298}
293 299
300#include <asm-generic/gpio.h> /* cansleep wrappers */
301#endif /* !CONFIG_GPIOLIB */
302
294static inline int irq_to_gpio(unsigned irq) 303static inline int irq_to_gpio(unsigned irq)
295{ 304{
296 return (irq - GPIO_IRQ_BASE); 305 return (irq - GPIO_IRQ_BASE);
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index e7c0623f9091..12f4060a31b0 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -12,6 +12,9 @@
12 12
13#include <linux/irqflags.h> 13#include <linux/irqflags.h>
14 14
15/* IRQs that may be used by external irq_chip controllers */
16#define NR_SPARE_IRQS 32
17
15#include <mach/anomaly.h> 18#include <mach/anomaly.h>
16 19
17/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ 20/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
@@ -35,4 +38,8 @@
35 38
36#include <asm-generic/irq.h> 39#include <asm-generic/irq.h>
37 40
41#ifdef CONFIG_NMI_WATCHDOG
42# define ARCH_HAS_NMI_WATCHDOG
43#endif
44
38#endif /* _BFIN_IRQ_H_ */ 45#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index ae8ef4ffd806..7f363d7e43a5 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -13,6 +13,7 @@
13#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/pgalloc.h> 14#include <asm/pgalloc.h>
15#include <asm/cplbinit.h> 15#include <asm/cplbinit.h>
16#include <asm/sections.h>
16 17
17/* Note: L1 stacks are CPU-private things, so we bluntly disable this 18/* Note: L1 stacks are CPU-private things, so we bluntly disable this
18 feature in SMP mode, and use the per-CPU scratch SRAM bank only to 19 feature in SMP mode, and use the per-CPU scratch SRAM bank only to
@@ -117,9 +118,16 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr,
117 unsigned long flags) 118 unsigned long flags)
118{ 119{
119 unsigned long *mask = mm->context.page_rwx_mask; 120 unsigned long *mask = mm->context.page_rwx_mask;
120 unsigned long page = addr >> 12; 121 unsigned long page;
121 unsigned long idx = page >> 5; 122 unsigned long idx;
122 unsigned long bit = 1 << (page & 31); 123 unsigned long bit;
124
125 if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
126 page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
127 else
128 page = addr >> 12;
129 idx = page >> 5;
130 bit = 1 << (page & 31);
123 131
124 if (flags & VM_READ) 132 if (flags & VM_READ)
125 mask[idx] |= bit; 133 mask[idx] |= bit;
diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h
new file mode 100644
index 000000000000..b9caac4fcfd8
--- /dev/null
+++ b/arch/blackfin/include/asm/nmi.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright 2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2
5 */
6
7#ifndef _BFIN_NMI_H_
8#define _BFIN_NMI_H_
9
10#include <linux/nmi.h>
11
12#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index 1d04e4078340..d0ce975bcd48 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -15,4 +15,7 @@
15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ 15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
17 17
18#include <asm-generic/memory_model.h>
19#include <asm-generic/getorder.h>
20
18#endif 21#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index b33a4488f498..aaa1c6c2bc19 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -24,6 +24,8 @@
24 24
25#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
26 26
27struct task_struct;
28
27/* this struct defines the way the registers are stored on the 29/* this struct defines the way the registers are stored on the
28 stack during a system call. */ 30 stack during a system call. */
29 31
@@ -101,9 +103,30 @@ struct pt_regs {
101 master interrupt enable. */ 103 master interrupt enable. */
102#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) 104#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
103#define instruction_pointer(regs) ((regs)->pc) 105#define instruction_pointer(regs) ((regs)->pc)
106#define user_stack_pointer(regs) ((regs)->usp)
104#define profile_pc(regs) instruction_pointer(regs) 107#define profile_pc(regs) instruction_pointer(regs)
105extern void show_regs(struct pt_regs *); 108extern void show_regs(struct pt_regs *);
106 109
110#define arch_has_single_step() (1)
111extern void user_enable_single_step(struct task_struct *child);
112extern void user_disable_single_step(struct task_struct *child);
113/* common code demands this function */
114#define ptrace_disable(child) user_disable_single_step(child)
115
116/*
117 * Get the address of the live pt_regs for the specified task.
118 * These are saved onto the top kernel stack when the process
119 * is not running.
120 *
121 * Note: if a user thread is execve'd from kernel space, the
122 * kernel stack will not be empty on entry to the kernel, so
123 * ptracing these tasks will fail.
124 */
125#define task_pt_regs(task) \
126 (struct pt_regs *) \
127 ((unsigned long)task_stack_page(task) + \
128 (THREAD_SIZE - sizeof(struct pt_regs)))
129
107#endif /* __KERNEL__ */ 130#endif /* __KERNEL__ */
108 131
109#endif /* __ASSEMBLY__ */ 132#endif /* __ASSEMBLY__ */
@@ -173,4 +196,6 @@ extern void show_regs(struct pt_regs *);
173#define PT_FDPIC_EXEC 232 196#define PT_FDPIC_EXEC 232
174#define PT_FDPIC_INTERP 236 197#define PT_FDPIC_INTERP 236
175 198
199#define PT_LAST_PSEUDO PT_FDPIC_INTERP
200
176#endif /* _BFIN_PTRACE_H */ 201#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 42f6c53c59c6..14a3e66d9167 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -21,6 +21,9 @@ extern unsigned long memory_start, memory_end, physical_mem_end;
21extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[]; 21extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
22extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[], 22extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
23 _data_l1_lma[], __weak _data_l1_len[]; 23 _data_l1_lma[], __weak _data_l1_len[];
24#ifdef CONFIG_ROMKERNEL
25extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
26#endif
24extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], 27extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
25 _data_b_l1_lma[], __weak _data_b_l1_len[]; 28 _data_b_l1_lma[], __weak _data_b_l1_len[];
26extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], 29extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index 6a0fe94b84a6..f5b537967116 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -22,8 +22,23 @@ extern char coreb_trampoline_start, coreb_trampoline_end;
22struct corelock_slot { 22struct corelock_slot {
23 int lock; 23 int lock;
24}; 24};
25extern struct corelock_slot corelock;
26
27#ifdef __ARCH_SYNC_CORE_ICACHE
28extern unsigned long icache_invld_count[NR_CPUS];
29#endif
30#ifdef __ARCH_SYNC_CORE_DCACHE
31extern unsigned long dcache_invld_count[NR_CPUS];
32#endif
25 33
26void smp_icache_flush_range_others(unsigned long start, 34void smp_icache_flush_range_others(unsigned long start,
27 unsigned long end); 35 unsigned long end);
36#ifdef CONFIG_HOTPLUG_CPU
37void coreb_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
38void cpu_die(void);
39void platform_cpu_die(void);
40int __cpu_disable(void);
41int __cpu_die(unsigned int cpu);
42#endif
28 43
29#endif /* !__ASM_BLACKFIN_SMP_H */ 44#endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h
new file mode 100644
index 000000000000..4921a4815cce
--- /dev/null
+++ b/arch/blackfin/include/asm/syscall.h
@@ -0,0 +1,96 @@
1/*
2 * Magic syscall break down functions
3 *
4 * Copyright 2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BLACKFIN_SYSCALL_H__
10#define __ASM_BLACKFIN_SYSCALL_H__
11
12/*
13 * Blackfin syscalls are simple:
14 * enter:
15 * p0: syscall number
16 * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
17 * exit:
18 * r0: return/error value
19 */
20
21#include <linux/err.h>
22#include <linux/sched.h>
23#include <asm/ptrace.h>
24
25static inline long
26syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
27{
28 return regs->p0;
29}
30
31static inline void
32syscall_rollback(struct task_struct *task, struct pt_regs *regs)
33{
34 regs->p0 = regs->orig_p0;
35}
36
37static inline long
38syscall_get_error(struct task_struct *task, struct pt_regs *regs)
39{
40 return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
41}
42
43static inline long
44syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
45{
46 return regs->r0;
47}
48
49static inline void
50syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
51 int error, long val)
52{
53 regs->r0 = error ? -error : val;
54}
55
56/**
57 * syscall_get_arguments()
58 * @task: unused
59 * @regs: the register layout to extract syscall arguments from
60 * @i: first syscall argument to extract
61 * @n: number of syscall arguments to extract
62 * @args: array to return the syscall arguments in
63 *
64 * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
65 */
66static inline void
67syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
68 unsigned int i, unsigned int n, unsigned long *args)
69{
70 /*
71 * Assume the ptrace layout doesn't change -- r5 is first in memory,
72 * then r4, ..., then r0. So we simply reverse the ptrace register
73 * array in memory to store into the args array.
74 */
75 long *aregs = &regs->r0 - i;
76
77 BUG_ON(i > 5 || i + n > 6);
78
79 while (n--)
80 *args++ = *aregs--;
81}
82
83/* See syscall_get_arguments() comments */
84static inline void
85syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
86 unsigned int i, unsigned int n, const unsigned long *args)
87{
88 long *aregs = &regs->r0 - i;
89
90 BUG_ON(i > 5 || i + n > 6);
91
92 while (n--)
93 *aregs-- = *args++;
94}
95
96#endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index a40d9368c38a..e9a5614cdbb1 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -17,7 +17,7 @@
17/* Thread Align Mask to reach to the top of the stack 17/* Thread Align Mask to reach to the top of the stack
18 * for any process 18 * for any process
19 */ 19 */
20#define ALIGN_PAGE_MASK 0xffffe000 20#define ALIGN_PAGE_MASK 0xffffe000
21 21
22/* 22/*
23 * Size of kernel stack for each process. This must be a power of 2... 23 * Size of kernel stack for each process. This must be a power of 2...
@@ -57,7 +57,7 @@ struct thread_info {
57 .exec_domain = &default_exec_domain, \ 57 .exec_domain = &default_exec_domain, \
58 .flags = 0, \ 58 .flags = 0, \
59 .cpu = 0, \ 59 .cpu = 0, \
60 .preempt_count = INIT_PREEMPT_COUNT, \ 60 .preempt_count = INIT_PREEMPT_COUNT, \
61 .restart_block = { \ 61 .restart_block = { \
62 .fn = do_no_restart_syscall, \ 62 .fn = do_no_restart_syscall, \
63 }, \ 63 }, \
@@ -73,8 +73,7 @@ __attribute_const__
73static inline struct thread_info *current_thread_info(void) 73static inline struct thread_info *current_thread_info(void)
74{ 74{
75 struct thread_info *ti; 75 struct thread_info *ti;
76 __asm__("%0 = sp;" : "=da"(ti) : 76 __asm__("%0 = sp;" : "=da"(ti));
77 );
78 return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); 77 return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
79} 78}
80 79
@@ -99,21 +98,23 @@ static inline struct thread_info *current_thread_info(void)
99#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ 98#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
100#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling 99#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
101 TIF_NEED_RESCHED */ 100 TIF_NEED_RESCHED */
102#define TIF_MEMDIE 4 101#define TIF_MEMDIE 4
103#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ 102#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
104#define TIF_FREEZE 6 /* is freezing for suspend */ 103#define TIF_FREEZE 6 /* is freezing for suspend */
105#define TIF_IRQ_SYNC 7 /* sync pipeline stage */ 104#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
106#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ 105#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
106#define TIF_SINGLESTEP 9
107 107
108/* as above, but as bit values */ 108/* as above, but as bit values */
109#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 109#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
110#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 110#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
111#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 111#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
112#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
113#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 112#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
114#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 113#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
115#define _TIF_FREEZE (1<<TIF_FREEZE) 114#define _TIF_FREEZE (1<<TIF_FREEZE)
116#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC) 115#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
116#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
117#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
117 118
118#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ 119#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
119 120
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
index 589e937ed1eb..9ca7db844d10 100644
--- a/arch/blackfin/include/asm/time.h
+++ b/arch/blackfin/include/asm/time.h
@@ -23,9 +23,7 @@
23 */ 23 */
24 24
25#ifndef CONFIG_CPU_FREQ 25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1 26# define TIME_SCALE 1
27#define __bfin_cycles_off (0)
28#define __bfin_cycles_mod (0)
29#else 27#else
30/* 28/*
31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . 29 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -33,9 +31,16 @@
33 * adjust the Core Timer Presale Register. This way we don't lose time. 31 * adjust the Core Timer Presale Register. This way we don't lose time.
34 */ 32 */
35#define TIME_SCALE 4 33#define TIME_SCALE 4
34
35# ifdef CONFIG_CYCLES_CLOCKSOURCE
36extern unsigned long long __bfin_cycles_off; 36extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod; 37extern unsigned int __bfin_cycles_mod;
38# endif
39#endif
40
41#if defined(CONFIG_TICKSOURCE_CORETMR)
42extern void bfin_coretmr_init(void);
43extern void bfin_coretmr_clockevent_init(void);
38#endif 44#endif
39 45
40extern void __init setup_core_timer(void);
41#endif 46#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 00:40:02 -0400