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authorSonic Zhang <sonic.zhang@analog.com>2008-10-09 02:11:57 -0400
committerBryan Wu <cooloney@kernel.org>2008-10-09 02:11:57 -0400
commitf099f39acf7575eff3dee3c562cec4e592876c33 (patch)
tree57beb28f62712f061789626ad15eabbe31cc5286 /arch/blackfin/include/asm
parent8606801b0361e0f8520892c9bf524df89c35e690 (diff)
Blackfin arch: Make L2 SRAM cacheable
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r--arch/blackfin/include/asm/cplb.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index 05d6f05fb748..9e8b4035fcec 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -55,7 +55,13 @@
55#endif 55#endif
56 56
57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) 57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
58#define L2_MEMORY (CPLB_COMMON) 58#ifdef CONFIG_BFIN_L2_CACHEABLE
59#define L2_IMEMORY (SDRAM_IGENERIC)
60#define L2_DMEMORY (SDRAM_DGENERIC)
61#else
62#define L2_IMEMORY (CPLB_COMMON)
63#define L2_DMEMORY (CPLB_COMMON)
64#endif
59#define SDRAM_DNON_CHBL (CPLB_COMMON) 65#define SDRAM_DNON_CHBL (CPLB_COMMON)
60#define SDRAM_EBIU (CPLB_COMMON) 66#define SDRAM_EBIU (CPLB_COMMON)
61#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) 67#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)