diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 08:33:19 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-03-09 00:30:46 -0500 |
| commit | 0e64268ced7975ddcfed3e47a26b8df534f8e3ed (patch) | |
| tree | c421f7aa4b8373072f862d12c6cedaf6ca09c037 /arch/blackfin/include/asm | |
| parent | 360adee8a5c249f221de43d7d46073391359a4ba (diff) | |
Blackfin: merge common CAN defines into one headers
Rather than copy and paste the MMR defines and register layout,
consolidate everything in one place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm')
| -rw-r--r-- | arch/blackfin/include/asm/bfin_can.h | 725 |
1 files changed, 725 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h new file mode 100644 index 000000000000..eec0076a385b --- /dev/null +++ b/arch/blackfin/include/asm/bfin_can.h | |||
| @@ -0,0 +1,725 @@ | |||
| 1 | /* | ||
| 2 | * bfin_can.h - interface to Blackfin CANs | ||
| 3 | * | ||
| 4 | * Copyright 2004-2009 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_BFIN_CAN_H__ | ||
| 10 | #define __ASM_BFIN_CAN_H__ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * transmit and receive channels | ||
| 14 | */ | ||
| 15 | #define TRANSMIT_CHL 24 | ||
| 16 | #define RECEIVE_STD_CHL 0 | ||
| 17 | #define RECEIVE_EXT_CHL 4 | ||
| 18 | #define RECEIVE_RTR_CHL 8 | ||
| 19 | #define RECEIVE_EXT_RTR_CHL 12 | ||
| 20 | #define MAX_CHL_NUMBER 32 | ||
| 21 | |||
| 22 | /* | ||
| 23 | * All Blackfin system MMRs are padded to 32bits even if the register | ||
| 24 | * itself is only 16bits. So use a helper macro to streamline this. | ||
| 25 | */ | ||
| 26 | #define __BFP(m) u16 m; u16 __pad_##m | ||
| 27 | |||
| 28 | /* | ||
| 29 | * bfin can registers layout | ||
| 30 | */ | ||
| 31 | struct bfin_can_mask_regs { | ||
| 32 | __BFP(aml); | ||
| 33 | __BFP(amh); | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct bfin_can_channel_regs { | ||
| 37 | u16 data[8]; | ||
| 38 | __BFP(dlc); | ||
| 39 | __BFP(tsv); | ||
| 40 | __BFP(id0); | ||
| 41 | __BFP(id1); | ||
| 42 | }; | ||
| 43 | |||
| 44 | struct bfin_can_regs { | ||
| 45 | /* | ||
| 46 | * global control and status registers | ||
| 47 | */ | ||
| 48 | __BFP(mc1); /* offset 0x00 */ | ||
| 49 | __BFP(md1); /* offset 0x04 */ | ||
| 50 | __BFP(trs1); /* offset 0x08 */ | ||
| 51 | __BFP(trr1); /* offset 0x0c */ | ||
| 52 | __BFP(ta1); /* offset 0x10 */ | ||
| 53 | __BFP(aa1); /* offset 0x14 */ | ||
| 54 | __BFP(rmp1); /* offset 0x18 */ | ||
| 55 | __BFP(rml1); /* offset 0x1c */ | ||
| 56 | __BFP(mbtif1); /* offset 0x20 */ | ||
| 57 | __BFP(mbrif1); /* offset 0x24 */ | ||
| 58 | __BFP(mbim1); /* offset 0x28 */ | ||
| 59 | __BFP(rfh1); /* offset 0x2c */ | ||
| 60 | __BFP(opss1); /* offset 0x30 */ | ||
| 61 | u32 __pad1[3]; | ||
| 62 | __BFP(mc2); /* offset 0x40 */ | ||
| 63 | __BFP(md2); /* offset 0x44 */ | ||
| 64 | __BFP(trs2); /* offset 0x48 */ | ||
| 65 | __BFP(trr2); /* offset 0x4c */ | ||
| 66 | __BFP(ta2); /* offset 0x50 */ | ||
| 67 | __BFP(aa2); /* offset 0x54 */ | ||
| 68 | __BFP(rmp2); /* offset 0x58 */ | ||
| 69 | __BFP(rml2); /* offset 0x5c */ | ||
| 70 | __BFP(mbtif2); /* offset 0x60 */ | ||
| 71 | __BFP(mbrif2); /* offset 0x64 */ | ||
| 72 | __BFP(mbim2); /* offset 0x68 */ | ||
| 73 | __BFP(rfh2); /* offset 0x6c */ | ||
| 74 | __BFP(opss2); /* offset 0x70 */ | ||
| 75 | u32 __pad2[3]; | ||
| 76 | __BFP(clock); /* offset 0x80 */ | ||
| 77 | __BFP(timing); /* offset 0x84 */ | ||
| 78 | __BFP(debug); /* offset 0x88 */ | ||
| 79 | __BFP(status); /* offset 0x8c */ | ||
| 80 | __BFP(cec); /* offset 0x90 */ | ||
| 81 | __BFP(gis); /* offset 0x94 */ | ||
| 82 | __BFP(gim); /* offset 0x98 */ | ||
| 83 | __BFP(gif); /* offset 0x9c */ | ||
| 84 | __BFP(control); /* offset 0xa0 */ | ||
| 85 | __BFP(intr); /* offset 0xa4 */ | ||
| 86 | u32 __pad3[1]; | ||
| 87 | __BFP(mbtd); /* offset 0xac */ | ||
| 88 | __BFP(ewr); /* offset 0xb0 */ | ||
| 89 | __BFP(esr); /* offset 0xb4 */ | ||
| 90 | u32 __pad4[2]; | ||
| 91 | __BFP(ucreg); /* offset 0xc0 */ | ||
| 92 | __BFP(uccnt); /* offset 0xc4 */ | ||
| 93 | __BFP(ucrc); /* offset 0xc8 */ | ||
| 94 | __BFP(uccnf); /* offset 0xcc */ | ||
| 95 | u32 __pad5[12]; | ||
| 96 | |||
| 97 | /* | ||
| 98 | * channel(mailbox) mask and message registers | ||
| 99 | */ | ||
| 100 | struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */ | ||
| 101 | struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */ | ||
| 102 | }; | ||
| 103 | |||
| 104 | #undef __BFP | ||
| 105 | |||
| 106 | /* CAN_CONTROL Masks */ | ||
| 107 | #define SRS 0x0001 /* Software Reset */ | ||
| 108 | #define DNM 0x0002 /* Device Net Mode */ | ||
| 109 | #define ABO 0x0004 /* Auto-Bus On Enable */ | ||
| 110 | #define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ | ||
| 111 | #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ | ||
| 112 | #define SMR 0x0020 /* Sleep Mode Request */ | ||
| 113 | #define CSR 0x0040 /* CAN Suspend Mode Request */ | ||
| 114 | #define CCR 0x0080 /* CAN Configuration Mode Request */ | ||
| 115 | |||
| 116 | /* CAN_STATUS Masks */ | ||
| 117 | #define WT 0x0001 /* TX Warning Flag */ | ||
| 118 | #define WR 0x0002 /* RX Warning Flag */ | ||
| 119 | #define EP 0x0004 /* Error Passive Mode */ | ||
| 120 | #define EBO 0x0008 /* Error Bus Off Mode */ | ||
| 121 | #define SMA 0x0020 /* Sleep Mode Acknowledge */ | ||
| 122 | #define CSA 0x0040 /* Suspend Mode Acknowledge */ | ||
| 123 | #define CCA 0x0080 /* Configuration Mode Acknowledge */ | ||
| 124 | #define MBPTR 0x1F00 /* Mailbox Pointer */ | ||
| 125 | #define TRM 0x4000 /* Transmit Mode */ | ||
| 126 | #define REC 0x8000 /* Receive Mode */ | ||
| 127 | |||
| 128 | /* CAN_CLOCK Masks */ | ||
| 129 | #define BRP 0x03FF /* Bit-Rate Pre-Scaler */ | ||
| 130 | |||
| 131 | /* CAN_TIMING Masks */ | ||
| 132 | #define TSEG1 0x000F /* Time Segment 1 */ | ||
| 133 | #define TSEG2 0x0070 /* Time Segment 2 */ | ||
| 134 | #define SAM 0x0080 /* Sampling */ | ||
| 135 | #define SJW 0x0300 /* Synchronization Jump Width */ | ||
| 136 | |||
| 137 | /* CAN_DEBUG Masks */ | ||
| 138 | #define DEC 0x0001 /* Disable CAN Error Counters */ | ||
| 139 | #define DRI 0x0002 /* Disable CAN RX Input */ | ||
| 140 | #define DTO 0x0004 /* Disable CAN TX Output */ | ||
| 141 | #define DIL 0x0008 /* Disable CAN Internal Loop */ | ||
| 142 | #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ | ||
| 143 | #define MRB 0x0020 /* Mode Read Back Enable */ | ||
| 144 | #define CDE 0x8000 /* CAN Debug Enable */ | ||
| 145 | |||
| 146 | /* CAN_CEC Masks */ | ||
| 147 | #define RXECNT 0x00FF /* Receive Error Counter */ | ||
| 148 | #define TXECNT 0xFF00 /* Transmit Error Counter */ | ||
| 149 | |||
| 150 | /* CAN_INTR Masks */ | ||
| 151 | #define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ | ||
| 152 | #define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ | ||
| 153 | #define GIRQ 0x0004 /* Global Interrupt */ | ||
| 154 | #define SMACK 0x0008 /* Sleep Mode Acknowledge */ | ||
| 155 | #define CANTX 0x0040 /* CAN TX Bus Value */ | ||
| 156 | #define CANRX 0x0080 /* CAN RX Bus Value */ | ||
| 157 | |||
| 158 | /* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ | ||
| 159 | #define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ | ||
| 160 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ | ||
| 161 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ | ||
| 162 | #define BASEID 0x1FFC /* Base Identifier */ | ||
| 163 | #define IDE 0x2000 /* Identifier Extension */ | ||
| 164 | #define RTR 0x4000 /* Remote Frame Transmission Request */ | ||
| 165 | #define AME 0x8000 /* Acceptance Mask Enable */ | ||
| 166 | |||
| 167 | /* CAN_MBxx_TIMESTAMP Masks */ | ||
| 168 | #define TSV 0xFFFF /* Timestamp */ | ||
| 169 | |||
| 170 | /* CAN_MBxx_LENGTH Masks */ | ||
| 171 | #define DLC 0x000F /* Data Length Code */ | ||
| 172 | |||
| 173 | /* CAN_AMxxH and CAN_AMxxL Masks */ | ||
| 174 | #define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ | ||
| 175 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ | ||
| 176 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ | ||
| 177 | #define BASEID 0x1FFC /* Base Identifier */ | ||
| 178 | #define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ | ||
| 179 | #define FMD 0x4000 /* Full Mask Data Field Enable */ | ||
| 180 | #define FDF 0x8000 /* Filter On Data Field Enable */ | ||
| 181 | |||
| 182 | /* CAN_MC1 Masks */ | ||
| 183 | #define MC0 0x0001 /* Enable Mailbox 0 */ | ||
| 184 | #define MC1 0x0002 /* Enable Mailbox 1 */ | ||
| 185 | #define MC2 0x0004 /* Enable Mailbox 2 */ | ||
| 186 | #define MC3 0x0008 /* Enable Mailbox 3 */ | ||
| 187 | #define MC4 0x0010 /* Enable Mailbox 4 */ | ||
| 188 | #define MC5 0x0020 /* Enable Mailbox 5 */ | ||
| 189 | #define MC6 0x0040 /* Enable Mailbox 6 */ | ||
| 190 | #define MC7 0x0080 /* Enable Mailbox 7 */ | ||
| 191 | #define MC8 0x0100 /* Enable Mailbox 8 */ | ||
| 192 | #define MC9 0x0200 /* Enable Mailbox 9 */ | ||
| 193 | #define MC10 0x0400 /* Enable Mailbox 10 */ | ||
| 194 | #define MC11 0x0800 /* Enable Mailbox 11 */ | ||
| 195 | #define MC12 0x1000 /* Enable Mailbox 12 */ | ||
| 196 | #define MC13 0x2000 /* Enable Mailbox 13 */ | ||
| 197 | #define MC14 0x4000 /* Enable Mailbox 14 */ | ||
| 198 | #define MC15 0x8000 /* Enable Mailbox 15 */ | ||
| 199 | |||
| 200 | /* CAN_MC2 Masks */ | ||
| 201 | #define MC16 0x0001 /* Enable Mailbox 16 */ | ||
| 202 | #define MC17 0x0002 /* Enable Mailbox 17 */ | ||
| 203 | #define MC18 0x0004 /* Enable Mailbox 18 */ | ||
| 204 | #define MC19 0x0008 /* Enable Mailbox 19 */ | ||
| 205 | #define MC20 0x0010 /* Enable Mailbox 20 */ | ||
| 206 | #define MC21 0x0020 /* Enable Mailbox 21 */ | ||
| 207 | #define MC22 0x0040 /* Enable Mailbox 22 */ | ||
| 208 | #define MC23 0x0080 /* Enable Mailbox 23 */ | ||
| 209 | #define MC24 0x0100 /* Enable Mailbox 24 */ | ||
| 210 | #define MC25 0x0200 /* Enable Mailbox 25 */ | ||
| 211 | #define MC26 0x0400 /* Enable Mailbox 26 */ | ||
| 212 | #define MC27 0x0800 /* Enable Mailbox 27 */ | ||
| 213 | #define MC28 0x1000 /* Enable Mailbox 28 */ | ||
| 214 | #define MC29 0x2000 /* Enable Mailbox 29 */ | ||
| 215 | #define MC30 0x4000 /* Enable Mailbox 30 */ | ||
| 216 | #define MC31 0x8000 /* Enable Mailbox 31 */ | ||
| 217 | |||
| 218 | /* CAN_MD1 Masks */ | ||
| 219 | #define MD0 0x0001 /* Enable Mailbox 0 For Receive */ | ||
| 220 | #define MD1 0x0002 /* Enable Mailbox 1 For Receive */ | ||
| 221 | #define MD2 0x0004 /* Enable Mailbox 2 For Receive */ | ||
| 222 | #define MD3 0x0008 /* Enable Mailbox 3 For Receive */ | ||
| 223 | #define MD4 0x0010 /* Enable Mailbox 4 For Receive */ | ||
| 224 | #define MD5 0x0020 /* Enable Mailbox 5 For Receive */ | ||
| 225 | #define MD6 0x0040 /* Enable Mailbox 6 For Receive */ | ||
| 226 | #define MD7 0x0080 /* Enable Mailbox 7 For Receive */ | ||
| 227 | #define MD8 0x0100 /* Enable Mailbox 8 For Receive */ | ||
| 228 | #define MD9 0x0200 /* Enable Mailbox 9 For Receive */ | ||
| 229 | #define MD10 0x0400 /* Enable Mailbox 10 For Receive */ | ||
| 230 | #define MD11 0x0800 /* Enable Mailbox 11 For Receive */ | ||
| 231 | #define MD12 0x1000 /* Enable Mailbox 12 For Receive */ | ||
| 232 | #define MD13 0x2000 /* Enable Mailbox 13 For Receive */ | ||
| 233 | #define MD14 0x4000 /* Enable Mailbox 14 For Receive */ | ||
| 234 | #define MD15 0x8000 /* Enable Mailbox 15 For Receive */ | ||
| 235 | |||
| 236 | /* CAN_MD2 Masks */ | ||
| 237 | #define MD16 0x0001 /* Enable Mailbox 16 For Receive */ | ||
| 238 | #define MD17 0x0002 /* Enable Mailbox 17 For Receive */ | ||
| 239 | #define MD18 0x0004 /* Enable Mailbox 18 For Receive */ | ||
| 240 | #define MD19 0x0008 /* Enable Mailbox 19 For Receive */ | ||
| 241 | #define MD20 0x0010 /* Enable Mailbox 20 For Receive */ | ||
| 242 | #define MD21 0x0020 /* Enable Mailbox 21 For Receive */ | ||
| 243 | #define MD22 0x0040 /* Enable Mailbox 22 For Receive */ | ||
| 244 | #define MD23 0x0080 /* Enable Mailbox 23 For Receive */ | ||
| 245 | #define MD24 0x0100 /* Enable Mailbox 24 For Receive */ | ||
| 246 | #define MD25 0x0200 /* Enable Mailbox 25 For Receive */ | ||
| 247 | #define MD26 0x0400 /* Enable Mailbox 26 For Receive */ | ||
| 248 | #define MD27 0x0800 /* Enable Mailbox 27 For Receive */ | ||
| 249 | #define MD28 0x1000 /* Enable Mailbox 28 For Receive */ | ||
| 250 | #define MD29 0x2000 /* Enable Mailbox 29 For Receive */ | ||
| 251 | #define MD30 0x4000 /* Enable Mailbox 30 For Receive */ | ||
| 252 | #define MD31 0x8000 /* Enable Mailbox 31 For Receive */ | ||
| 253 | |||
| 254 | /* CAN_RMP1 Masks */ | ||
| 255 | #define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ | ||
| 256 | #define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ | ||
| 257 | #define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ | ||
| 258 | #define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ | ||
| 259 | #define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ | ||
| 260 | #define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ | ||
| 261 | #define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ | ||
| 262 | #define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ | ||
| 263 | #define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ | ||
| 264 | #define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ | ||
| 265 | #define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ | ||
| 266 | #define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ | ||
| 267 | #define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ | ||
| 268 | #define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ | ||
| 269 | #define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ | ||
| 270 | #define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ | ||
| 271 | |||
| 272 | /* CAN_RMP2 Masks */ | ||
| 273 | #define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ | ||
| 274 | #define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ | ||
| 275 | #define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ | ||
| 276 | #define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ | ||
| 277 | #define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ | ||
| 278 | #define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ | ||
| 279 | #define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ | ||
| 280 | #define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ | ||
| 281 | #define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ | ||
| 282 | #define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ | ||
| 283 | #define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ | ||
| 284 | #define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ | ||
| 285 | #define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ | ||
| 286 | #define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ | ||
| 287 | #define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ | ||
| 288 | #define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ | ||
| 289 | |||
| 290 | /* CAN_RML1 Masks */ | ||
| 291 | #define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ | ||
| 292 | #define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ | ||
| 293 | #define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ | ||
| 294 | #define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ | ||
| 295 | #define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ | ||
| 296 | #define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ | ||
| 297 | #define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ | ||
| 298 | #define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ | ||
| 299 | #define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ | ||
| 300 | #define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ | ||
| 301 | #define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ | ||
| 302 | #define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ | ||
| 303 | #define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ | ||
| 304 | #define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ | ||
| 305 | #define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ | ||
| 306 | #define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ | ||
| 307 | |||
| 308 | /* CAN_RML2 Masks */ | ||
| 309 | #define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ | ||
| 310 | #define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ | ||
| 311 | #define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ | ||
| 312 | #define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ | ||
| 313 | #define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ | ||
| 314 | #define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ | ||
| 315 | #define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ | ||
| 316 | #define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ | ||
| 317 | #define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ | ||
| 318 | #define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ | ||
| 319 | #define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ | ||
| 320 | #define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ | ||
| 321 | #define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ | ||
| 322 | #define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ | ||
| 323 | #define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ | ||
| 324 | #define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ | ||
| 325 | |||
| 326 | /* CAN_OPSS1 Masks */ | ||
| 327 | #define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ | ||
| 328 | #define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ | ||
| 329 | #define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ | ||
| 330 | #define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ | ||
| 331 | #define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ | ||
| 332 | #define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ | ||
| 333 | #define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ | ||
| 334 | #define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ | ||
| 335 | #define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ | ||
| 336 | #define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ | ||
| 337 | #define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ | ||
| 338 | #define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ | ||
| 339 | #define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ | ||
| 340 | #define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ | ||
| 341 | #define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ | ||
| 342 | #define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ | ||
| 343 | |||
| 344 | /* CAN_OPSS2 Masks */ | ||
| 345 | #define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ | ||
| 346 | #define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ | ||
| 347 | #define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ | ||
| 348 | #define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ | ||
| 349 | #define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ | ||
| 350 | #define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ | ||
| 351 | #define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ | ||
| 352 | #define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ | ||
| 353 | #define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ | ||
| 354 | #define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ | ||
| 355 | #define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ | ||
| 356 | #define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ | ||
| 357 | #define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ | ||
| 358 | #define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ | ||
| 359 | #define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ | ||
| 360 | #define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ | ||
| 361 | |||
| 362 | /* CAN_TRR1 Masks */ | ||
| 363 | #define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ | ||
| 364 | #define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ | ||
| 365 | #define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ | ||
| 366 | #define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ | ||
| 367 | #define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ | ||
| 368 | #define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ | ||
| 369 | #define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ | ||
| 370 | #define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ | ||
| 371 | #define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ | ||
| 372 | #define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ | ||
| 373 | #define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ | ||
| 374 | #define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ | ||
| 375 | #define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ | ||
| 376 | #define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ | ||
| 377 | #define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ | ||
| 378 | #define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ | ||
| 379 | |||
| 380 | /* CAN_TRR2 Masks */ | ||
| 381 | #define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ | ||
| 382 | #define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ | ||
| 383 | #define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ | ||
| 384 | #define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ | ||
| 385 | #define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ | ||
| 386 | #define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ | ||
| 387 | #define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ | ||
| 388 | #define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ | ||
| 389 | #define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ | ||
| 390 | #define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ | ||
| 391 | #define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ | ||
| 392 | #define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ | ||
| 393 | #define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ | ||
| 394 | #define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ | ||
| 395 | #define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ | ||
| 396 | #define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ | ||
| 397 | |||
| 398 | /* CAN_TRS1 Masks */ | ||
| 399 | #define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ | ||
| 400 | #define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ | ||
| 401 | #define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ | ||
| 402 | #define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ | ||
| 403 | #define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ | ||
| 404 | #define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ | ||
| 405 | #define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ | ||
| 406 | #define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ | ||
| 407 | #define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ | ||
| 408 | #define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ | ||
| 409 | #define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ | ||
| 410 | #define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ | ||
| 411 | #define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ | ||
| 412 | #define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ | ||
| 413 | #define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ | ||
| 414 | #define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ | ||
| 415 | |||
| 416 | /* CAN_TRS2 Masks */ | ||
| 417 | #define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ | ||
| 418 | #define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ | ||
| 419 | #define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ | ||
| 420 | #define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ | ||
| 421 | #define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ | ||
| 422 | #define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ | ||
| 423 | #define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ | ||
| 424 | #define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ | ||
| 425 | #define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ | ||
| 426 | #define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ | ||
| 427 | #define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ | ||
| 428 | #define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ | ||
| 429 | #define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ | ||
| 430 | #define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ | ||
| 431 | #define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ | ||
| 432 | #define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ | ||
| 433 | |||
| 434 | /* CAN_AA1 Masks */ | ||
| 435 | #define AA0 0x0001 /* Aborted Message In Mailbox 0 */ | ||
| 436 | #define AA1 0x0002 /* Aborted Message In Mailbox 1 */ | ||
| 437 | #define AA2 0x0004 /* Aborted Message In Mailbox 2 */ | ||
| 438 | #define AA3 0x0008 /* Aborted Message In Mailbox 3 */ | ||
| 439 | #define AA4 0x0010 /* Aborted Message In Mailbox 4 */ | ||
| 440 | #define AA5 0x0020 /* Aborted Message In Mailbox 5 */ | ||
| 441 | #define AA6 0x0040 /* Aborted Message In Mailbox 6 */ | ||
| 442 | #define AA7 0x0080 /* Aborted Message In Mailbox 7 */ | ||
| 443 | #define AA8 0x0100 /* Aborted Message In Mailbox 8 */ | ||
| 444 | #define AA9 0x0200 /* Aborted Message In Mailbox 9 */ | ||
| 445 | #define AA10 0x0400 /* Aborted Message In Mailbox 10 */ | ||
| 446 | #define AA11 0x0800 /* Aborted Message In Mailbox 11 */ | ||
| 447 | #define AA12 0x1000 /* Aborted Message In Mailbox 12 */ | ||
| 448 | #define AA13 0x2000 /* Aborted Message In Mailbox 13 */ | ||
| 449 | #define AA14 0x4000 /* Aborted Message In Mailbox 14 */ | ||
| 450 | #define AA15 0x8000 /* Aborted Message In Mailbox 15 */ | ||
| 451 | |||
| 452 | /* CAN_AA2 Masks */ | ||
| 453 | #define AA16 0x0001 /* Aborted Message In Mailbox 16 */ | ||
| 454 | #define AA17 0x0002 /* Aborted Message In Mailbox 17 */ | ||
| 455 | #define AA18 0x0004 /* Aborted Message In Mailbox 18 */ | ||
| 456 | #define AA19 0x0008 /* Aborted Message In Mailbox 19 */ | ||
| 457 | #define AA20 0x0010 /* Aborted Message In Mailbox 20 */ | ||
| 458 | #define AA21 0x0020 /* Aborted Message In Mailbox 21 */ | ||
| 459 | #define AA22 0x0040 /* Aborted Message In Mailbox 22 */ | ||
| 460 | #define AA23 0x0080 /* Aborted Message In Mailbox 23 */ | ||
| 461 | #define AA24 0x0100 /* Aborted Message In Mailbox 24 */ | ||
| 462 | #define AA25 0x0200 /* Aborted Message In Mailbox 25 */ | ||
| 463 | #define AA26 0x0400 /* Aborted Message In Mailbox 26 */ | ||
| 464 | #define AA27 0x0800 /* Aborted Message In Mailbox 27 */ | ||
| 465 | #define AA28 0x1000 /* Aborted Message In Mailbox 28 */ | ||
| 466 | #define AA29 0x2000 /* Aborted Message In Mailbox 29 */ | ||
| 467 | #define AA30 0x4000 /* Aborted Message In Mailbox 30 */ | ||
| 468 | #define AA31 0x8000 /* Aborted Message In Mailbox 31 */ | ||
| 469 | |||
| 470 | /* CAN_TA1 Masks */ | ||
| 471 | #define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ | ||
| 472 | #define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ | ||
| 473 | #define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ | ||
| 474 | #define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ | ||
| 475 | #define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ | ||
| 476 | #define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ | ||
| 477 | #define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ | ||
| 478 | #define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ | ||
| 479 | #define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ | ||
| 480 | #define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ | ||
| 481 | #define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ | ||
| 482 | #define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ | ||
| 483 | #define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ | ||
| 484 | #define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ | ||
| 485 | #define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ | ||
| 486 | #define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ | ||
| 487 | |||
| 488 | /* CAN_TA2 Masks */ | ||
| 489 | #define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ | ||
| 490 | #define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ | ||
| 491 | #define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ | ||
| 492 | #define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ | ||
| 493 | #define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ | ||
| 494 | #define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ | ||
| 495 | #define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ | ||
| 496 | #define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ | ||
| 497 | #define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ | ||
| 498 | #define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ | ||
| 499 | #define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ | ||
| 500 | #define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ | ||
| 501 | #define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ | ||
| 502 | #define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ | ||
| 503 | #define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ | ||
| 504 | #define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ | ||
| 505 | |||
| 506 | /* CAN_MBTD Masks */ | ||
| 507 | #define TDPTR 0x001F /* Mailbox To Temporarily Disable */ | ||
| 508 | #define TDA 0x0040 /* Temporary Disable Acknowledge */ | ||
| 509 | #define TDR 0x0080 /* Temporary Disable Request */ | ||
| 510 | |||
| 511 | /* CAN_RFH1 Masks */ | ||
| 512 | #define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ | ||
| 513 | #define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ | ||
| 514 | #define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ | ||
| 515 | #define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ | ||
| 516 | #define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ | ||
| 517 | #define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ | ||
| 518 | #define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ | ||
| 519 | #define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ | ||
| 520 | #define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ | ||
| 521 | #define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ | ||
| 522 | #define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ | ||
| 523 | #define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ | ||
| 524 | #define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ | ||
| 525 | #define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ | ||
| 526 | #define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ | ||
| 527 | #define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ | ||
| 528 | |||
| 529 | /* CAN_RFH2 Masks */ | ||
| 530 | #define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ | ||
| 531 | #define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ | ||
| 532 | #define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ | ||
| 533 | #define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ | ||
| 534 | #define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ | ||
| 535 | #define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ | ||
| 536 | #define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ | ||
| 537 | #define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ | ||
| 538 | #define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ | ||
| 539 | #define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ | ||
| 540 | #define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ | ||
| 541 | #define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ | ||
| 542 | #define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ | ||
| 543 | #define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ | ||
| 544 | #define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ | ||
| 545 | #define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ | ||
| 546 | |||
| 547 | /* CAN_MBTIF1 Masks */ | ||
| 548 | #define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ | ||
| 549 | #define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ | ||
| 550 | #define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ | ||
| 551 | #define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ | ||
| 552 | #define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ | ||
| 553 | #define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ | ||
| 554 | #define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ | ||
| 555 | #define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ | ||
| 556 | #define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ | ||
| 557 | #define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ | ||
| 558 | #define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ | ||
| 559 | #define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ | ||
| 560 | #define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ | ||
| 561 | #define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ | ||
| 562 | #define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ | ||
| 563 | #define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ | ||
| 564 | |||
| 565 | /* CAN_MBTIF2 Masks */ | ||
| 566 | #define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ | ||
| 567 | #define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ | ||
| 568 | #define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ | ||
| 569 | #define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ | ||
| 570 | #define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ | ||
| 571 | #define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ | ||
| 572 | #define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ | ||
| 573 | #define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ | ||
| 574 | #define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ | ||
| 575 | #define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ | ||
| 576 | #define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ | ||
| 577 | #define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ | ||
| 578 | #define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ | ||
| 579 | #define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ | ||
| 580 | #define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ | ||
| 581 | #define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ | ||
| 582 | |||
| 583 | /* CAN_MBRIF1 Masks */ | ||
| 584 | #define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ | ||
| 585 | #define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ | ||
| 586 | #define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ | ||
| 587 | #define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ | ||
| 588 | #define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ | ||
| 589 | #define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ | ||
| 590 | #define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ | ||
| 591 | #define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ | ||
| 592 | #define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ | ||
| 593 | #define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ | ||
| 594 | #define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ | ||
| 595 | #define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ | ||
| 596 | #define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ | ||
| 597 | #define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ | ||
| 598 | #define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ | ||
| 599 | #define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ | ||
| 600 | |||
| 601 | /* CAN_MBRIF2 Masks */ | ||
| 602 | #define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ | ||
| 603 | #define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ | ||
| 604 | #define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ | ||
| 605 | #define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ | ||
| 606 | #define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ | ||
| 607 | #define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ | ||
| 608 | #define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ | ||
| 609 | #define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ | ||
| 610 | #define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ | ||
| 611 | #define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ | ||
| 612 | #define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ | ||
| 613 | #define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ | ||
| 614 | #define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ | ||
| 615 | #define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ | ||
| 616 | #define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ | ||
| 617 | #define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ | ||
| 618 | |||
| 619 | /* CAN_MBIM1 Masks */ | ||
| 620 | #define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ | ||
| 621 | #define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ | ||
| 622 | #define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ | ||
| 623 | #define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ | ||
| 624 | #define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ | ||
| 625 | #define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ | ||
| 626 | #define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ | ||
| 627 | #define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ | ||
| 628 | #define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ | ||
| 629 | #define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ | ||
| 630 | #define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ | ||
| 631 | #define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ | ||
| 632 | #define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ | ||
| 633 | #define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ | ||
| 634 | #define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ | ||
| 635 | #define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ | ||
| 636 | |||
| 637 | /* CAN_MBIM2 Masks */ | ||
| 638 | #define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ | ||
| 639 | #define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ | ||
| 640 | #define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ | ||
| 641 | #define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ | ||
| 642 | #define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ | ||
| 643 | #define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ | ||
| 644 | #define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ | ||
| 645 | #define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ | ||
| 646 | #define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ | ||
| 647 | #define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ | ||
| 648 | #define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ | ||
| 649 | #define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ | ||
| 650 | #define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ | ||
| 651 | #define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ | ||
| 652 | #define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ | ||
| 653 | #define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ | ||
| 654 | |||
| 655 | /* CAN_GIM Masks */ | ||
| 656 | #define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ | ||
| 657 | #define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ | ||
| 658 | #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ | ||
| 659 | #define BOIM 0x0008 /* Enable Bus Off Interrupt */ | ||
| 660 | #define WUIM 0x0010 /* Enable Wake-Up Interrupt */ | ||
| 661 | #define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ | ||
| 662 | #define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ | ||
| 663 | #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ | ||
| 664 | #define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ | ||
| 665 | #define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ | ||
| 666 | #define ADIM 0x0400 /* Enable Access Denied Interrupt */ | ||
| 667 | |||
| 668 | /* CAN_GIS Masks */ | ||
| 669 | #define EWTIS 0x0001 /* TX Error Count IRQ Status */ | ||
| 670 | #define EWRIS 0x0002 /* RX Error Count IRQ Status */ | ||
| 671 | #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ | ||
| 672 | #define BOIS 0x0008 /* Bus Off IRQ Status */ | ||
| 673 | #define WUIS 0x0010 /* Wake-Up IRQ Status */ | ||
| 674 | #define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ | ||
| 675 | #define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ | ||
| 676 | #define RMLIS 0x0080 /* RX Message Lost IRQ Status */ | ||
| 677 | #define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ | ||
| 678 | #define EXTIS 0x0200 /* External Trigger Output IRQ Status */ | ||
| 679 | #define ADIS 0x0400 /* Access Denied IRQ Status */ | ||
| 680 | |||
| 681 | /* CAN_GIF Masks */ | ||
| 682 | #define EWTIF 0x0001 /* TX Error Count IRQ Flag */ | ||
| 683 | #define EWRIF 0x0002 /* RX Error Count IRQ Flag */ | ||
| 684 | #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ | ||
| 685 | #define BOIF 0x0008 /* Bus Off IRQ Flag */ | ||
| 686 | #define WUIF 0x0010 /* Wake-Up IRQ Flag */ | ||
| 687 | #define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ | ||
| 688 | #define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ | ||
| 689 | #define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ | ||
| 690 | #define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ | ||
| 691 | #define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ | ||
| 692 | #define ADIF 0x0400 /* Access Denied IRQ Flag */ | ||
| 693 | |||
| 694 | /* CAN_UCCNF Masks */ | ||
| 695 | #define UCCNF 0x000F /* Universal Counter Mode */ | ||
| 696 | #define UC_STAMP 0x0001 /* Timestamp Mode */ | ||
| 697 | #define UC_WDOG 0x0002 /* Watchdog Mode */ | ||
| 698 | #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ | ||
| 699 | #define UC_ERROR 0x0006 /* CAN Error Frame Count */ | ||
| 700 | #define UC_OVER 0x0007 /* CAN Overload Frame Count */ | ||
| 701 | #define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ | ||
| 702 | #define UC_AA 0x0009 /* TX Abort Count */ | ||
| 703 | #define UC_TA 0x000A /* TX Successful Count */ | ||
| 704 | #define UC_REJECT 0x000B /* RX Message Rejected Count */ | ||
| 705 | #define UC_RML 0x000C /* RX Message Lost Count */ | ||
| 706 | #define UC_RX 0x000D /* Total Successful RX Messages Count */ | ||
| 707 | #define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ | ||
| 708 | #define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ | ||
| 709 | #define UCRC 0x0020 /* Universal Counter Reload/Clear */ | ||
| 710 | #define UCCT 0x0040 /* Universal Counter CAN Trigger */ | ||
| 711 | #define UCE 0x0080 /* Universal Counter Enable */ | ||
| 712 | |||
| 713 | /* CAN_ESR Masks */ | ||
| 714 | #define ACKE 0x0004 /* Acknowledge Error */ | ||
| 715 | #define SER 0x0008 /* Stuff Error */ | ||
| 716 | #define CRCE 0x0010 /* CRC Error */ | ||
| 717 | #define SA0 0x0020 /* Stuck At Dominant Error */ | ||
| 718 | #define BEF 0x0040 /* Bit Error Flag */ | ||
| 719 | #define FER 0x0080 /* Form Error Flag */ | ||
| 720 | |||
| 721 | /* CAN_EWR Masks */ | ||
| 722 | #define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ | ||
| 723 | #define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ | ||
| 724 | |||
| 725 | #endif | ||